1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | ␉#define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | ␉#define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | ␉#define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | #define XEON "Xeon"␊ |
22 | #define CORE_I3 "Core(TM) i3"␊ |
23 | #define CORE_I5 "Core(TM) i5"␊ |
24 | #define CORE_I7 "Core(TM) i7"␊ |
25 | ␊ |
26 | ␊ |
27 | bool getProcessorInformationExternalClock(returnType *value)␊ |
28 | {␊ |
29 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
30 | ␉{␊ |
31 | ␉␉switch (Platform.CPU.Family)␊ |
32 | ␉␉{␊ |
33 | ␉␉␉case 0x06:␊ |
34 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
35 | ␉␉␉␉{␊ |
36 | ␉␉␉␉␉// set external clock to 0 for SANDY␊ |
37 | ␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
38 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
39 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
40 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
41 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
42 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
43 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
44 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
45 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊ |
46 | ␊ |
47 | ␉␉␉␉␉␉value->word = 0;␊ |
48 | ␉␉␉␉␉␉break;␊ |
49 | ␉␉␉␉␉default:␊ |
50 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
51 | ␉␉␉␉␉␉break;␊ |
52 | ␉␉␉␉}␊ |
53 | ␉␉␉␉break;␊ |
54 | ␊ |
55 | ␉␉␉default:␊ |
56 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
57 | ␉␉␉␉break;␊ |
58 | ␉␉}␊ |
59 | ␉}␊ |
60 | ␉else␊ |
61 | ␉{␊ |
62 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
63 | ␉}␊ |
64 | ␊ |
65 | ␉return true;␊ |
66 | }␊ |
67 | ␊ |
68 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
69 | {␊ |
70 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
71 | ␉return true;␊ |
72 | }␊ |
73 | ␊ |
74 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
75 | {␊ |
76 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
77 | ␉{␊ |
78 | ␉␉switch (Platform.CPU.Family)␊ |
79 | ␉␉{␊ |
80 | ␉␉␉case 0x06:␊ |
81 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
82 | ␉␉␉␉{␊ |
83 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
84 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊ |
85 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
86 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
87 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
88 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
89 | ␉␉␉␉␉␉return false;␊ |
90 | ␊ |
91 | ␉␉␉␉␉case 0x19:␊ |
92 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
93 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
94 | ␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␊ |
95 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
96 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
97 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
98 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
99 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
100 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
101 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
102 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
103 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
104 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊ |
105 | ␉␉␉␉␉{␊ |
106 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
107 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
108 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
109 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
110 | ␉␉␉␉␉␉unsigned int i;␊ |
111 | ␉␉␉␉␉␉␊ |
112 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
113 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
114 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊ |
115 | ␉␉␉␉␉␉{␊ |
116 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
117 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
118 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
119 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
120 | ␉␉␉␉␉␉␉␊ |
121 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
122 | ␉␉␉␉␉␉␉{␊ |
123 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊ |
124 | ␉␉␉␉␉␉␉}␊ |
125 | ␉␉␉␉␉␉}␊ |
126 | ␊ |
127 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
128 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
129 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
130 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
131 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
132 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
133 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
134 | ␉␉␉␉␉␉{␊ |
135 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
136 | ␉␉␉␉␉␉}␊ |
137 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
138 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
139 | ␉␉␉␉␉␉return true;␊ |
140 | ␉␉␉␉␉}␊ |
141 | ␉␉␉␉␉break;␊ |
142 | ␊ |
143 | ␉␉␉␉␉default:␊ |
144 | ␉␉␉␉␉␉break;␊ |
145 | ␉␉␉␉}␊ |
146 | ␉␉␉␉break;␊ |
147 | ␊ |
148 | ␉␉␉default:␊ |
149 | ␉␉␉␉break;␊ |
150 | ␉␉}␊ |
151 | ␉}␊ |
152 | ␊ |
153 | ␉return false; //Unsupported CPU type␊ |
154 | }␊ |
155 | ␊ |
156 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
157 | {␊ |
158 | ␉if (Platform.CPU.NoCores >= 4)␊ |
159 | ␉{␊ |
160 | ␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊ |
161 | ␉}␊ |
162 | ␉else if (Platform.CPU.NoCores == 1)␊ |
163 | ␉{␊ |
164 | ␉␉return 0x201;␉// 513 - Core Duo␊ |
165 | ␉};␊ |
166 | ␉␊ |
167 | ␉return 0x301;␉␉// 769 - Core 2 Duo␊ |
168 | }␊ |
169 | ␊ |
170 | bool getSMBOemProcessorType(returnType *value)␊ |
171 | {␊ |
172 | ␉static bool done = false;␊ |
173 | ␊ |
174 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
175 | ␊ |
176 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
177 | ␉{␊ |
178 | ␉␉if (!done)␊ |
179 | ␉␉{␊ |
180 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
181 | ␉␉␉done = true;␊ |
182 | ␉␉}␊ |
183 | ␊ |
184 | ␉␉switch (Platform.CPU.Family)␊ |
185 | ␉␉{␊ |
186 | ␉␉␉case 0x0F:␊ |
187 | ␉␉␉case 0x06:␊ |
188 | ␊ |
189 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
190 | ␉␉␉␉{␊ |
191 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
192 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊ |
193 | ␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊ |
194 | ␉␉␉␉␉case CPUID_MODEL_NOCONA:␊ |
195 | ␊ |
196 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
197 | ␉␉␉␉␉␉{␊ |
198 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
199 | ␉␉␉␉␉␉␉return true;␊ |
200 | ␉␉␉␉␉␉}␊ |
201 | ␊ |
202 | ␉␉␉␉␉␉return true;␊ |
203 | ␊ |
204 | ␉␉␉␉␉case CPUID_MODEL_PRESLER:␊ |
205 | ␉␉␉␉␉case CPUID_MODEL_CELERON:␊ |
206 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
207 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
208 | ␉␉␉␉␉␉return true;␊ |
209 | ␊ |
210 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
211 | ␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
212 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
213 | ␊ |
214 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
215 | ␉␉␉␉␉␉{␊ |
216 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
217 | ␉␉␉␉␉␉␉return true;␊ |
218 | ␉␉␉␉␉␉}␊ |
219 | ␊ |
220 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
221 | ␉␉␉␉␉␉{␊ |
222 | ␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊ |
223 | ␉␉␉␉␉␉␉return true;␊ |
224 | ␉␉␉␉␉␉}␊ |
225 | ␉␉␉␉␉␉else␊ |
226 | ␉␉␉␉␉␉{␊ |
227 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊ |
228 | ␉␉␉␉␉␉␉return true;␊ |
229 | ␉␉␉␉␉␉}␊ |
230 | ␊ |
231 | ␉␉␉␉␉␉return true;␊ |
232 | ␊ |
233 | ␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
234 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
235 | ␊ |
236 | ␉␉␉␉␉␉return true;␊ |
237 | ␊ |
238 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊ |
239 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
240 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
241 | ␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
242 | ␊ |
243 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
244 | ␉␉␉␉␉␉{␊ |
245 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
246 | ␉␉␉␉␉␉␉return true;␊ |
247 | ␉␉␉␉␉␉}␊ |
248 | ␊ |
249 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
250 | ␉␉␉␉␉␉{␊ |
251 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
252 | ␉␉␉␉␉␉␉return true;␊ |
253 | ␉␉␉␉␉␉}␊ |
254 | ␊ |
255 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
256 | ␉␉␉␉␉␉{␊ |
257 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
258 | ␉␉␉␉␉␉␉return true;␊ |
259 | ␉␉␉␉␉␉}␊ |
260 | ␊ |
261 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
262 | ␉␉␉␉␉␉{␊ |
263 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
264 | ␉␉␉␉␉␉␉return true;␊ |
265 | ␉␉␉␉␉␉}␊ |
266 | ␊ |
267 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
268 | ␉␉␉␉␉␉{␊ |
269 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊ |
270 | ␉␉␉␉␉␉␉return true;␊ |
271 | ␉␉␉␉␉␉}␊ |
272 | ␊ |
273 | ␉␉␉␉␉␉return true;␊ |
274 | ␊ |
275 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
276 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
277 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
278 | ␊ |
279 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
280 | ␉␉␉␉␉␉{␊ |
281 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
282 | ␉␉␉␉␉␉␉return true;␊ |
283 | ␉␉␉␉␉␉}␊ |
284 | ␊ |
285 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
286 | ␉␉␉␉␉␉{␊ |
287 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
288 | ␉␉␉␉␉␉␉return true;␊ |
289 | ␉␉␉␉␉␉}␊ |
290 | ␊ |
291 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
292 | ␉␉␉␉␉␉{␊ |
293 | ␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊ |
294 | ␉␉␉␉␉␉␉return true;␊ |
295 | ␉␉␉␉␉␉}␊ |
296 | ␊ |
297 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
298 | ␉␉␉␉␉␉{␊ |
299 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
300 | ␉␉␉␉␉␉␉return true;␊ |
301 | ␉␉␉␉␉␉}␊ |
302 | ␊ |
303 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
304 | ␉␉␉␉␉␉{␊ |
305 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊ |
306 | ␉␉␉␉␉␉␉return true;␊ |
307 | ␉␉␉␉␉␉}␊ |
308 | ␊ |
309 | ␉␉␉␉␉␉return true;␊ |
310 | ␊ |
311 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
312 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
313 | ␊ |
314 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
315 | ␉␉␉␉␉␉{␊ |
316 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
317 | ␉␉␉␉␉␉␉return true;␊ |
318 | ␉␉␉␉␉␉}␊ |
319 | ␊ |
320 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
321 | ␉␉␉␉␉␉{␊ |
322 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
323 | ␉␉␉␉␉␉␉return true;␊ |
324 | ␉␉␉␉␉␉}␊ |
325 | ␊ |
326 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
327 | ␉␉␉␉␉␉{␊ |
328 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
329 | ␉␉␉␉␉␉␉return true;␊ |
330 | ␉␉␉␉␉␉}␊ |
331 | ␊ |
332 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
333 | ␉␉␉␉␉␉{␊ |
334 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
335 | ␉␉␉␉␉␉␉return true;␊ |
336 | ␉␉␉␉␉␉}␊ |
337 | ␊ |
338 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
339 | ␉␉␉␉␉␉{␊ |
340 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊ |
341 | ␉␉␉␉␉␉␉return true;␊ |
342 | ␉␉␉␉␉␉}␊ |
343 | ␊ |
344 | ␉␉␉␉␉␉return true;␊ |
345 | ␊ |
346 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
347 | ␊ |
348 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
349 | ␉␉␉␉␉␉{␊ |
350 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
351 | ␉␉␉␉␉␉␉return true;␊ |
352 | ␉␉␉␉␉␉}␊ |
353 | ␊ |
354 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
355 | ␉␉␉␉␉␉{␊ |
356 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊ |
357 | ␉␉␉␉␉␉␉return true;␊ |
358 | ␉␉␉␉␉␉}␊ |
359 | ␊ |
360 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
361 | ␉␉␉␉␉␉{␊ |
362 | ␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊ |
363 | ␉␉␉␉␉␉␉return true;␊ |
364 | ␉␉␉␉␉␉}␊ |
365 | ␊ |
366 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
367 | ␉␉␉␉␉␉{␊ |
368 | ␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊ |
369 | ␉␉␉␉␉␉␉return true;␊ |
370 | ␉␉␉␉␉␉}␊ |
371 | ␊ |
372 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
373 | ␉␉␉␉␉␉{␊ |
374 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊ |
375 | ␉␉␉␉␉␉␉return true;␊ |
376 | ␉␉␉␉␉␉}␊ |
377 | ␊ |
378 | ␉␉␉␉␉␉return true;␊ |
379 | ␊ |
380 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␉␉␉// 0x3D -␊ |
381 | ␊ |
382 | ␉␉␉␉␉␉value->word = 0x606;␉␉␉// 1542␊ |
383 | ␉␉␉␉␉␉return true;␊ |
384 | ␊ |
385 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊ |
386 | ␊ |
387 | ␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊ |
388 | ␉␉␉␉␉␉return true;␊ |
389 | ␊ |
390 | ␉␉␉␉␉case CPUID_MODEL_ATOM_3700:␉␉␉// 0x37 -␊ |
391 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊ |
392 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊ |
393 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
394 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␉␉␉// 0x46 -␊ |
395 | ␊ |
396 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
397 | ␉␉␉␉␉␉{␊ |
398 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
399 | ␉␉␉␉␉␉␉return true;␊ |
400 | ␉␉␉␉␉␉}␊ |
401 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
402 | ␉␉␉␉␉␉{␊ |
403 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
404 | ␉␉␉␉␉␉␉return true;␊ |
405 | ␉␉␉␉␉␉}␊ |
406 | ␊ |
407 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
408 | ␉␉␉␉␉␉{␊ |
409 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
410 | ␉␉␉␉␉␉␉return true;␊ |
411 | ␉␉␉␉␉␉}␊ |
412 | ␊ |
413 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
414 | ␉␉␉␉␉␉{␊ |
415 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
416 | ␉␉␉␉␉␉␉return true;␊ |
417 | ␉␉␉␉␉␉}␊ |
418 | ␊ |
419 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
420 | ␉␉␉␉␉␉{␊ |
421 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊ |
422 | ␉␉␉␉␉␉␉return true;␊ |
423 | ␉␉␉␉␉␉}␊ |
424 | ␊ |
425 | ␉␉␉␉␉␉return true;␊ |
426 | ␊ |
427 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
428 | ␊ |
429 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
430 | ␉␉␉␉␉␉return true;␊ |
431 | ␊ |
432 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
433 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
434 | ␊ |
435 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
436 | ␉␉␉␉␉␉return true;␊ |
437 | ␊ |
438 | ␉␉␉␉␉default:␊ |
439 | ␊ |
440 | ␉␉␉␉␉␉return true;␊ |
441 | ␉␉␉␉␉␉break; // Unsupported CPU type␊ |
442 | ␉␉␉␉}␊ |
443 | ␉␉␉␉break;␊ |
444 | ␊ |
445 | ␉␉␉default:␊ |
446 | ␉␉␉␉break;␊ |
447 | ␉␉}␊ |
448 | ␉}␊ |
449 | /*␊ |
450 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_AMD) // AMD␊ |
451 | ␉{␊ |
452 | ␉␉value->word = simpleGetSMBOemProcessorType();␊ |
453 | ␉␉return true;␊ |
454 | ␉}␊ |
455 | */␊ |
456 | ␉return false;␊ |
457 | }␊ |
458 | ␊ |
459 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
460 | {␊ |
461 | ␉static int idx = -1;␊ |
462 | ␉int␉map;␊ |
463 | ␊ |
464 | ␉if (!bootInfo->memDetect)␊ |
465 | ␉{␊ |
466 | ␉␉return false;␊ |
467 | ␉}␊ |
468 | ␊ |
469 | ␉idx++;␊ |
470 | ␉if (idx < MAX_RAM_SLOTS)␊ |
471 | ␉{␊ |
472 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
473 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
474 | ␉␉{␊ |
475 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
476 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
477 | ␉␉␉return true;␊ |
478 | ␉␉}␊ |
479 | ␉}␊ |
480 | ␊ |
481 | ␉value->byte = 2; // means Unknown␊ |
482 | ␉return true;␊ |
483 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
484 | //␉return true;␊ |
485 | }␊ |
486 | ␊ |
487 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
488 | {␊ |
489 | ␉value->word = 0xFFFF;␊ |
490 | ␉return true;␊ |
491 | }␊ |
492 | ␊ |
493 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
494 | {␊ |
495 | ␉static int idx = -1;␊ |
496 | ␉int␉map;␊ |
497 | ␊ |
498 | ␉if (!bootInfo->memDetect)␊ |
499 | ␉{␊ |
500 | ␉␉return false;␊ |
501 | ␉}␊ |
502 | ␊ |
503 | ␉idx++;␊ |
504 | ␉if (idx < MAX_RAM_SLOTS)␊ |
505 | ␉{␊ |
506 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
507 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
508 | ␉␉{␊ |
509 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
510 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
511 | ␉␉␉return true;␊ |
512 | ␉␉}␊ |
513 | ␉}␊ |
514 | ␊ |
515 | ␉value->dword = 0; // means Unknown␊ |
516 | ␉return true;␊ |
517 | //␉value->dword = 800;␊ |
518 | //␉return true;␊ |
519 | }␊ |
520 | ␊ |
521 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
522 | {␊ |
523 | ␉static int idx = -1;␊ |
524 | ␉int␉map;␊ |
525 | ␊ |
526 | ␉if (!bootInfo->memDetect)␊ |
527 | ␉{␊ |
528 | ␉␉return false;␊ |
529 | ␉}␊ |
530 | ␊ |
531 | ␉idx++;␊ |
532 | ␉if (idx < MAX_RAM_SLOTS)␊ |
533 | ␉{␊ |
534 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
535 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
536 | ␉␉{␊ |
537 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
538 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
539 | ␉␉␉return true;␊ |
540 | ␉␉}␊ |
541 | ␉}␊ |
542 | ␊ |
543 | ␉value->string = NOT_AVAILABLE;␊ |
544 | ␉return true;␊ |
545 | }␊ |
546 | ␊ |
547 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
548 | {␊ |
549 | ␉static int idx = -1;␊ |
550 | ␉int␉map;␊ |
551 | ␊ |
552 | ␉if (!bootInfo->memDetect)␊ |
553 | ␉{␊ |
554 | ␉␉return false;␊ |
555 | ␉}␊ |
556 | ␊ |
557 | ␉idx++;␊ |
558 | ␊ |
559 | ␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
560 | ␊ |
561 | ␉if (idx < MAX_RAM_SLOTS)␊ |
562 | ␉{␊ |
563 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
564 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
565 | ␉␉{␊ |
566 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
567 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
568 | ␉␉␉return true;␊ |
569 | ␉␉}␊ |
570 | ␉}␊ |
571 | ␊ |
572 | ␉value->string = NOT_AVAILABLE;␊ |
573 | ␉return true;␊ |
574 | }␊ |
575 | ␊ |
576 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
577 | {␊ |
578 | ␉static int idx = -1;␊ |
579 | ␉int␉map;␊ |
580 | ␊ |
581 | ␉if (!bootInfo->memDetect)␊ |
582 | ␉{␊ |
583 | ␉␉return false;␊ |
584 | ␉}␊ |
585 | ␊ |
586 | ␉idx++;␊ |
587 | ␉if (idx < MAX_RAM_SLOTS)␊ |
588 | ␉{␊ |
589 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
590 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
591 | ␉␉{␊ |
592 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
593 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
594 | ␉␉␉return true;␊ |
595 | ␉␉}␊ |
596 | ␉}␊ |
597 | ␊ |
598 | ␉value->string = NOT_AVAILABLE;␊ |
599 | ␉return true;␊ |
600 | }␊ |
601 | ␊ |
602 | ␊ |
603 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
604 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
605 | static const char * const SMTAG = "_SM_";␊ |
606 | static const char* const DMITAG = "_DMI_";␊ |
607 | ␊ |
608 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
609 | {␊ |
610 | ␉SMBEntryPoint␉*smbios;␊ |
611 | ␉/*␊ |
612 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
613 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
614 | ␉ */␊ |
615 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
616 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊ |
617 | ␉{␊ |
618 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
619 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
620 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
621 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
622 | ␉␉{␊ |
623 | ␉␉␉return smbios;␊ |
624 | ␉ }␊ |
625 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
626 | ␉}␊ |
627 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
628 | ␉pause();␊ |
629 | ␉return NULL;␊ |
630 | }␊ |
631 | ␊ |
632 | |