1 | /*␊ |
2 | * platform.h␊ |
3 | * AsereBLN: reworked and extended␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
8 | #define __LIBSAIO_PLATFORM_H␊ |
9 | ␊ |
10 | //#include "libsaio.h"␊ |
11 | ␊ |
12 | extern bool platformCPUFeature(uint32_t);␊ |
13 | extern void scan_platform(void);␊ |
14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
15 | ␊ |
16 | /* CPUID index into cpuid_raw */␊ |
17 | #define CPUID_0␉␉␉␉0␊ |
18 | #define CPUID_1␉␉␉␉1␊ |
19 | #define CPUID_2␉␉␉␉2␊ |
20 | #define CPUID_3␉␉␉␉3␊ |
21 | #define CPUID_4␉␉␉␉4␊ |
22 | #define CPUID_5␉␉␉␉5␊ |
23 | #define CPUID_6␉␉␉␉6␊ |
24 | #define CPUID_80␉␉␉7␊ |
25 | #define CPUID_81␉␉␉8␊ |
26 | #define CPUID_85␉␉␉9␊ |
27 | #define CPUID_86␉␉␉10␊ |
28 | #define CPUID_87␉␉␉11␊ |
29 | #define CPUID_88␉␉␉12␊ |
30 | #define CPUID_MAX␉␉␉13␊ |
31 | ␊ |
32 | #define CPUID_MODEL_ANY␉␉␉0x00␊ |
33 | #define CPUID_MODEL_UNKNOWN␉␉0x01␊ |
34 | #define CPUID_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊ |
35 | #define CPUID_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona/Paxville, Irwindale (90nm)␊ |
36 | #define CPUID_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊ |
37 | #define CPUID_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias Pentium M (130nm)␊ |
38 | #define CPUID_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan Pentium M, Celeron M (90nm)␊ |
39 | #define CPUID_MODEL_YONAH␉␉0x0E␉␉␉// Sossaman, Yonah␊ |
40 | #define CPUID_MODEL_MEROM␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊ |
41 | #define CPUID_MODEL_CONROE␉␉0x0F␉␉␉//␊ |
42 | #define CPUID_MODEL_CELERON␉␉0x16␉␉␉// Merom, Conroe (65nm), Celeron (45nm)␊ |
43 | #define CPUID_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊ |
44 | #define CPUID_MODEL_WOLFDALE␉␉0x17␉␉␉// Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx␊ |
45 | #define CPUID_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊ |
46 | #define CPUID_MODEL_ATOM␉␉0x1C␉␉␉// Pineview, Bonnell␊ |
47 | #define CPUID_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊ |
48 | #define CPUID_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊ |
49 | #define CPUID_MODEL_CLARKDALE␉␉0x1F␉␉␉// Havendale, Auburndale␊ |
50 | #define CPUID_MODEL_DALES␉␉0x25␉␉␉// Clarkdale, Arrandale␊ |
51 | #define CPUID_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊ |
52 | #define CPUID_MODEL_LINCROFT␉␉0x27␉␉␉// Bonnell␊ |
53 | #define CPUID_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊ |
54 | #define CPUID_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊ |
55 | #define CPUID_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊ |
56 | #define CPUID_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊ |
57 | #define CPUID_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊ |
58 | //#define CPUID_MODEL_BONNELL_ATOM␉0x35␉␉␉// Atom Family Bonnell␊ |
59 | #define CPUID_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview / Saltwell␊ |
60 | #define CPUID_MODEL_ATOM_3700␉␉0x37␉␉␉// Atom E3000, Z3000 Atom Silvermont␊ |
61 | #define CPUID_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊ |
62 | #define CPUID_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊ |
63 | #define CPUID_MODEL_HASWELL_U5␉␉0x3D␉␉␉// Haswell U5 5th generation Broadwell, Core M / Core-AVX2␊ |
64 | #define CPUID_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊ |
65 | #define CPUID_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E)␊ |
66 | //#define CPUID_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊ |
67 | #define CPUID_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT, 4th gen Core, Xeon E3-12xx v3␊ |
68 | #define CPUID_MODEL_HASWELL_ULX␉␉0x46␉␉␉// Crystal Well, 4th gen Core, Xeon E3-12xx v3␊ |
69 | //#define CPUID_MODEL_␉␉␉0x4A␉␉␉// Future Atom E3000, Z3000 silvermont / atom␊ |
70 | #define CPUID_MODEL_AVOTON␉␉0x4D␉␉␉// Silvermont/Avoton Atom C2000␊ |
71 | //#define CPUID_MODEL_␉␉␉0x4E␉␉␉// Future Core␊ |
72 | #define CPUID_MODEL_BRODWELL_SVR␉0x4F␉␉␉// Broadwell Server␊ |
73 | #define CPUID_MODEL_BRODWELL_MSVR␉0x56␉␉␉// Broadwell Micro Server, Future Xeon␊ |
74 | //#define CPUID_MODEL_␉␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000␊ |
75 | //#define CPUID_MODEL_␉␉␉0x5D␉␉␉// Silvermont, Future Atom E3000, Z3000␊ |
76 | ␊ |
77 | /* CPUID Vendor */␊ |
78 | #define␉CPUID_VID_INTEL␉␉␉"GenuineIntel"␊ |
79 | #define␉CPUID_VID_AMD␉␉␉"AuthenticAMD"␊ |
80 | ␊ |
81 | #define CPUID_VENDOR_INTEL␉␉0x756E6547␊ |
82 | #define CPUID_VENDOR_AMD␉␉0x68747541␊ |
83 | ␊ |
84 | /* This spells out "GenuineIntel". */␊ |
85 | //#define is_intel \␊ |
86 | // ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69␊ |
87 | ␊ |
88 | /* This spells out "AuthenticAMD". */␊ |
89 | //#define is_amd \␊ |
90 | // ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65␊ |
91 | ␊ |
92 | /* Unknown CPU */␊ |
93 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Typ"␊ |
94 | ␊ |
95 | //definitions from Apple XNU␊ |
96 | ␊ |
97 | /* CPU defines */␊ |
98 | #define bit(n)␉␉␉␉(1ULL << (n))␊ |
99 | #define bitmask(h,l)␉␉␉((bit(h) | (bit(h)-1)) & ~(bit(l)-1))␊ |
100 | #define bitfield(x,h,l)␉␉␉(((x) & bitmask(h,l)) >> l)␊ |
101 | #define hbit(n)␉␉␉␉(1ULL << ((n)+32))␊ |
102 | #define min(a,b)␉␉␉((a) < (b) ? (a) : (b))␊ |
103 | #define quad32(hi,lo)␉␉␉((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))␊ |
104 | #define quad64(hi,lo)␉␉␉((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))␊ |
105 | ␊ |
106 | /*␊ |
107 | * The CPUID_FEATURE_XXX values define 64-bit values␊ |
108 | * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
109 | */␊ |
110 | #define CPUID_FEATURE_FPU␉␉bit(0) /* Floating point unit on-chip */␊ |
111 | #define CPUID_FEATURE_VME␉␉bit(1) /* Virtual Mode Extension */␊ |
112 | #define CPUID_FEATURE_DE␉␉bit(2) /* Debugging Extension */␊ |
113 | #define CPUID_FEATURE_PSE␉␉bit(3) /* Page Size Extension */␊ |
114 | #define CPUID_FEATURE_TSC␉␉bit(4) /* Time Stamp Counter */␊ |
115 | #define CPUID_FEATURE_MSR␉␉bit(5) /* Model Specific Registers */␊ |
116 | #define CPUID_FEATURE_PAE␉␉bit(6) /* Physical Address Extension */␊ |
117 | #define CPUID_FEATURE_MCE␉␉bit(7) /* Machine Check Exception */␊ |
118 | #define CPUID_FEATURE_CX8␉␉bit(8) /* CMPXCHG8B */␊ |
119 | #define CPUID_FEATURE_APIC␉␉bit(9) /* On-chip APIC */␊ |
120 | #define CPUID_FEATURE_SEP␉␉bit(11) /* Fast System Call */␊ |
121 | #define CPUID_FEATURE_MTRR␉␉bit(12) /* Memory Type Range Register */␊ |
122 | #define CPUID_FEATURE_PGE␉␉bit(13) /* Page Global Enable */␊ |
123 | #define CPUID_FEATURE_MCA␉␉bit(14) /* Machine Check Architecture */␊ |
124 | #define CPUID_FEATURE_CMOV␉␉bit(15) /* Conditional Move Instruction */␊ |
125 | #define CPUID_FEATURE_PAT␉␉bit(16) /* Page Attribute Table */␊ |
126 | #define CPUID_FEATURE_PSE36␉␉bit(17) /* 36-bit Page Size Extension */␊ |
127 | #define CPUID_FEATURE_PSN␉␉bit(18) /* Processor Serial Number */␊ |
128 | #define CPUID_FEATURE_CLFSH␉␉bit(19) /* CLFLUSH Instruction supported */␊ |
129 | #define CPUID_FEATURE_DS␉␉bit(21) /* Debug Store */␊ |
130 | #define CPUID_FEATURE_ACPI␉␉bit(22) /* Thermal monitor and Clock Ctrl */␊ |
131 | #define CPUID_FEATURE_MMX␉␉bit(23) /* MMX supported */␊ |
132 | #define CPUID_FEATURE_FXSR␉␉bit(24) /* Fast floating pt save/restore */␊ |
133 | #define CPUID_FEATURE_SSE␉␉bit(25) /* Streaming SIMD extensions */␊ |
134 | #define CPUID_FEATURE_SSE2␉␉bit(26) /* Streaming SIMD extensions 2 */␊ |
135 | #define CPUID_FEATURE_SS␉␉bit(27) /* Self-Snoop */␊ |
136 | #define CPUID_FEATURE_HTT␉␉bit(28) /* Hyper-Threading Technology */␊ |
137 | #define CPUID_FEATURE_TM␉␉bit(29) /* Thermal Monitor (TM1) */␊ |
138 | #define CPUID_FEATURE_PBE␉␉bit(31) /* Pend Break Enable */␊ |
139 | ␊ |
140 | #define CPUID_FEATURE_SSE3␉␉hbit(0) /* Streaming SIMD extensions 3 */␊ |
141 | #define CPUID_FEATURE_PCLMULQDQ␉␉hbit(1) /* PCLMULQDQ Instruction */␊ |
142 | #define CPUID_FEATURE_DTES64␉␉hbit(2) /* 64-bit DS layout */␊ |
143 | #define CPUID_FEATURE_MONITOR␉␉hbit(3) /* Monitor/mwait */␊ |
144 | #define CPUID_FEATURE_DSCPL␉␉hbit(4) /* Debug Store CPL */␊ |
145 | #define CPUID_FEATURE_VMX␉␉hbit(5) /* VMX */␊ |
146 | #define CPUID_FEATURE_SMX␉␉hbit(6) /* SMX */␊ |
147 | #define CPUID_FEATURE_EST␉␉hbit(7) /* Enhanced SpeedsTep (GV3) */␊ |
148 | #define CPUID_FEATURE_TM2␉␉hbit(8) /* Thermal Monitor 2 */␊ |
149 | #define CPUID_FEATURE_SSSE3␉␉hbit(9) /* Supplemental SSE3 instructions */␊ |
150 | #define CPUID_FEATURE_CID␉␉hbit(10) /* L1 Context ID */␊ |
151 | #define CPUID_FEATURE_SEGLIM64␉␉hbit(11) /* 64-bit segment limit checking */␊ |
152 | #define CPUID_FEATURE_FMA␉␉hbit(12) /* Fused-Multiply-Add support */␊ |
153 | #define CPUID_FEATURE_CX16␉␉hbit(13) /* CmpXchg16b instruction */␊ |
154 | #define CPUID_FEATURE_xTPR␉␉hbit(14) /* Send Task PRiority msgs */␊ |
155 | #define CPUID_FEATURE_PDCM␉␉hbit(15) /* Perf/Debug Capability MSR */␊ |
156 | ␊ |
157 | #define CPUID_FEATURE_PCID␉␉hbit(17) /* ASID-PCID support */␊ |
158 | #define CPUID_FEATURE_DCA␉␉hbit(18) /* Direct Cache Access */␊ |
159 | #define CPUID_FEATURE_SSE4_1␉␉hbit(19) /* Streaming SIMD extensions 4.1 */␊ |
160 | #define CPUID_FEATURE_SSE4_2␉␉hbit(20) /* Streaming SIMD extensions 4.2 */␊ |
161 | #define CPUID_FEATURE_x2APIC␉␉hbit(21) /* Extended APIC Mode */␊ |
162 | #define CPUID_FEATURE_MOVBE␉␉hbit(22) /* MOVBE instruction */␊ |
163 | #define CPUID_FEATURE_POPCNT␉␉hbit(23) /* POPCNT instruction */␊ |
164 | #define CPUID_FEATURE_TSCTMR␉␉hbit(24) /* TSC deadline timer */␊ |
165 | #define CPUID_FEATURE_AES␉␉hbit(25) /* AES instructions */␊ |
166 | #define CPUID_FEATURE_XSAVE␉␉hbit(26) /* XSAVE instructions */␊ |
167 | #define CPUID_FEATURE_OSXSAVE␉␉hbit(27) /* XGETBV/XSETBV instructions */␊ |
168 | #define CPUID_FEATURE_AVX1_0␉␉hbit(28) /* AVX 1.0 instructions */␊ |
169 | #define CPUID_FEATURE_F16C␉␉hbit(29) /* Float16 convert instructions */␊ |
170 | #define CPUID_FEATURE_RDRAND␉␉hbit(30) /* RDRAND instruction */␊ |
171 | #define CPUID_FEATURE_VMM␉␉hbit(31) /* VMM (Hypervisor) present */␊ |
172 | ␊ |
173 | /*␊ |
174 | * Leaf 7, subleaf 0 additional features.␊ |
175 | * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
176 | */␊ |
177 | #define CPUID_LEAF7_FEATURE_RDWRFSGS␉bit(0)␉/* FS/GS base read/write */␊ |
178 | #define CPUID_LEAF7_FEATURE_TSCOFF␉bit(1)␉/* TSC thread offset */␊ |
179 | #define CPUID_LEAF7_FEATURE_BMI1␉bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
180 | #define CPUID_LEAF7_FEATURE_HLE␉␉bit(4)␉/* Hardware Lock Elision*/␊ |
181 | #define CPUID_LEAF7_FEATURE_AVX2␉bit(5)␉/* AVX2 Instructions */␊ |
182 | #define CPUID_LEAF7_FEATURE_SMEP␉bit(7)␉/* Supervisor Mode Execute Protect */␊ |
183 | #define CPUID_LEAF7_FEATURE_BMI2␉bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
184 | #define CPUID_LEAF7_FEATURE_ENFSTRG␉bit(9)␉/* ENhanced Fast STRinG copy */␊ |
185 | #define CPUID_LEAF7_FEATURE_INVPCID␉bit(10)␉/* INVPCID intruction, TDB */␊ |
186 | #define CPUID_LEAF7_FEATURE_RTM␉␉bit(11)␉/* TBD */␊ |
187 | ␊ |
188 | /*␊ |
189 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
190 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
191 | */␊ |
192 | #define CPUID_EXTFEATURE_SYSCALL␉bit(11)␉/* SYSCALL/sysret */␊ |
193 | #define CPUID_EXTFEATURE_XD␉␉bit(20)␉/* eXecute Disable */␊ |
194 | ␊ |
195 | #define CPUID_EXTFEATURE_1GBPAGE␉bit(26)␉/* 1GB pages support */␊ |
196 | #define CPUID_EXTFEATURE_RDTSCP␉␉bit(27)␉/* RDTSCP */␊ |
197 | #define CPUID_EXTFEATURE_EM64T␉␉bit(29)␉/* Extended Mem 64 Technology */␊ |
198 | ␊ |
199 | ␊ |
200 | #define CPUID_EXTFEATURE_LAHF␉␉hbit(0)␉/* LAFH/SAHF instructions */␊ |
201 | ␊ |
202 | /*␊ |
203 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
204 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
205 | */␊ |
206 | #define CPUID_EXTFEATURE_TSCI␉␉bit(8)␉/* TSC Invariant */␊ |
207 | ␊ |
208 | #define␉CPUID_CACHE_SIZE␉␉16␉/* Number of descriptor values */␊ |
209 | ␊ |
210 | #define CPUID_MWAIT_EXTENSION␉␉bit(0)␉/* enumeration of WMAIT extensions */␊ |
211 | #define CPUID_MWAIT_BREAK␉␉bit(1)␉/* interrupts are break events␉ */␊ |
212 | ␊ |
213 | //-- processor type -> p_type:␊ |
214 | #define PT_OEM␉␉␉␉0x00␉// Intel Original OEM Processor;␊ |
215 | #define PT_OD␉␉␉␉0x01 ␉// Intel Over Drive Processor;␊ |
216 | #define PT_DUAL␉␉␉␉0x02␉// Intel Dual Processor;␊ |
217 | #define PT_RES␉␉␉␉0x03␉// Intel Reserved;␊ |
218 | ␊ |
219 | /* Known MSR registers */␊ |
220 | #define MSR_IA32_PLATFORM_ID␉␉0x0017␊ |
221 | #define IA32_APIC_BASE␉␉␉0x001B /* used also for AMD */␊ |
222 | #define MSR_CORE_THREAD_COUNT␉␉0x0035␉/* limited use - not for Penryn or older */␊ |
223 | #define IA32_TSC_ADJUST␉␉␉0x003B␊ |
224 | #define MSR_IA32_BIOS_SIGN_ID␉␉0x008B␉/* microcode version */␊ |
225 | #define MSR_FSB_FREQ␉␉␉0x00CD␉/* limited use - not for i7 */␊ |
226 | #define␉MSR_PLATFORM_INFO␉␉0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
227 | /* turbo for penryn */␊ |
228 | #define MSR_PKG_CST_CONFIG_CONTROL␉0x00E2␉␉// sandy and ivy␊ |
229 | #define MSR_PMG_IO_CAPTURE_BASE␉␉0x00E4␊ |
230 | #define IA32_MPERF␉␉␉0x00E7␉␉// TSC in C0 only␊ |
231 | #define IA32_APERF␉␉␉0x00E8␉␉// actual clocks in C0␊ |
232 | #define MSR_IA32_EXT_CONFIG␉␉0x00EE␉␉// limited use - not for i7␊ |
233 | #define MSR_FLEX_RATIO␉␉␉0x0194␉␉// limited use - not for Penryn or older␊ |
234 | ␉␉␉␉␉␉//see no value on most CPUs␊ |
235 | #define␉MSR_IA32_PERF_STATUS␉␉0x0198␊ |
236 | #define MSR_IA32_PERF_CONTROL␉␉0x0199␊ |
237 | #define MSR_IA32_CLOCK_MODULATION␉0x019A␊ |
238 | #define MSR_THERMAL_STATUS␉␉0x019C␊ |
239 | #define MSR_IA32_MISC_ENABLE␉␉0x01A0␊ |
240 | #define MSR_THERMAL_TARGET␉␉0x01A2␉␉// TjMax limited use - not for Penryn or older␊ |
241 | #define MSR_MISC_PWR_MGMT␉␉0x01AA␊ |
242 | #define MSR_TURBO_RATIO_LIMIT␉␉0x01AD␉␉// limited use - not for Penryn or older␊ |
243 | ␊ |
244 | #define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊ |
245 | #define MSR_PACKAGE_THERM_STATUS␉0x01B1␊ |
246 | #define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊ |
247 | #define MSR_POWER_CTL␉␉␉0x01FC␉␉// MSR 000001FC 0000-0000-0004-005F␊ |
248 | ␊ |
249 | // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊ |
250 | #define MSR_RAPL_POWER_UNIT␉␉0x606␉␉// R/O␊ |
251 | //MSR 00000606 0000-0000-000A-1003␊ |
252 | #define MSR_PKGC3_IRTL␉␉␉0x60A␉␉// RW time limit to go C3␊ |
253 | // bit 15 = 1 -- the value valid for C-state PM␊ |
254 | #define MSR_PKGC6_IRTL␉␉␉0x60B␉␉// RW time limit to go C6␊ |
255 | //MSR 0000060B 0000-0000-0000-8854␊ |
256 | //Valid + 010=1024ns + 0x54=84mks␊ |
257 | #define MSR_PKGC7_IRTL␉␉␉0x60C␉␉// RW time limit to go C7␊ |
258 | //MSR 0000060C 0000-0000-0000-8854␊ |
259 | #define MSR_PKG_C2_RESIDENCY␉␉0x60D␉␉// same as TSC but in C2 only␊ |
260 | ␊ |
261 | #define MSR_PKG_RAPL_POWER_LIMIT␉0x610␉␉//MSR 00000610 0000-A580-0000-8960␊ |
262 | #define MSR_PKG_ENERGY_STATUS␉␉0x611␉␉//MSR 00000611 0000-0000-3212-A857␊ |
263 | #define MSR_PKG_POWER_INFO␉␉0x614␉␉//MSR 00000614 0000-0000-01E0-02F8␊ |
264 | ␊ |
265 | // Sandy Bridge IA (Core) domain MSR's.␊ |
266 | #define MSR_PP0_POWER_LIMIT␉␉0x638␊ |
267 | #define MSR_PP0_ENERGY_STATUS␉␉0x639␊ |
268 | #define MSR_PP0_POLICY␉␉␉0x63A␊ |
269 | #define MSR_PP0_PERF_STATUS␉␉0x63B␊ |
270 | ␊ |
271 | // Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).␊ |
272 | #define MSR_PP1_POWER_LIMIT␉␉0x640␊ |
273 | #define MSR_PP1_ENERGY_STATUS␉ ␉0x641␊ |
274 | //MSR 00000641 0000-0000-0000-0000␊ |
275 | #define MSR_PP1_POLICY␉␉␉0x642␊ |
276 | ␊ |
277 | // JakeTown only Memory MSR's.␊ |
278 | #define MSR_PKG_PERF_STATUS␉␉0x613 ␊ |
279 | #define MSR_DRAM_POWER_LIMIT␉ ␉0x618␊ |
280 | #define MSR_DRAM_ENERGY_STATUS␉␉0x619␊ |
281 | #define MSR_DRAM_PERF_STATUS␉␉0x61B␊ |
282 | #define MSR_DRAM_POWER_INFO␉␉0x61C␊ |
283 | ␊ |
284 | //IVY_BRIDGE␊ |
285 | #define MSR_CONFIG_TDP_NOMINAL␉␉0x648␊ |
286 | #define MSR_CONFIG_TDP_LEVEL1␉␉0x649␊ |
287 | #define MSR_CONFIG_TDP_LEVEL2␉␉0x64A␊ |
288 | #define MSR_CONFIG_TDP_CONTROL␉␉0x64B␉␉// write once to lock␊ |
289 | #define MSR_TURBO_ACTIVATION_RATIO␉0x64C␊ |
290 | ␊ |
291 | /* AMD Defined MSRs */␊ |
292 | #define MSR_K6_EFER␉␉␉0xC0000080␊ |
293 | #define MSR_K6_STAR␉␉␉0xC0000081␊ |
294 | #define MSR_K6_WHCR␉␉␉0xC0000082␊ |
295 | #define MSR_K6_UWCCR␉␉␉0xC0000085␊ |
296 | #define MSR_K6_EPMR␉␉␉0xC0000086␊ |
297 | #define MSR_K6_PSOR␉␉␉0xC0000087␊ |
298 | #define MSR_K6_PFIR␉␉␉0xC0000088␊ |
299 | ␊ |
300 | #define MSR_K7_EVNTSEL0␉␉␉0xC0010000␊ |
301 | #define MSR_K7_PERFCTR0␉␉␉0xC0010004␊ |
302 | #define MSR_K7_HWCR␉␉␉0xC0010015␊ |
303 | #define MSR_K7_CLK_CTL␉␉␉0xC001001b␊ |
304 | #define MSR_K7_FID_VID_CTL␉␉0xC0010041␊ |
305 | ␊ |
306 | #define K8_FIDVID_STATUS␉␉0xC0010042␊ |
307 | #define K10_COFVID_LIMIT␉␉0xC0010061␉// max enabled p-state (msr >> 4) & 7␊ |
308 | #define K10_COFVID_CONTROL␉␉0xC0010062␉// switch to p-state␊ |
309 | #define K10_PSTATE_STATUS␉␉0xC0010064␊ |
310 | #define K10_COFVID_STATUS␉␉0xC0010071␉// current p-state (msr >> 16) & 7␊ |
311 | ␊ |
312 | #define MSR_AMD_MPERF␉␉␉0x000000E7␊ |
313 | #define MSR_AMD_APERF␉␉␉0x000000E8␊ |
314 | ␊ |
315 | #define DEFAULT_FSB␉␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
316 | ␊ |
317 | // DFE: This constant comes from older xnu:␊ |
318 | #define CLKNUM␉␉␉␉1193182␉␉/* formerly 1193167 */␊ |
319 | ␊ |
320 | /* CPU Features */␊ |
321 | #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊ |
322 | #define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊ |
323 | #define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊ |
324 | #define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊ |
325 | #define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊ |
326 | #define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊ |
327 | #define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊ |
328 | #define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊ |
329 | #define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊ |
330 | #define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊ |
331 | ␊ |
332 | /* SMBIOS Memory Types */ ␊ |
333 | #define SMB_MEM_TYPE_UNDEFINED␉␉0␊ |
334 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
335 | #define SMB_MEM_TYPE_UNKNOWN␉␉2␊ |
336 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
337 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
338 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
339 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
340 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
341 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
342 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
343 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
344 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
345 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
346 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
347 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
348 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
349 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
350 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
351 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
352 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
353 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
354 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
355 | #define SMB_MEM_TYPE_DDR4␉␉26␊ |
356 | ␊ |
357 | /* Memory Configuration Types */ ␊ |
358 | #define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊ |
359 | #define SMB_MEM_CHANNEL_SINGLE␉␉1␊ |
360 | #define SMB_MEM_CHANNEL_DUAL␉␉2␊ |
361 | #define SMB_MEM_CHANNEL_TRIPLE␉␉3␊ |
362 | ␊ |
363 | /* Maximum number of ram slots */␊ |
364 | #define MAX_RAM_SLOTS␉␉␉8␊ |
365 | ␊ |
366 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
367 | ␊ |
368 | /* Maximum number of SPD bytes */␊ |
369 | #define MAX_SPD_SIZE␉␉␉256␊ |
370 | ␊ |
371 | /* Size of SMBIOS UUID in bytes */␊ |
372 | #define UUID_LEN␉␉␉16␊ |
373 | ␊ |
374 | typedef struct _RamSlotInfo_t␊ |
375 | {␊ |
376 | ␉uint32_t␉␉ModuleSize;␉␉␉// Size of Module in MB␊ |
377 | ␉uint32_t␉␉Frequency;␉␉␉// in Mhz␊ |
378 | ␉const char*␉␉Vendor;␊ |
379 | ␉const char*␉␉PartNo;␊ |
380 | ␉const char*␉␉SerialNo;␊ |
381 | ␉char*␉␉␉spd;␉␉␉␉// SPD Dump␊ |
382 | ␉bool␉␉␉InUse;␊ |
383 | ␉uint8_t␉␉␉Type;␊ |
384 | ␉uint8_t␉␉␉BankConnections;␉␉// table type 6, see (3.3.7)␊ |
385 | ␉uint8_t␉␉␉BankConnCnt;␊ |
386 | } RamSlotInfo_t;␊ |
387 | ␊ |
388 | //==============================================================================␊ |
389 | ␊ |
390 | typedef struct _PlatformInfo_t␊ |
391 | {␊ |
392 | ␉struct CPU {␊ |
393 | ␉␉uint32_t␉␉Features;␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
394 | ␉␉uint32_t␉␉Vendor;␉␉␉// Vendor␊ |
395 | ␉␉uint32_t␉␉CoresPerPackage;␊ |
396 | ␉␉uint32_t␉␉LogicalPerPackage;␊ |
397 | ␉␉uint32_t␉␉Signature;␉␉// Processor Signature␊ |
398 | ␉␉uint32_t␉␉Stepping;␉␉// Stepping␊ |
399 | ␉␉uint32_t␉␉Model;␉␉␉// Model␊ |
400 | ␉␉//uint32_t␉␉Type;␉␉␉// Processor Type␊ |
401 | ␉␉uint32_t␉␉ExtModel;␉␉// Extended Model␊ |
402 | ␉␉uint32_t␉␉Family;␉␉␉// Family␊ |
403 | ␉␉uint32_t␉␉ExtFamily;␉␉// Extended Family␊ |
404 | ␉␉uint32_t␉␉NoCores;␉␉// No Cores per Package␊ |
405 | ␉␉uint32_t␉␉NoThreads;␉␉// Threads per Package␊ |
406 | ␉␉uint8_t␉␉␉MaxCoef;␉␉// Max Multiplier␊ |
407 | ␉␉uint8_t␉␉␉MaxDiv;␉␉␉// Min Multiplier␊ |
408 | ␉␉uint8_t␉␉␉CurrCoef;␉␉// Current Multiplier␊ |
409 | ␉␉uint8_t␉␉␉CurrDiv;␊ |
410 | ␉␉uint64_t␉␉TSCFrequency;␉␉// TSC Frequency Hz␊ |
411 | ␉␉uint64_t␉␉FSBFrequency;␉␉// FSB Frequency Hz␊ |
412 | ␉␉uint64_t␉␉CPUFrequency;␉␉// CPU Frequency Hz␊ |
413 | ␉␉uint32_t␉␉MaxRatio;␉␉// Max Bus Ratio␊ |
414 | ␉␉uint32_t␉␉MinRatio;␉␉// Min Bus Ratio␊ |
415 | ␉␉char␉␉␉BrandString[48];␉// 48 Byte Branding String␊ |
416 | ␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
417 | ␊ |
418 | ␉} CPU;␊ |
419 | ␊ |
420 | ␉struct DMI␊ |
421 | ␉{␊ |
422 | ␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots populated by SMBIOS␊ |
423 | ␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊ |
424 | ␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊ |
425 | ␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
426 | ␉} DMI;␊ |
427 | ␉struct RAM␊ |
428 | ␉{␊ |
429 | ␉␉uint64_t␉␉Frequency;␉␉// Ram Frequency␊ |
430 | ␉␉uint32_t␉␉Divider;␉␉// Memory divider␊ |
431 | ␉␉uint8_t␉␉␉CAS;␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
432 | ␉␉uint8_t␉␉␉TRC;␊ |
433 | ␉␉uint8_t␉␉␉TRP;␊ |
434 | ␉␉uint8_t␉␉␉RAS;␊ |
435 | ␉␉uint8_t␉␉␉Channels;␉␉// Channel Configuration Single,Dual, Triple or Quad␊ |
436 | ␉␉uint8_t␉␉␉NoSlots;␉␉// Maximum no of slots available␊ |
437 | ␉␉uint8_t␉␉␉Type;␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
438 | ␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉␉// Information about each slot␊ |
439 | ␉} RAM;␊ |
440 | ␊ |
441 | ␉uint8_t␉␉␉␉Type;␉␉␉// system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊ |
442 | ␉uint8_t␉␉␉␉*UUID;␉␉␉// system-id (SMBIOS Table 1: system uuid)␊ |
443 | ␉uint32_t␉␉␉HWSignature;␉␉// machine-signature (FACS: Hardware Signature)␊ |
444 | } PlatformInfo_t;␊ |
445 | ␊ |
446 | extern PlatformInfo_t Platform;␊ |
447 | ␊ |
448 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
449 | |