1 | /*␊ |
2 | * resolution.h␊ |
3 | * ␊ |
4 | *␉NOTE: I don't beleive this code is production ready / should be in trunk␊ |
5 | * Atleast, not in it's current state. ␊ |
6 | *␊ |
7 | * Created by Evan Lojewski on 3/4/10.␊ |
8 | * Copyright 2009. All rights reserved.␊ |
9 | *␊ |
10 | */␊ |
11 | ␊ |
12 | #ifndef _RESOLUTION_H_␊ |
13 | #define _RESOLUTION_H_␊ |
14 | ␊ |
15 | //#include "libsaio.h"␊ |
16 | //#include "edid.h" //included␊ |
17 | #include "915resolution.h"␊ |
18 | ␊ |
19 | ␊ |
20 | void patchVideoBios()␊ |
21 | {␊ |
22 | ␉UInt32 x = 0, y = 0, bp = 0;␊ |
23 | ␉␊ |
24 | ␉verbose("Resolution:\n");␊ |
25 | ␉getResolution(&x, &y, &bp);␊ |
26 | ␉␊ |
27 | ␉if (x != 0 && y != 0 && bp != 0)␊ |
28 | ␉{␊ |
29 | ␉␉vbios_map * map;␊ |
30 | ␉␉␊ |
31 | ␉␉map = open_vbios(CT_UNKNOWN);␊ |
32 | ␉␉if(map)␊ |
33 | ␉␉{␊ |
34 | ␉␉␉unlock_vbios(map);␊ |
35 | ␊ |
36 | ␉␉␉set_mode(map, x, y, bp, 0, 0);␊ |
37 | ␊ |
38 | ␉␉␉relock_vbios(map);␊ |
39 | ␊ |
40 | ␉␉␉close_vbios(map);␊ |
41 | ␉␉}␊ |
42 | ␉}␊ |
43 | }␊ |
44 | ␊ |
45 | ␊ |
46 | /* Copied from 915 resolution created by steve tomljenovic␊ |
47 | *␊ |
48 | * This code is based on the techniques used in :␊ |
49 | *␊ |
50 | * - 855patch. Many thanks to Christian Zietz (czietz gmx net)␊ |
51 | * for demonstrating how to shadow the VBIOS into system RAM␊ |
52 | * and then modify it.␊ |
53 | *␊ |
54 | * - 1280patch by Andrew Tipton (andrewtipton null li).␊ |
55 | *␊ |
56 | * - 855resolution by Alain Poirier␊ |
57 | *␊ |
58 | * This source code is into the public domain.␊ |
59 | */␊ |
60 | ␊ |
61 | /**␊ |
62 | **␊ |
63 | **/␊ |
64 | ␊ |
65 | #define CONFIG_MECH_ONE_ADDR␉0xCF8␊ |
66 | #define CONFIG_MECH_ONE_DATA␉0xCFC␊ |
67 | ␊ |
68 | int freqs[] = { 60, 75, 85 };␊ |
69 | ␊ |
70 | UInt32 get_chipset_id(void)␊ |
71 | {␊ |
72 | ␉outl(CONFIG_MECH_ONE_ADDR, 0x80000000);␊ |
73 | ␉return inl(CONFIG_MECH_ONE_DATA);␊ |
74 | }␊ |
75 | ␊ |
76 | chipset_type get_chipset(UInt32 id)␊ |
77 | {␊ |
78 | ␉chipset_type type;␊ |
79 | ␉␉␊ |
80 | ␉switch (id) {␊ |
81 | ␉␉case 0x35758086:␊ |
82 | ␉␉␉type = CT_830;␊ |
83 | ␉␉␉break;␊ |
84 | ␉␉␉␊ |
85 | ␉␉case 0x25608086:␊ |
86 | ␉␉␉type = CT_845G;␊ |
87 | ␉␉␉break;␊ |
88 | ␉␉␉␊ |
89 | ␉␉case 0x35808086:␊ |
90 | ␉␉␉type = CT_855GM;␊ |
91 | ␉␉␉break;␊ |
92 | ␉␉␉␊ |
93 | ␉␉case 0x25708086:␊ |
94 | ␉␉␉type = CT_865G;␊ |
95 | ␉␉␉break;␊ |
96 | ␉␉␉␊ |
97 | ␉␉case 0x25808086:␊ |
98 | ␉␉␉type = CT_915G;␊ |
99 | ␉␉␉break;␊ |
100 | ␉␉␉␊ |
101 | ␉␉case 0x25908086:␊ |
102 | ␉␉␉type = CT_915GM;␊ |
103 | ␉␉␉break;␊ |
104 | ␉␉␉␊ |
105 | ␉␉case 0x27708086:␊ |
106 | ␉␉␉type = CT_945G;␊ |
107 | ␉␉␉break;␊ |
108 | ␉␉␉␊ |
109 | ␉␉case 0x27a08086:␊ |
110 | ␉␉␉type = CT_945GM;␊ |
111 | ␉␉␉break;␊ |
112 | ␉␉␉␊ |
113 | ␉␉case 0x27ac8086:␊ |
114 | ␉␉␉type = CT_945GME;␊ |
115 | ␉␉␉break;␊ |
116 | ␉␉␉␊ |
117 | ␉␉case 0x29708086:␊ |
118 | ␉␉␉type = CT_946GZ;␊ |
119 | ␉␉␉break;␊ |
120 | ␉␉␉␊ |
121 | ␉␉case 0x27748086:␊ |
122 | ␉␉␉type = CT_955X;␊ |
123 | ␉␉␉break;␊ |
124 | ␉␉␉␊ |
125 | ␉␉case 0x277c8086:␊ |
126 | ␉␉␉type = CT_975X;␊ |
127 | ␉␉␉break;␊ |
128 | ␊ |
129 | ␉␉case 0x29a08086:␊ |
130 | ␉␉␉type = CT_G965;␊ |
131 | ␉␉␉break;␊ |
132 | ␉␉␉␊ |
133 | ␉␉case 0x29908086:␊ |
134 | ␉␉␉type = CT_Q965;␊ |
135 | ␉␉␉break;␊ |
136 | ␉␉␉␊ |
137 | ␉␉case 0x81008086:␊ |
138 | ␉␉␉type = CT_500;␊ |
139 | ␉␉␉break;␊ |
140 | ␉␉␉␊ |
141 | ␉␉case 0x2e108086:␊ |
142 | ␉␉case 0X2e908086:␊ |
143 | ␉␉␉type = CT_B43;␊ |
144 | ␉␉␉break;␊ |
145 | ␊ |
146 | ␉␉case 0x2e208086:␊ |
147 | ␉␉␉type = CT_P45;␊ |
148 | ␉␉␉break;␊ |
149 | ␊ |
150 | ␉␉case 0x2e308086:␊ |
151 | ␉␉␉type = CT_G41;␊ |
152 | ␉␉␉break;␊ |
153 | ␉␉␉␉␉␊ |
154 | ␉␉case 0x29c08086:␊ |
155 | ␉␉␉type = CT_G31;␊ |
156 | ␉␉␉break;␊ |
157 | ␉␉␉␊ |
158 | ␉␉case 0x29208086:␊ |
159 | ␉␉␉type = CT_G45;␊ |
160 | ␉␉␉break;␊ |
161 | ␉␉␉␊ |
162 | ␉␉case 0xA0108086:␉// mobile␊ |
163 | ␉␉case 0xA0008086:␉// desktop␊ |
164 | ␉␉␉type = CT_3150;␊ |
165 | ␉␉␉break;␊ |
166 | ␉␉␉␊ |
167 | ␉␉case 0x2a008086:␊ |
168 | ␉␉␉type = CT_965GM;␊ |
169 | ␉␉␉break;␊ |
170 | ␉␉␉␊ |
171 | ␉␉case 0x29e08086:␊ |
172 | ␉␉␉type = CT_X48;␊ |
173 | ␉␉␉break;␉␉␉␊ |
174 | ␉␉␉␉␊ |
175 | ␉␉case 0x2a408086:␊ |
176 | ␉␉␉type = CT_GM45;␊ |
177 | ␉␉␉break;␊ |
178 | ␉␉␉␊ |
179 | ␉␉␉//␊ |
180 | ␉␉␉// Core processors␊ |
181 | ␉␉␉// http://pci-ids.ucw.cz/read/PC/8086␊ |
182 | ␉␉␉//␊ |
183 | ␉␉case 0x00408086: // Core Processor DRAM Controller␊ |
184 | ␉␉case 0x00448086: // Core Processor DRAM Controller␊ |
185 | ␉␉case 0x00488086: // Core Processor DRAM Controller␊ |
186 | ␉␉case 0x00698086: // Core Processor DRAM Controller␊ |
187 | ␉␉␉␊ |
188 | ␉␉case 0x01008086: // 2nd Generation Core Processor Family DRAM Controller␊ |
189 | ␉␉case 0x01048086: // 2nd Generation Core Processor Family DRAM Controller␊ |
190 | ␉␉case 0x01088086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊ |
191 | ␉␉case 0x010c8086: // Xeon E3-1200 2nd Generation Core Processor Family DRAM Controller␊ |
192 | ␊ |
193 | ␉␉case 0x01508086: // 3rd Generation Core Processor Family DRAM Controller␊ |
194 | ␉␉case 0x01548086: // 3rd Generation Core Processor Family DRAM Controller␊ |
195 | ␉␉case 0x01588086: // 3rd Generation Core Processor Family DRAM Controller␊ |
196 | ␉␉case 0x015c8086: // 3rd Generation Core Processor Family DRAM Controller␊ |
197 | ␊ |
198 | ␉␉case 0x01608086: // 3rd Generation Core Processor Family DRAM Controller␊ |
199 | ␉␉case 0x01648086: // 3rd Generation Core Processor Family DRAM Controller␊ |
200 | ␊ |
201 | ␉␉case 0x0C008086: // 4rd Generation Core Processor Family DRAM Controller␊ |
202 | ␉␉case 0x0C048086: // 4rd Generation M-Processor Series␊ |
203 | ␉␉case 0x0A048086: // 4rd Generation U-Processor Series␊ |
204 | ␉␉case 0x0D048086: // 4rd Generation H-Processor Series (BGA) with GT3 Graphics␊ |
205 | ␉␉case 0x16048086: // 5th Generation Core Processor Family DRAM Controller␊ |
206 | ␉␉␉verbose(" core proc identified\n");␊ |
207 | ␉␉␉type = CT_CORE_PROC;␊ |
208 | ␉␉␉break;␊ |
209 | ␉␉␉␊ |
210 | ␉␉default:␊ |
211 | ␉␉␉if((id & 0x0000FFFF) == 0x00008086) // Intel chipset␊ |
212 | ␉␉␉{␊ |
213 | ␉␉␉␉//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);␊ |
214 | ␉␉␉␉//getc();␊ |
215 | ␉␉␉␉type = CT_UNKNOWN_INTEL;␊ |
216 | ␉␉␉␉//type = CT_UNKNOWN;␊ |
217 | ␊ |
218 | ␉␉␉}␊ |
219 | ␉␉␉else␊ |
220 | ␉␉␉{␊ |
221 | ␉␉␉␉type = CT_UNKNOWN;␊ |
222 | ␉␉␉}␊ |
223 | ␉␉␉break;␊ |
224 | ␉}␊ |
225 | ␊ |
226 | ␉return type;␊ |
227 | }␊ |
228 | ␊ |
229 | vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)␊ |
230 | {␊ |
231 | ␉vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res)); ␊ |
232 | ␉return ptr;␊ |
233 | }␊ |
234 | ␊ |
235 | vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)␊ |
236 | {␊ |
237 | ␉vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res)); ␊ |
238 | ␉return ptr;␊ |
239 | }␊ |
240 | ␊ |
241 | vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)␊ |
242 | {␊ |
243 | ␉vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res)); ␊ |
244 | ␉return ptr;␊ |
245 | }␊ |
246 | ␊ |
247 | char detect_bios_type(vbios_map * map, char modeline, int entry_size);␊ |
248 | char detect_bios_type(vbios_map * map, char modeline, int entry_size)␊ |
249 | {␊ |
250 | ␉UInt32 i;␊ |
251 | ␉UInt16 r1, r2;␊ |
252 | ␉␊ |
253 | ␉r1 = r2 = 32000;␊ |
254 | ␉␊ |
255 | ␉for (i=0; i < map->mode_table_size; i++)␊ |
256 | ␉{␊ |
257 | ␉␉if (map->mode_table[i].resolution <= r1)␊ |
258 | ␉␉{␊ |
259 | ␉␉␉r1 = map->mode_table[i].resolution;␊ |
260 | ␉␉}␊ |
261 | ␉␉else␊ |
262 | ␉␉{␊ |
263 | ␉␉␉if (map->mode_table[i].resolution <= r2)␊ |
264 | ␉␉␉{␊ |
265 | ␉␉␉␉r2 = map->mode_table[i].resolution;␊ |
266 | ␉␉␉}␊ |
267 | ␉␉}␊ |
268 | ␊ |
269 | ␉␉//printf("r1 = %d r2 = %d\n", r1, r2);␊ |
270 | ␉}␊ |
271 | ␉␊ |
272 | ␉return (r2-r1-6) % entry_size == 0;␊ |
273 | }␊ |
274 | ␊ |
275 | void close_vbios(vbios_map * map);␊ |
276 | ␊ |
277 | char detect_ati_bios_type(vbios_map * map)␊ |
278 | {␉␊ |
279 | ␉return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;␊ |
280 | }␊ |
281 | ␊ |
282 | ␊ |
283 | vbios_map * open_vbios(chipset_type forced_chipset)␊ |
284 | {␊ |
285 | ␉UInt32 z;␊ |
286 | ␉vbios_map * map = malloc(sizeof(vbios_map));␊ |
287 | ␉if (!map)␊ |
288 | ␉{␊ |
289 | ␉␉return 0;␊ |
290 | ␉}␊ |
291 | ␉for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;␊ |
292 | ␉/*␊ |
293 | ␉ * Determine chipset␊ |
294 | ␉ */␊ |
295 | ␉␊ |
296 | ␉if (forced_chipset == CT_UNKNOWN)␊ |
297 | ␉{␊ |
298 | ␉␉map->chipset_id = get_chipset_id();␊ |
299 | ␉␉map->chipset = get_chipset(map->chipset_id);␊ |
300 | ␉}␊ |
301 | ␉else if (forced_chipset != CT_UNKNOWN)␊ |
302 | ␉{␊ |
303 | ␉␉map->chipset = forced_chipset;␊ |
304 | ␉}␊ |
305 | ␉␊ |
306 | ␉␊ |
307 | ␉if (map->chipset == CT_UNKNOWN)␊ |
308 | ␉{␊ |
309 | ␉␉verbose(" Unknown chipset type: %08x.\n", (unsigned) map->chipset_id);␊ |
310 | ␉␉//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");␊ |
311 | ␉␉//verbose("Chipset Id: %x\n", map->chipset_id);␊ |
312 | ␉␉close_vbios(map);␊ |
313 | ␉␉return 0;␊ |
314 | ␉} else {␊ |
315 | ␉␉verbose(" Detected chipset/proc id (DRAM controller): %08x\n", (unsigned) map->chipset_id);␊ |
316 | ␉}␊ |
317 | ␉␊ |
318 | ␉␊ |
319 | ␉verbose(" VBios: ");␊ |
320 | ␉/*␊ |
321 | ␉ * Map the video bios to memory␊ |
322 | ␉ */␊ |
323 | ␉map->bios_ptr=(char*)VBIOS_START;␊ |
324 | ␉␊ |
325 | ␉/*␊ |
326 | ␉ * check if we have ATI Radeon␊ |
327 | ␉ */␊ |
328 | ␉map->ati_tables.base = map->bios_ptr;␊ |
329 | ␉map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER)); ␊ |
330 | ␉if (strncmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM", sizeof("ATOM")) == 0)␊ |
331 | ␉{␊ |
332 | ␉␉verbose("ATI");␊ |
333 | ␉␉// ATI Radeon Card␊ |
334 | ␉␉map->bios = BT_ATI_1;␊ |
335 | ␉␉␊ |
336 | ␉␉map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;␊ |
337 | ␉␉unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;␊ |
338 | ␉␉ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);␊ |
339 | ␉␉␊ |
340 | ␉␉map->ati_mode_table = (char *) &std_vesa->aModeTimings;␊ |
341 | ␉␉if (map->ati_mode_table == 0)␊ |
342 | ␉␉{␊ |
343 | ␉␉␉printf("Unable to locate the mode table.\n");␊ |
344 | ␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
345 | ␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
346 | ␉␉␉printf("Chipset: %d\n", map->chipset);␊ |
347 | ␉␉␉close_vbios(map);␊ |
348 | ␉␉␉return 0;␊ |
349 | ␉␉}␊ |
350 | ␉␉map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);␊ |
351 | ␉␉␊ |
352 | ␉␉if (!detect_ati_bios_type(map))␊ |
353 | ␉␉{␊ |
354 | ␉␉␉map->bios = BT_ATI_2;␊ |
355 | ␉␉}␊ |
356 | ␊ |
357 | ␉␉if (map->bios == BT_ATI_1)␊ |
358 | ␉␉{␊ |
359 | ␉␉␉verbose(", BT_ATI_1\n");␊ |
360 | ␉␉} else {␊ |
361 | ␉␉␉verbose(", BT_ATI_2\n");␊ |
362 | ␉␉}␊ |
363 | ␉}␊ |
364 | ␉else␊ |
365 | ␉{␊ |
366 | ␉␉␊ |
367 | ␉␉/*␊ |
368 | ␉␉ * check if we have NVIDIA␊ |
369 | ␉␉ */␊ |
370 | ␊ |
371 | ␉␉int i = 0;␊ |
372 | ␉␉while (i < 512)␊ |
373 | ␉␉{ // we don't need to look through the whole bios, just the first 512 bytes␊ |
374 | ␉␉␉if ((␉map->bios_ptr[i] == 'N') ␊ |
375 | ␉␉␉␉&& (map->bios_ptr[i+1] == 'V') ␊ |
376 | ␉␉␉␉&& (map->bios_ptr[i+2] == 'I') ␊ |
377 | ␉␉␉␉&& (map->bios_ptr[i+3] == 'D')) ␊ |
378 | ␉␉␉{␊ |
379 | ␉␉␉␉verbose("nVidia\n");␊ |
380 | ␉␉␉␉map->bios = BT_NVDA;␊ |
381 | ␉␉␉␉unsigned short nv_data_table_offset = 0;␊ |
382 | ␉␉␉␉unsigned short * nv_data_table;␊ |
383 | ␉␉␉␉NV_VESA_TABLE * std_vesa;␊ |
384 | ␉␉␉␉␊ |
385 | ␉␉␉␉int i = 0;␊ |
386 | ␊ |
387 | ␉␉␉␉while (i < 0x300)␊ |
388 | ␉␉␉␉{ //We don't need to look for the table in the whole bios, the 768 first bytes only␊ |
389 | ␉␉␉␉␉if ((␉map->bios_ptr[i] == 0x44) ␊ |
390 | ␉␉␉␉␉␉&& (map->bios_ptr[i+1] == 0x01) ␊ |
391 | ␉␉␉␉␉␉&& (map->bios_ptr[i+2] == 0x04) ␊ |
392 | ␉␉␉␉␉␉&& (map->bios_ptr[i+3] == 0x00))␊ |
393 | ␉␉␉␉␉{␊ |
394 | ␉␉␉␉␉␉nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));␊ |
395 | ␉␉␉␉␉␉break;␊ |
396 | ␉␉␉␉␉}␊ |
397 | ␉␉␉␉␉i++;␊ |
398 | ␉␉␉␉}␊ |
399 | ␉␉␉␉␊ |
400 | ␉␉␉␉nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));␊ |
401 | ␉␉␉␉std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);␊ |
402 | ␉␉␉␉␊ |
403 | ␉␉␉␉map->nv_mode_table = (char *) std_vesa->sModelines;␊ |
404 | ␉␉␉␉if (map->nv_mode_table == 0)␊ |
405 | ␉␉␉␉{␊ |
406 | ␉␉␉␉␉printf("Unable to locate the mode table.\n");␊ |
407 | ␉␉␉␉␉printf("Please run the program 'dump_bios' as root and\n");␊ |
408 | ␉␉␉␉␉printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");␊ |
409 | ␉␉␉␉␉printf("Chipset: %s\n", map->chipset);␊ |
410 | ␉␉␉␉␉close_vbios(map);␊ |
411 | ␉␉␉␉␉return 0;␊ |
412 | ␉␉␉␉}␊ |
413 | ␉␉␉␉map->mode_table_size = std_vesa->sHeader.usTable_Size;␊ |
414 | ␉␉␉␉␊ |
415 | ␉␉␉␉break;␊ |
416 | ␉␉␉}␊ |
417 | ␉␉␉i++;␊ |
418 | ␉␉}␊ |
419 | ␉}␊ |
420 | ␉␊ |
421 | ␊ |
422 | ␉/*␊ |
423 | ␉ * check if we have Intel␊ |
424 | ␉ */␊ |
425 | ␊ |
426 | ␉/*if (map->chipset == CT_UNKNOWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {␊ |
427 | ␉ printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");␊ |
428 | ␊ |
429 | ␉ printf("Chipset Id: %x\n", map->chipset_id);␊ |
430 | ␊ |
431 | ␉ printf("Please report this problem to stomljen@yahoo.com\n");␊ |
432 | ␊ |
433 | ␉ close_vbios(map);␊ |
434 | ␉ return 0;␊ |
435 | ␉ }*/␊ |
436 | ␊ |
437 | ␉/*␊ |
438 | ␉ * check for others␊ |
439 | ␉ */␊ |
440 | ␉␊ |
441 | ␉/*␊ |
442 | ␉ * Figure out where the mode table is ␊ |
443 | ␉ */␊ |
444 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA)) ␊ |
445 | ␉{␊ |
446 | ␉␉char* p = map->bios_ptr + 16;␊ |
447 | ␉␉char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));␊ |
448 | ␉␉␊ |
449 | ␉␉verbose("Other");␊ |
450 | ␉␉while (p < limit && map->mode_table == 0)␊ |
451 | ␉␉{␊ |
452 | ␉␉␉vbios_mode * mode_ptr = (vbios_mode *) p;␊ |
453 | ␉␉␉␊ |
454 | ␉␉␉if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&␊ |
455 | ␉␉␉␉((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))␊ |
456 | ␉␉␉{␊ |
457 | ␉␉␉␉map->mode_table = mode_ptr;␊ |
458 | ␉␉␉}␊ |
459 | ␉␉␉␊ |
460 | ␉␉␉p++;␊ |
461 | ␉␉}␊ |
462 | ␊ |
463 | ␉␉if (map->mode_table == 0)␊ |
464 | ␉␉{␊ |
465 | ␉␉␉close_vbios(map);␊ |
466 | ␉␉␉return 0;␊ |
467 | ␉␉}␊ |
468 | ␉}␊ |
469 | ␉␊ |
470 | ␉␊ |
471 | ␉/*␊ |
472 | ␉ * Determine size of mode table␊ |
473 | ␉ */␊ |
474 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
475 | ␉{␊ |
476 | ␉␉vbios_mode * mode_ptr = map->mode_table;␊ |
477 | ␉␉␊ |
478 | ␉␉while (mode_ptr->mode != 0xff)␊ |
479 | ␉␉{␊ |
480 | ␉␉␉map->mode_table_size++;␊ |
481 | ␉␉␉mode_ptr++;␊ |
482 | ␉␉}␊ |
483 | ␉}␊ |
484 | ␉␊ |
485 | ␉/*␊ |
486 | ␉ * Figure out what type of bios we have␊ |
487 | ␉ * order of detection is important␊ |
488 | ␉ */␊ |
489 | ␉if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))␊ |
490 | ␉{␊ |
491 | ␉␉if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))␊ |
492 | ␉␉{␊ |
493 | ␉␉␉map->bios = BT_3;␊ |
494 | ␉␉␉verbose(", BT_3\n");␊ |
495 | ␉␉}␊ |
496 | ␉␉else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))␊ |
497 | ␉␉{␊ |
498 | ␉␉␉map->bios = BT_2;␊ |
499 | ␉␉␉verbose(", BT_2\n");␊ |
500 | ␉␉}␊ |
501 | ␉␉else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))␊ |
502 | ␉␉{␊ |
503 | ␉␉␉map->bios = BT_1;␊ |
504 | ␉␉␉verbose(", BT_1\n");␊ |
505 | ␉␉}␊ |
506 | ␉␉else {␊ |
507 | ␉␉␉verbose(" - unknown\n");␊ |
508 | ␉␉␉return 0;␊ |
509 | ␉␉}␊ |
510 | ␉}␊ |
511 | ␉␊ |
512 | ␉return map;␊ |
513 | }␊ |
514 | ␊ |
515 | void close_vbios(vbios_map * map)␊ |
516 | {␊ |
517 | ␉free(map);␊ |
518 | }␊ |
519 | ␊ |
520 | void unlock_vbios(vbios_map * map)␊ |
521 | {␊ |
522 | ␊ |
523 | ␉map->unlocked = TRUE;␊ |
524 | ␊ |
525 | ␉switch (map->chipset) {␊ |
526 | ␉␉case CT_UNKNOWN:␊ |
527 | ␉␉␉break;␊ |
528 | ␉␉case CT_830:␊ |
529 | ␉␉case CT_855GM:␊ |
530 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
531 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
532 | ␉␉␉␊ |
533 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
534 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
535 | ␉␉␉break;␊ |
536 | ␉␉case CT_845G:␊ |
537 | ␉␉case CT_865G:␊ |
538 | ␉␉case CT_915G:␊ |
539 | ␉␉case CT_915GM:␊ |
540 | ␉␉case CT_945G:␊ |
541 | ␉␉case CT_945GM:␊ |
542 | ␉␉case CT_945GME:␊ |
543 | ␉␉case CT_946GZ:␊ |
544 | ␉␉case CT_G965:␊ |
545 | ␉␉case CT_Q965:␊ |
546 | ␉␉case CT_965GM:␊ |
547 | ␉␉case CT_975X:␊ |
548 | ␉␉case CT_P35:␊ |
549 | ␉␉case CT_955X:␊ |
550 | ␉␉case CT_X48:␊ |
551 | ␉␉case CT_B43:␊ |
552 | ␉␉case CT_Q45:␊ |
553 | ␉␉case CT_P45:␊ |
554 | ␉␉case CT_GM45:␊ |
555 | ␉␉case CT_G45:␊ |
556 | ␉␉case CT_G41:␊ |
557 | ␉␉case CT_G31:␊ |
558 | ␉␉case CT_500:␊ |
559 | ␉␉case CT_3150:␊ |
560 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
561 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
562 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
563 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
564 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
565 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
566 | ␉␉␉break;␊ |
567 | ␉␉case CT_CORE_PROC:␉ // Core procs - PAM regs are 80h - 86h␊ |
568 | ␉␉case CT_UNKNOWN_INTEL:␉// Assume newer intel chipset is the same as before␊ |
569 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
570 | ␉␉␉map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);␊ |
571 | ␉␉␉map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);␊ |
572 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
573 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, 0x33);␊ |
574 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, 0x33);␊ |
575 | ␉␉␉break;␊ |
576 | ␉␉default:␊ |
577 | ␉␉␉break;␊ |
578 | ␉}␊ |
579 | ␉␊ |
580 | #if DEBUG␊ |
581 | ␉{␊ |
582 | ␉␉UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
583 | ␉␉verbose("unlock PAM: (0x%08x)\n", t);␊ |
584 | ␉}␊ |
585 | #endif␊ |
586 | }␊ |
587 | ␊ |
588 | void relock_vbios(vbios_map * map)␊ |
589 | {␊ |
590 | ␉␊ |
591 | ␉map->unlocked = FALSE;␊ |
592 | ␉␊ |
593 | ␉switch (map->chipset)␊ |
594 | ␉{␊ |
595 | ␉␉case CT_UNKNOWN:␊ |
596 | ␉␉␉break;␊ |
597 | ␉␉case CT_830:␊ |
598 | ␉␉case CT_855GM:␊ |
599 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);␊ |
600 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b1);␊ |
601 | ␉␉␉break;␊ |
602 | ␉␉case CT_845G:␊ |
603 | ␉␉case CT_865G:␊ |
604 | ␉␉case CT_915G:␊ |
605 | ␉␉case CT_915GM:␊ |
606 | ␉␉case CT_945G:␊ |
607 | ␉␉case CT_945GM:␊ |
608 | ␉␉case CT_945GME:␊ |
609 | ␉␉case CT_946GZ:␊ |
610 | ␉␉case CT_G965:␊ |
611 | ␉␉case CT_955X:␊ |
612 | ␉␉case CT_G45:␊ |
613 | ␉␉case CT_Q965:␊ |
614 | ␉␉case CT_965GM:␊ |
615 | ␉␉case CT_975X:␊ |
616 | ␉␉case CT_P35:␊ |
617 | ␉␉case CT_X48:␊ |
618 | ␉␉case CT_B43:␊ |
619 | ␉␉case CT_Q45:␊ |
620 | ␉␉case CT_P45:␊ |
621 | ␉␉case CT_GM45:␊ |
622 | ␉␉case CT_G41:␊ |
623 | ␉␉case CT_G31:␊ |
624 | ␉␉case CT_500:␊ |
625 | ␉␉case CT_3150:␊ |
626 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000090);␊ |
627 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
628 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
629 | ␉␉␉break;␊ |
630 | ␉␉case CT_CORE_PROC:␊ |
631 | ␉␉case CT_UNKNOWN_INTEL:␊ |
632 | ␉␉␉outl(CONFIG_MECH_ONE_ADDR, 0x80000080);␊ |
633 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 1, map->b1);␊ |
634 | ␉␉␉outb(CONFIG_MECH_ONE_DATA + 2, map->b2);␊ |
635 | ␉␉default:␊ |
636 | ␉␉␉break;␊ |
637 | ␉}␊ |
638 | ␉␊ |
639 | #if DEBUG␊ |
640 | ␉{␊ |
641 | UInt32 t = inl(CONFIG_MECH_ONE_DATA);␊ |
642 | ␉␉verbose("relock PAM: (0x%08x)\n", t);␊ |
643 | ␉}␊ |
644 | #endif␊ |
645 | }␊ |
646 | ␊ |
647 | ␊ |
648 | int getMode(edid_mode *mode)␊ |
649 | {␊ |
650 | ␉char* edidInfo = readEDID();␊ |
651 | ␉␉␉␊ |
652 | ␉if(!edidInfo) return 1;␊ |
653 | //Slice␊ |
654 | ␉if(!fb_parse_edid((struct EDID *)edidInfo, mode) || !mode->h_active) ␊ |
655 | ␉{␊ |
656 | ␉␉free( edidInfo );␊ |
657 | ␉␉return 1;␊ |
658 | ␉}␊ |
659 | /*␉mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];␊ |
660 | ␉mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);␊ |
661 | ␉mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];␊ |
662 | ␉mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);␊ |
663 | ␉mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];␊ |
664 | ␉mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];␊ |
665 | ␉mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];␊ |
666 | ␉mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);␊ |
667 | ␉mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);␊ |
668 | */␉␉␊ |
669 | ␊ |
670 | ␉free( edidInfo );␊ |
671 | ␉␉␊ |
672 | ␉if(!mode->h_active) return 1;␊ |
673 | ␊ |
674 | ␉return 0;␊ |
675 | ␉␉␊ |
676 | }␊ |
677 | ␊ |
678 | ␊ |
679 | static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,␊ |
680 | ␉␉␉␉␉␉unsigned long *clock,␊ |
681 | ␉␉␉␉␉␉UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,␊ |
682 | ␉␉␉␉␉␉UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)␊ |
683 | {␊ |
684 | ␉UInt32 hbl, vbl, vfreq;␊ |
685 | ␉␊ |
686 | ␉vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;␊ |
687 | ␉vfreq = vbl * freq;␊ |
688 | ␉hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /␊ |
689 | ␉␉␉␉␉ + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);␊ |
690 | ␊ |
691 | ␉*vsyncstart = y;␊ |
692 | ␉*vsyncend = y + 3;␊ |
693 | ␉*vblank = vbl - 1;␊ |
694 | ␉*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;␊ |
695 | ␉*hsyncend = x + hbl / 2 - 1;␊ |
696 | ␉*hblank = x + hbl - 1;␊ |
697 | ␉*clock = (x + hbl) * vfreq / 1000;␊ |
698 | }␊ |
699 | ␊ |
700 | void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {␊ |
701 | ␉UInt32 xprev, yprev;␊ |
702 | ␉UInt32 i = 0, j;␊ |
703 | ␉// patch first available mode␊ |
704 | ␉␊ |
705 | ␉//␉for (i=0; i < map->mode_table_size; i++) {␊ |
706 | ␉//␉␉if (map->mode_table[0].mode == mode) {␊ |
707 | ␉verbose(" Patching: ");␊ |
708 | ␉switch(map->bios) {␊ |
709 | ␉␉case BT_INTEL:␊ |
710 | ␉␉␉verbose("BT_INTEL - not supported\n");␊ |
711 | ␉␉␉return;␊ |
712 | ␊ |
713 | ␉␉case BT_1:␊ |
714 | ␉␉{␊ |
715 | ␉␉␉verbose("BT_1 patched.\n");␊ |
716 | ␉␉␉vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);␊ |
717 | ␉␉␉␊ |
718 | ␉␉␉if (bp)␊ |
719 | ␉␉␉{␊ |
720 | ␉␉␉␉map->mode_table[i].bits_per_pixel = (uint8_t)bp;␊ |
721 | ␉␉␉}␊ |
722 | ␉␉␉␊ |
723 | ␉␉␉res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);␊ |
724 | ␉␉␉res->x1 = (x & 0xff);␊ |
725 | ␉␉␉␊ |
726 | ␉␉␉res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);␊ |
727 | ␉␉␉res->y1 = (y & 0xff);␊ |
728 | ␉␉␉if (htotal)␊ |
729 | ␉␉␉{␊ |
730 | ␉␉␉␉res->x_total = ((htotal-x) & 0xff);␊ |
731 | ␉␉␉}␊ |
732 | ␉␉␉if (vtotal)␊ |
733 | ␉␉␉{␊ |
734 | ␉␉␉␉res->y_total = ((vtotal-y) & 0xff);␊ |
735 | ␉␉␉}␊ |
736 | ␉␉␉break;␊ |
737 | ␉␉}␊ |
738 | ␉␉case BT_2:␊ |
739 | ␉␉{␊ |
740 | ␉␉␉vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);␊ |
741 | ␉␉␉␊ |
742 | ␉␉␉res->xchars = (uint8_t)(x / 8);␊ |
743 | ␉␉␉res->ychars = (uint8_t)(y / 16 - 1);␊ |
744 | ␉␉␉xprev = res->modelines[0].x1;␊ |
745 | ␉␉␉yprev = res->modelines[0].y1;␊ |
746 | ␉␉␉␊ |
747 | ␉␉␉for(j=0; j < 3; j++) {␊ |
748 | ␉␉␉␉vbios_modeline_type2 * modeline = &res->modelines[j];␊ |
749 | ␉␉␉␉␊ |
750 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev)␊ |
751 | ␉␉␉␉{␊ |
752 | ␉␉␉␉␉modeline->x1 = modeline->x2 = (uint16_t)(x-1);␊ |
753 | ␉␉␉␉␉modeline->y1 = modeline->y2 = (uint16_t)(y-1);␊ |
754 | ␉␉␉␉␉␊ |
755 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
756 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
757 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
758 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
759 | ␉␉␉␉␉␊ |
760 | ␉␉␉␉␉if (htotal)␊ |
761 | ␉␉␉␉␉{␊ |
762 | ␉␉␉␉␉␉modeline->htotal = (uint16_t)htotal;␊ |
763 | ␉␉␉␉␉}␊ |
764 | ␉␉␉␉␉else␊ |
765 | ␉␉␉␉␉{␊ |
766 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
767 | ␉␉␉␉␉}␊ |
768 | ␉␉␉␉␉if (vtotal)␊ |
769 | ␉␉␉␉␉{␊ |
770 | ␉␉␉␉␉␉modeline->vtotal = (uint16_t)vtotal;␊ |
771 | ␉␉␉␉␉}␊ |
772 | ␉␉␉␉␉else␊ |
773 | ␉␉␉␉␉{␊ |
774 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
775 | ␉␉␉␉␉}␊ |
776 | ␉␉␉␉}␊ |
777 | ␉␉␉}␊ |
778 | ␉␉␉verbose("BT_1 patched.\n");␊ |
779 | ␉␉␉break;␊ |
780 | ␉␉}␊ |
781 | ␉␉case BT_3:␊ |
782 | ␉␉{␊ |
783 | ␉␉␉vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);␊ |
784 | ␉␉␉␊ |
785 | ␉␉␉xprev = res->modelines[0].x1;␊ |
786 | ␉␉␉yprev = res->modelines[0].y1;␊ |
787 | ␉␉␉␊ |
788 | ␉␉␉for (j=0; j < 3; j++)␊ |
789 | ␉␉␉{␊ |
790 | ␉␉␉␉vbios_modeline_type3 * modeline = &res->modelines[j];␊ |
791 | ␉␉␉␉␊ |
792 | ␉␉␉␉if (modeline->x1 == xprev && modeline->y1 == yprev)␊ |
793 | ␉␉␉␉{␊ |
794 | ␉␉␉␉␉modeline->x1 = modeline->x2 = (uint16_t)(x-1);␊ |
795 | ␉␉␉␉␉modeline->y1 = modeline->y2 = (uint16_t)(y-1);␊ |
796 | ␉␉␉␉␉␊ |
797 | ␉␉␉␉␉gtf_timings(x, y, freqs[j], &modeline->clock,␊ |
798 | ␉␉␉␉␉␉␉␉&modeline->hsyncstart, &modeline->hsyncend,␊ |
799 | ␉␉␉␉␉␉␉␉&modeline->hblank, &modeline->vsyncstart,␊ |
800 | ␉␉␉␉␉␉␉␉&modeline->vsyncend, &modeline->vblank);␊ |
801 | ␉␉␉␉␉if (htotal)␊ |
802 | ␉␉␉␉␉{␊ |
803 | ␉␉␉␉␉␉modeline->htotal = (uint16_t)htotal;␊ |
804 | ␉␉␉␉␉}␊ |
805 | ␉␉␉␉␉else␊ |
806 | ␉␉␉␉␉{␊ |
807 | ␉␉␉␉␉␉modeline->htotal = modeline->hblank;␊ |
808 | ␉␉␉␉␉}␊ |
809 | ␉␉␉␉␉if (vtotal)␊ |
810 | ␉␉␉␉␉{␊ |
811 | ␉␉␉␉␉␉modeline->vtotal = (uint16_t)vtotal;␊ |
812 | ␉␉␉␉␉}␊ |
813 | ␉␉␉␉␉else␊ |
814 | ␉␉␉␉␉{␊ |
815 | ␉␉␉␉␉␉modeline->vtotal = modeline->vblank;␊ |
816 | ␉␉␉␉␉}␊ |
817 | ␉␉␉␉␉modeline->timing_h = (uint16_t)(y-1);␊ |
818 | ␉␉␉␉␉modeline->timing_v = (uint16_t)(x-1);␊ |
819 | ␉␉␉␉}␊ |
820 | ␉␉␉}␊ |
821 | ␉␉␉verbose("BT_3 patched.\n");␊ |
822 | ␉␉␉break;␊ |
823 | ␉␉}␊ |
824 | ␉␉case BT_ATI_1:␊ |
825 | ␉␉{␊ |
826 | ␉␉␉verbose("BT_ATI_1");␊ |
827 | ␉␉␉edid_mode mode;␊ |
828 | ␉␉␉␉␊ |
829 | ␉␉␉ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;␊ |
830 | ␊ |
831 | ␉␉␉//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force){␊ |
832 | ␉␉␉if (!getMode(&mode))␊ |
833 | ␉␉␉{␊ |
834 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊ |
835 | ␉␉␉␉mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;␊ |
836 | ␉␉␉␉mode_timing->usCRTC_H_Disp = mode.h_active;␊ |
837 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
838 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;␊ |
839 | ␉␉␉␉␉␊ |
840 | ␉␉␉␉mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;␊ |
841 | ␉␉␉␉mode_timing->usCRTC_V_Disp = mode.v_active;␊ |
842 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
843 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;␊ |
844 | ␊ |
845 | ␉␉␉␉mode_timing->usPixelClock = mode.pixel_clock;␊ |
846 | ␉␉␉}␊ |
847 | ␉␉␉else␊ |
848 | ␉␉␉{␊ |
849 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
850 | ␉␉␉}␊ |
851 | ␉␉␉/*else␊ |
852 | ␉␉␉{␊ |
853 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
854 | ␊ |
855 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
856 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
857 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
858 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
859 | ␊ |
860 | ␉␉␉␉mode_timing->usCRTC_H_Total = x + modeline.hblank;␊ |
861 | ␉␉␉␉mode_timing->usCRTC_H_Disp = x;␊ |
862 | ␉␉␉␉mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;␊ |
863 | ␉␉␉␉mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
864 | ␊ |
865 | ␉␉␉␉mode_timing->usCRTC_V_Total = y + modeline.vblank;␊ |
866 | ␉␉␉␉mode_timing->usCRTC_V_Disp = y;␊ |
867 | ␉␉␉␉mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;␊ |
868 | ␉␉␉␉mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;␊ |
869 | ␉␉␉␉␉␉␉␉␉␉␉␉␊ |
870 | ␉␉␉␉mode_timing->usPixelClock = modeline.clock;␊ |
871 | ␉␉␉ }*/␊ |
872 | ␊ |
873 | ␉␉␉break;␊ |
874 | ␉␉}␊ |
875 | ␉␉case BT_ATI_2:␊ |
876 | ␉␉{␊ |
877 | ␉␉␉verbose("BT_ATI_2");␊ |
878 | ␉␉␉edid_mode mode;␊ |
879 | ␉␉␉␉␉␉␊ |
880 | ␉␉␉ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;␊ |
881 | ␉␉␉␊ |
882 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
883 | ␉␉␉if (!getMode(&mode))␊ |
884 | ␉␉␉{␊ |
885 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode 0 patched!\n", mode.h_active, mode.v_active);␊ |
886 | ␉␉␉␉mode_timing->usHBlanking_Time = mode.h_blanking;␊ |
887 | ␉␉␉␉mode_timing->usHActive = mode.h_active;␊ |
888 | ␉␉␉␉mode_timing->usHSyncOffset = mode.h_sync_offset;␊ |
889 | ␉␉␉␉mode_timing->usHSyncWidth = mode.h_sync_width;␊ |
890 | ␉␉␉␉␉␉␉␉␉␉␊ |
891 | ␉␉␉␉mode_timing->usVBlanking_Time = mode.v_blanking;␊ |
892 | ␉␉␉␉mode_timing->usVActive = mode.v_active;␊ |
893 | ␉␉␉␉mode_timing->usVSyncOffset = mode.v_sync_offset;␊ |
894 | ␉␉␉␉mode_timing->usVSyncWidth = mode.v_sync_width;␊ |
895 | ␉␉␉␉␉␉␉␉␉␉␊ |
896 | ␉␉␉␉mode_timing->usPixClk = mode.pixel_clock;␊ |
897 | ␉␉␉}␊ |
898 | ␉␉␉else␊ |
899 | ␉␉␉{␊ |
900 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
901 | ␉␉␉}␊ |
902 | ␉␉␉/*else␊ |
903 | ␉␉␉{␊ |
904 | ␉␉␉␉vbios_modeline_type2 modeline;␊ |
905 | ␉␉␉␊ |
906 | ␉␉␉␉cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
907 | ␉␉␉␉␉␉␉&modeline.hsyncstart, &modeline.hsyncend,␊ |
908 | ␉␉␉␉␉␉␉&modeline.hblank, &modeline.vsyncstart,␊ |
909 | ␉␉␉␉␉␉␉&modeline.vsyncend, &modeline.vblank, 0);␊ |
910 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
911 | ␉␉␉␉mode_timing->usHBlanking_Time = modeline.hblank;␊ |
912 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usHActive = x;␊ |
913 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usHSyncOffset = modeline.hsyncstart - x;␊ |
914 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
915 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
916 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVBlanking_Time = modeline.vblank;␊ |
917 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVActive = y;␊ |
918 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVSyncOffset = modeline.vsyncstart - y;␊ |
919 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;␊ |
920 | ␉␉␉␉␉␉␉␉␉␉␉␊ |
921 | ␉␉␉␉␉␉␉␉␉␉␉mode_timing->usPixClk = modeline.clock;␊ |
922 | ␉␉␉␉␉␉␉␉␉␉}*/␊ |
923 | ␊ |
924 | ␉␉␉break;␊ |
925 | ␉␉}␊ |
926 | ␉␉case BT_NVDA:␊ |
927 | ␉␉{␊ |
928 | ␉␉␉verbose("BT_NVDA");␊ |
929 | ␉␉␉edid_mode mode;␊ |
930 | ␉␉␉NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;␊ |
931 | ␉␉␉␊ |
932 | ␉␉␉/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/␊ |
933 | ␉␉␉if (!getMode(&mode))␊ |
934 | ␉␉␉{␊ |
935 | ␉␉␉␉verbose("\n Edid detailed timing descriptor found: %dx%d\n vbios mode %d patched!\n", mode.h_active, mode.v_active, (int) i);␊ |
936 | ␉␉␉␉mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;␊ |
937 | ␉␉␉␉mode_timing[i].usH_Active = mode.h_active;␊ |
938 | ␉␉␉␉mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;␊ |
939 | ␉␉␉␉mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;␊ |
940 | ␉␉␉␉␊ |
941 | ␉␉␉␉mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;␊ |
942 | ␉␉␉␉mode_timing[i].usV_Active = mode.v_active;␊ |
943 | ␉␉␉␉mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;␊ |
944 | ␉␉␉␉mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;␊ |
945 | ␉␉␉␉␊ |
946 | ␉␉␉␉mode_timing[i].usPixel_Clock = mode.pixel_clock;␊ |
947 | ␉␉␉}␊ |
948 | ␉␉␉ else␊ |
949 | ␉␉␉{␊ |
950 | ␉␉␉␉verbose(" Edid not found or invalid - vbios not patched!\n");␊ |
951 | ␉␉␉}␊ |
952 | ␉␉␉/*else␊ |
953 | ␉␉␉ {␊ |
954 | ␉␉␉ vbios_modeline_type2 modeline;␊ |
955 | ␉␉␉ cvt_timings(x, y, freqs[0], &modeline.clock,␊ |
956 | ␉␉␉ &modeline.hsyncstart, &modeline.hsyncend,␊ |
957 | ␉␉␉ &modeline.hblank, &modeline.vsyncstart,␊ |
958 | ␉␉␉ &modeline.vsyncend, &modeline.vblank, 0);␊ |
959 | ␊ |
960 | ␉␉␉ mode_timing[i].usH_Total = x + modeline.hblank - 1;␊ |
961 | ␉␉␉ mode_timing[i].usH_Active = x;␊ |
962 | ␉␉␉ mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;␊ |
963 | ␉␉␉ mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;␊ |
964 | ␊ |
965 | ␉␉␉ mode_timing[i].usV_Total = y + modeline.vblank - 1;␊ |
966 | ␉␉␉ mode_timing[i].usV_Active = y;␊ |
967 | ␉␉␉ mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;␊ |
968 | ␉␉␉ mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;␊ |
969 | ␊ |
970 | ␉␉␉ mode_timing[i].usPixel_Clock = modeline.clock;␊ |
971 | ␉␉␉ }*/␊ |
972 | ␉␉␉break;␊ |
973 | ␉␉}␊ |
974 | ␉␉case BT_UNKNOWN:␊ |
975 | ␉␉{␊ |
976 | ␉␉␉verbose(" Unknown - vbios not patched\n");␊ |
977 | ␉␉␉break;␊ |
978 | ␉␉}␊ |
979 | ␉␉default:␊ |
980 | ␉␉␉break;␊ |
981 | ␉}␊ |
982 | ␉//␉␉}␊ |
983 | ␉//␉}␊ |
984 | }␊ |
985 | ␊ |
986 | #endif // _RESOLUTION_H_␊ |
987 | |