Chameleon

Chameleon Svn Source Tree

Root/trunk/i386/libsaio/cpu.c

1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 * Bronya: 2015 Improve AMD support, cleanup and bugfix␊
5 */␊
6␊
7#include "libsaio.h"␊
8#include "platform.h"␊
9#include "cpu.h"␊
10#include "bootstruct.h"␊
11#include "boot.h"␊
12␊
13#ifndef DEBUG_CPU␊
14␉#define DEBUG_CPU 0␊
15#endif␊
16␊
17#if DEBUG_CPU␊
18␉#define DBG(x...)␉␉printf(x)␊
19#else␊
20␉#define DBG(x...)␊
21#endif␊
22␊
23␊
24#define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊
25␊
26clock_frequency_info_t gPEClockFrequencyInfo;␊
27␊
28static __unused uint64_t rdtsc32(void)␊
29{␊
30␉unsigned int lo,hi;␊
31␉__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));␊
32␉return ((uint64_t)hi << 32) | lo;␊
33}␊
34␊
35/*␊
36 * timeRDTSC()␊
37 * This routine sets up PIT counter 2 to count down 1/20 of a second.␊
38 * It pauses until the value is latched in the counter␊
39 * and then reads the time stamp counter to return to the caller.␊
40 */␊
41static uint64_t timeRDTSC(void)␊
42{␊
43␉int␉␉attempts = 0;␊
44␉uint32_t ␉latchTime;␊
45␉uint64_t␉saveTime,intermediate;␊
46␉unsigned int␉timerValue, lastValue;␊
47␉//boolean_t␉int_enabled;␊
48␉/*␊
49␉ * Table of correction factors to account for␊
50␉ *␉ - timer counter quantization errors, and␊
51␉ *␉ - undercounts 0..5␊
52␉ */␊
53#define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊
54#define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊
55#define SAMPLE_NSECS␉␉(2000000000LL)␊
56#define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊
57#define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊
58␉uint64_t␉scale[6] = {␊
59␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊
60␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊
61␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊
62␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊
63␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊
64␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊
65␉};␊
66␊
67␉//int_enabled = ml_set_interrupts_enabled(false);␊
68␊
69restart:␊
70␉if (attempts >= 3) // increase to up to 9 attempts.␊
71␉{␊
72␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊
73␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
74␉}␊
75␉attempts++;␊
76␉enable_PIT2();␉␉// turn on PIT2␊
77␉set_PIT2(0);␉␉// reset timer 2 to be zero␊
78␉latchTime = rdtsc32();␉// get the time stamp to time␊
79␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊
80␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊
81␉saveTime = rdtsc32();␉// now time how long a 20th a second is...␊
82␉get_PIT2(&lastValue);␊
83␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊
84␉do {␊
85␉␉intermediate = get_PIT2(&timerValue);␊
86␉␉if (timerValue > lastValue)␊
87␉␉{␊
88␉␉␉// Timer wrapped␊
89␉␉␉set_PIT2(0);␊
90␉␉␉disable_PIT2();␊
91␉␉␉goto restart;␊
92␉␉}␊
93␉␉lastValue = timerValue;␊
94␉} while (timerValue > 5);␊
95␉//printf("timerValue␉ %d\n",timerValue);␊
96␉//printf("intermediate 0x%016llX\n",intermediate);␊
97␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊
98 ␊
99␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊
100␉intermediate *= scale[timerValue];␉// rescale measured time spent␊
101␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊
102␉intermediate += latchTime;␉␉// add on our save fudge␊
103␊
104␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊
105␉disable_PIT2();␉␉␉// turn off PIT 2␊
106␊
107␉//ml_set_interrupts_enabled(int_enabled);␊
108␉return intermediate;␊
109}␊
110␊
111/*␊
112 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
113 */␊
114static uint64_t __unused measure_tsc_frequency(void)␊
115{␊
116␉uint64_t tscStart;␊
117␉uint64_t tscEnd;␊
118␉uint64_t tscDelta = 0xffffffffffffffffULL;␊
119␉unsigned long pollCount;␊
120␉uint64_t retval = 0;␊
121␉int i;␊
122␊
123␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
124␉ * counter 2. We run this loop 3 times to make sure the cache␊
125␉ * is hot and we take the minimum delta from all of the runs.␊
126␉ * That is to say that we're biased towards measuring the minimum␊
127␉ * number of TSC ticks that occur while waiting for the timer to␊
128␉ * expire. That theoretically helps avoid inconsistencies when␊
129␉ * running under a VM if the TSC is not virtualized and the host␊
130␉ * steals time.␉ The TSC is normally virtualized for VMware.␊
131␉ */␊
132␉for(i = 0; i < 10; ++i)␊
133␉{␊
134␉␉enable_PIT2();␊
135␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊
136␉␉tscStart = rdtsc64();␊
137␉␉pollCount = poll_PIT2_gate();␊
138␉␉tscEnd = rdtsc64();␊
139␉␉/* The poll loop must have run at least a few times for accuracy */␊
140␉␉if (pollCount <= 1)␊
141␉␉{␊
142␉␉␉continue;␊
143␉␉}␊
144␉␉/* The TSC must increment at LEAST once every millisecond.␊
145␉␉ * We should have waited exactly 30 msec so the TSC delta should␊
146␉␉ * be >= 30. Anything less and the processor is way too slow.␊
147␉␉ */␊
148␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
149␉␉{␊
150␉␉␉continue;␊
151␉␉}␊
152␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊
153␉␉if ( (tscEnd - tscStart) < tscDelta )␊
154␉␉{␊
155␉␉␉tscDelta = tscEnd - tscStart;␊
156␉␉}␊
157␉}␊
158␉/* tscDelta is now the least number of TSC ticks the processor made in␊
159␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊
160␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊
161␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
162␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊
163␉ * dividing by the milliseconds, we simply multiply by 1000.␊
164␉ */␊
165␊
166␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
167␉ * that we're going to multiply by 1000 first so we do need at least some␊
168␉ * arithmetic headroom. For now, 32-bit should be enough.␊
169␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
170␉ */␊
171␉if (tscDelta > (1ULL<<32))␊
172␉{␊
173␉␉retval = 0;␊
174␉}␊
175␉else␊
176␉{␊
177␉␉retval = tscDelta * 1000 / 30;␊
178␉}␊
179␉disable_PIT2();␊
180␉return retval;␊
181}␊
182␊
183static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊
184#define RTC_FAST_DENOM␉0xFFFFFFFF␊
185␊
186inline static uint32_t␊
187create_mul_quant_GHZ(int shift, uint32_t quant)␊
188{␊
189␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊
190}␊
191␊
192struct␉{␊
193␉mach_timespec_t␉␉␉calend_offset;␊
194␉boolean_t␉␉␉calend_is_set;␊
195␊
196␉int64_t␉␉␉␉calend_adjtotal;␊
197␉int32_t␉␉␉␉calend_adjdelta;␊
198␊
199␉uint32_t␉␉␉boottime;␊
200␊
201␉mach_timebase_info_data_t␉timebase_const;␊
202␊
203␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊
204} rtclock;␊
205␊
206uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊
207uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊
208uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊
209uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊
210␊
211static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊
212{␊
213␊
214␉if (cycles > (NSEC_PER_SEC/20))␊
215␉{␊
216␉␉// we can use just a "fast" multiply to get nanos␊
217␉␉rtc_quant_shift = 32;␊
218␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
219␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊
220␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊
221␉}␊
222␉else␊
223␉{␊
224␉␉rtc_quant_shift = 26;␊
225␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊
226␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊
227␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊
228␉}␊
229␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊
230␉// BUT we also want to calculate...␊
231␊
232␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊
233 / UI_CPUFREQ_ROUNDING_FACTOR)␊
234␉* UI_CPUFREQ_ROUNDING_FACTOR;␊
235␊
236␉/*␊
237␉ * Set current measured speed.␊
238␉ */␊
239␉if (cycles >= 0x100000000ULL)␊
240␉{␊
241␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊
242␉}␊
243␉else␊
244␉{␊
245␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊
246␉}␊
247␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊
248␊
249␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊
250␉return(rtc_cyc_per_sec);␊
251}␊
252␊
253/*␊
254 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
255 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
256 *␉ a max multi. (used to calculate the FSB freq.),␊
257 *␉ and a current multi. (used to calculate the CPU freq.)␊
258 * - busFrequency = tscFrequency / multi␊
259 * - cpuFrequency = busFrequency * multi␊
260 */␊
261␊
262/* Decimal powers: */␊
263#define kilo (1000ULL)␊
264#define Mega (kilo * kilo)␊
265#define Giga (kilo * Mega)␊
266#define Tera (kilo * Giga)␊
267#define Peta (kilo * Tera)␊
268␊
269#define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊
270␊
271void get_cpuid(PlatformInfo_t *p)␊
272{␊
273␊
274␉char␉␉str[128];␊
275␉uint32_t␉reg[4];␊
276␉char␉␉*s␉␉␉= 0;␊
277␊
278␊
279␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊
280␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊
281␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊
282␊
283␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊
284␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); // Get the max extended cpuid␊
285␊
286␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊
287␉{␊
288␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
289␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
290␉}␊
291␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊
292␉{␊
293␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
294␉}␊
295␊
296// ==============================================================␊
297␊
298␉/* get BrandString (if supported) */␊
299␉/* Copyright: from Apple's XNU cpuid.c */␊
300␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊
301␉{␊
302␉␉bzero(str, 128);␊
303␉␉/*␊
304␉␉ * The BrandString 48 bytes (max), guaranteed to␊
305␉␉ * be NULL terminated.␊
306␉␉ */␊
307␉␉do_cpuid(0x80000002, reg);␊
308␉␉memcpy(&str[0], (char *)reg, 16);␊
309␉␉do_cpuid(0x80000003, reg);␊
310␉␉memcpy(&str[16], (char *)reg, 16);␊
311␉␉do_cpuid(0x80000004, reg);␊
312␉␉memcpy(&str[32], (char *)reg, 16);␊
313␉␉for (s = str; *s != '\0'; s++)␊
314␉␉{␊
315␉␉␉if (*s != ' ')␊
316␉␉␉{␊
317␉␉␉␉break;␊
318␉␉␉}␊
319␉␉}␊
320␉␉strlcpy(p->CPU.BrandString, s, 48);␊
321␊
322␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊
323␉␉{␊
324␉␉␉/*␊
325␉␉␉ * This string means we have a firmware-programmable brand string,␊
326␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
327␉␉␉ */␊
328␉␉␉p->CPU.BrandString[0] = '\0';␊
329␉␉}␊
330␉␉p->CPU.BrandString[47] = '\0';␊
331//␉␉DBG("\tBrandstring = %s\n", p->CPU.BrandString);␊
332␉}␊
333␊
334// ==============================================================␊
335␊
336␉switch(p->CPU.BrandString[0])␊
337␉{␊
338␉␉case 'A':␊
339␉␉␉/* AMD Processors */␊
340␉␉␉// The cache information is only in ecx and edx so only save␊
341␉␉␉// those registers␊
342␊
343␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊
344␊
345␉␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊
346␉␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊
347␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊
348␊
349␉␉␉break;␊
350␊
351␉␉case 'G':␊
352␉␉␉/* Intel Processors */␊
353␉␉␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); // Cache Index for Inte␊
354␊
355␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊
356␉␉␉{␊
357␉␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊
358␉␉␉}␊
359␊
360␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊
361␉␉␉{␊
362␉␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊
363␉␉␉}␊
364␊
365␉␉␉break;␊
366␉}␊
367}␊
368void scan_cpu(PlatformInfo_t *p)␊
369{␊
370␉verbose("[ CPU INFO ]\n");␊
371␉get_cpuid(p);␊
372␊
373␉uint64_t␉busFCvtt2n;␊
374␉uint64_t␉tscFCvtt2n;␊
375␉uint64_t␉tscFreq␉␉␉= 0;␊
376␉uint64_t␉busFrequency␉␉= 0;␊
377␉uint64_t␉cpuFrequency␉␉= 0;␊
378␉uint64_t␉msr␉␉␉= 0;␊
379␉uint64_t␉flex_ratio␉␉= 0;␊
380␉uint64_t␉cpuid_features;␊
381␊
382␉uint32_t␉max_ratio␉␉= 0;␊
383␉uint32_t␉min_ratio␉␉= 0;␊
384␉uint32_t␉reg[4];␊
385␉uint32_t␉cores_per_package␉= 0;␊
386␉uint32_t␉logical_per_package␉= 1;␊
387␉uint32_t␉threads_per_core␉= 1;␊
388␊
389␉uint8_t␉␉bus_ratio_max␉␉= 0;␊
390␉uint8_t␉␉bus_ratio_min␉␉= 0;␊
391␉uint8_t␉␉currdiv␉␉␉= 0;␊
392␉uint8_t␉␉currcoef␉␉= 0;␊
393␉uint8_t␉␉maxdiv␉␉␉= 0;␊
394␉uint8_t␉␉maxcoef␉␉␉= 0;␊
395␉uint8_t␉␉pic0_mask;␊
396␉uint8_t␉␉cpuMultN2␉␉= 0;␊
397␊
398␉const char␉*newratio;␊
399␊
400␉int␉␉len␉␉␉= 0;␊
401␉int␉␉myfsb␉␉␉= 0;␊
402␉int␉␉i␉␉␉= 0;␊
403␊
404␊
405/* http://www.flounder.com/cpuid_explorer2.htm␊
406 EAX (Intel):␊
407 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
408 +--------+----------------+--------+----+----+--------+--------+--------+␊
409 |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊
410 +--------+----------------+--------+----+----+--------+--------+--------+␊
411␊
412 EAX (AMD):␊
413 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊
414 +--------+----------------+--------+----+----+--------+--------+--------+␊
415 |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊
416 +--------+----------------+--------+----+----+--------+--------+--------+␊
417*/␊
418␉///////////////////-- MaxFn,Vendor --////////////////////////␊
419␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
420␊
421␉///////////////////-- Signature, stepping, features -- //////␊
422␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]);␊
423␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊
424␉{␊
425␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊
426␉}␊
427␉else␊
428␉{␊
429␉␉logical_per_package = 1;␊
430␉}␊
431␊
432␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
433␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊
434␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊
435␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊
436␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊
437␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊
438␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊
439␊
440␉if (p->CPU.Family == 0x0f)␊
441␉{␊
442␉␉p->CPU.Family += p->CPU.ExtFamily;␊
443␉}␊
444␊
445␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊
446␉{␊
447␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
448␉}␊
449␊
450␉switch (p->CPU.Vendor)␊
451␉{␊
452␉␉case CPUID_VENDOR_INTEL:␊
453␉␉{␊
454␉␉␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊
455␉␉␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊
456␉␉␉{␊
457␉␉␉␉for (i = 0; i < 0xFF; i++) // safe loop␊
458␉␉␉␉{␊
459␉␉␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊
460␉␉␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊
461␉␉␉␉␉{␊
462␉␉␉␉␉␉break;␊
463␉␉␉␉␉}␊
464␉␉␉␉␉cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊
465␉␉␉␉}␊
466␉␉␉}␊
467␊
468␉␉␉if (i > 0)␊
469␉␉␉{␊
470␉␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊
471␉␉␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊
472␉␉␉}␊
473␊
474␉␉␉if (cores_per_package == 0)␊
475␉␉␉{␊
476␉␉␉␉cores_per_package = 1;␊
477␉␉␉}␊
478␊
479␉␉␉switch (p->CPU.Model)␊
480␉␉␉{␊
481␉␉␉␉case CPUID_MODEL_NEHALEM:␊
482␉␉␉␉case CPUID_MODEL_FIELDS:␊
483␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
484␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
485␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
486␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
487␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
488␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
489␉␉␉␉case CPUID_MODEL_HASWELL:␊
490␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
491␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊
492␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
493␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
494␉␉␉␉//case CPUID_MODEL_:␊
495␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊
496␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊
497␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
498␉␉␉␉␉break;␊
499␊
500␉␉␉␉case CPUID_MODEL_DALES:␊
501␉␉␉␉case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core␊
502␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
503␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊
504␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊
505␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊
506␉␉␉␉␉break;␊
507␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
508␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊
509␉␉␉␉␉p->CPU.NoThreads␉= 4;␊
510␉␉␉␉␉break;␊
511␉␉␉}␊
512␊
513␉␉␉if (p->CPU.NoCores == 0)␊
514␉␉␉{␊
515␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
516␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
517␉␉␉}␊
518␊
519␉␉␉// MSR is *NOT* available on the Intel Atom CPU␊
520␉␉␉//workaround for N270. I don't know why it detected wrong␊
521␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊
522␉␉␉{␊
523␉␉␉␉p->CPU.NoCores␉␉= 1;␊
524␉␉␉␉p->CPU.NoThreads␉= 2;␊
525␉␉␉}␊
526␊
527␉␉␉//workaround for Quad␊
528␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊
529␉␉␉{␊
530␉␉␉␉p->CPU.NoCores␉␉= 4;␊
531␉␉␉␉p->CPU.NoThreads␉= 4;␊
532␉␉␉}␊
533␊
534␉␉␉//workaround for Xeon Harpertown␊
535␊
536␉␉␉if ( strstr(p->CPU.BrandString, "E5405") )␊
537␉␉␉{␊
538␉␉␉␉p->CPU.NoCores␉␉= 4;␊
539␉␉␉␉p->CPU.NoThreads␉= 4;␊
540␉␉␉}␊
541␉␉}␊
542␊
543␉␉break;␊
544␊
545␉␉case CPUID_VENDOR_AMD:␊
546␉␉{␊
547␊
548␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊
549␉␉␉threads_per_core = cores_per_package;␊
550␊
551␉␉␉if (cores_per_package == 0)␊
552␉␉␉{␊
553␉␉␉␉cores_per_package = 1;␊
554␉␉␉}␊
555␊
556␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊
557␉␉␉p->CPU.NoThreads␉= logical_per_package;␊
558␊
559␉␉␉if (p->CPU.NoCores == 0)␊
560␉␉␉{␊
561␉␉␉␉p->CPU.NoCores = 1;␊
562␉␉␉␉p->CPU.NoThreads␉= 1;␊
563␉␉␉}␊
564␉␉}␊
565␉␉break;␊
566␊
567␉␉default :␊
568␉␉␉stop("Unsupported CPU detected! System halted.");␊
569␉}␊
570␊
571␉/* setup features */␊
572␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
573␉{␊
574␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊
575␉}␊
576␊
577␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
578␉{␊
579␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊
580␉}␊
581␊
582␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
583␉{␊
584␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊
585␉}␊
586␊
587␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
588␉{␊
589␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊
590␉}␊
591␊
592␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
593␉{␊
594␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊
595␉}␊
596␊
597␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊
598␉{␊
599␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊
600␉}␊
601␊
602␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊
603␉{␊
604␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊
605␉}␊
606␊
607␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊
608␉{␊
609␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊
610␉}␊
611␊
612␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊
613␉{␊
614␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
615␉}␊
616␊
617␉pic0_mask = inb(0x21U);␊
618␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊
619␊
620␉uint64_t cycles;␊
621␉cycles = timeRDTSC();␊
622␉tscFreq = rtc_set_cyc_per_sec(cycles);␊
623␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊
624␉// if usual method failed␊
625␉if ( tscFreq < 1000 )␉//TEST␊
626␉{␊
627␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊
628␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊
629␉}␊
630␊
631␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊
632␉{␊
633␉␉int intelCPU = p->CPU.Model;␊
634␉␉if (p->CPU.Family == 0x06)␊
635␉␉{␊
636␉␉␉/* Nehalem CPU model */␊
637␉␉␉switch (p->CPU.Model)␊
638␉␉␉{␊
639␉␉␉␉case CPUID_MODEL_NEHALEM:␊
640␉␉␉␉case CPUID_MODEL_FIELDS:␊
641␉␉␉␉case CPUID_MODEL_CLARKDALE:␊
642␉␉␉␉case CPUID_MODEL_DALES:␊
643␉␉␉␉case CPUID_MODEL_WESTMERE:␊
644␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊
645␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊
646/* --------------------------------------------------------- */␊
647␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊
648␉␉␉␉case CPUID_MODEL_JAKETOWN:␊
649␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊
650␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊
651␉␉␉␉case CPUID_MODEL_ATOM_3700:␊
652␉␉␉␉case CPUID_MODEL_HASWELL:␊
653␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊
654␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊
655␊
656␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊
657␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊
658/* --------------------------------------------------------- */␊
659␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
660␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
661␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
662␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
663␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
664␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
665␉␉␉␉␉if (bitfield(msr, 16, 16))␊
666␉␉␉␉␉{␊
667␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
668␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊
669␉␉␉␉␉␉// where the cpu multipler can't be changed to␊
670␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
671␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊
672␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊
673␉␉␉␉␉␉// causing the system to crash since tscGranularity␊
674␉␉␉␉␉␉// is inadvertently set to 0.␊
675␊
676␉␉␉␉␉␉if (flex_ratio == 0)␊
677␉␉␉␉␉␉{␊
678␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊
679␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊
680␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
681␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊
682␉␉␉␉␉␉}␊
683␉␉␉␉␉␉else␊
684␉␉␉␉␉␉{␊
685␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊
686␉␉␉␉␉␉␉{␊
687␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊
688␉␉␉␉␉␉␉}␊
689␉␉␉␉␉␉}␊
690␉␉␉␉␉}␊
691␊
692␉␉␉␉␉if (bus_ratio_max)␊
693␉␉␉␉␉{␊
694␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊
695␉␉␉␉␉}␊
696␊
697␉␉␉␉␉//valv: Turbo Ratio Limit␊
698␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊
699␉␉␉␉␉{␊
700␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊
701␊
702␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊
703␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊
704␉␉␉␉␉}␊
705␉␉␉␉␉else␊
706␉␉␉␉␉{␊
707␉␉␉␉␉␉cpuFrequency = tscFreq;␊
708␉␉␉␉␉}␊
709␊
710␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊
711␉␉␉␉␉{␊
712␉␉␉␉␉␉max_ratio = atoi(newratio);␊
713␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊
714␉␉␉␉␉␉if (len >= 3)␊
715␉␉␉␉␉␉{␊
716␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊
717␉␉␉␉␉␉}␊
718␊
719␉␉␉␉␉␉verbose("\tBus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊
720␊
721␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊
722␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊
723␉␉␉␉␉␉{␊
724␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊
725␉␉␉␉␉␉␉if (len >= 3)␊
726␉␉␉␉␉␉␉{␊
727␉␉␉␉␉␉␉␉maxdiv = 1;␊
728␉␉␉␉␉␉␉}␊
729␉␉␉␉␉␉␉else␊
730␉␉␉␉␉␉␉{␊
731␉␉␉␉␉␉␉␉maxdiv = 0;␊
732␉␉␉␉␉␉␉}␊
733␉␉␉␉␉␉}␊
734␉␉␉␉␉␉else␊
735␉␉␉␉␉␉{␊
736␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊
737␉␉␉␉␉␉}␊
738␉␉␉␉␉}␊
739␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊
740␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊
741␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊
742␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊
743␊
744␉␉␉␉myfsb = busFrequency / 1000000;␊
745␉␉␉␉verbose("\tSticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊
746␉␉␉␉currcoef = bus_ratio_max;␊
747␊
748␉␉␉␉break;␊
749␊
750␉␉␉default:␊
751␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
752␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊
753␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊
754␉␉␉␉// Non-integer bus ratio for the max-multi␊
755␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊
756␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊
757␉␉␉␉currdiv = bitfield(msr, 14, 14);␊
758␊
759␉␉␉␉// This will always be model >= 3␊
760␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊
761␉␉␉␉{␊
762␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
763␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊
764␉␉␉␉}␊
765␉␉␉␉else␊
766␉␉␉␉{␊
767␉␉␉␉␉// On lower models, currcoef defines TSC freq␊
768␉␉␉␉␉// XXX␊
769␉␉␉␉␉maxcoef = currcoef;␊
770␉␉␉␉}␊
771␊
772␉␉␉␉if (!currcoef)␊
773␉␉␉␉{␊
774␉␉␉␉␉currcoef = maxcoef;␊
775␉␉␉␉}␊
776␊
777␉␉␉␉if (maxcoef)␊
778␉␉␉␉{␊
779␉␉␉␉␉if (maxdiv)␊
780␉␉␉␉␉{␊
781␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊
782␉␉␉␉␉}␊
783␉␉␉␉␉else␊
784␉␉␉␉␉{␊
785␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊
786␉␉␉␉␉}␊
787␊
788␉␉␉␉␉if (currdiv)␊
789␉␉␉␉␉{␊
790␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊
791␉␉␉␉␉}␊
792␉␉␉␉␉else␊
793␉␉␉␉␉{␊
794␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊
795␉␉␉␉␉}␊
796␊
797␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
798␉␉␉␉}␊
799␉␉␉␉break;␊
800␉␉␉}␊
801␉␉}␊
802␉␉// Mobile CPU␊
803␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊
804␉␉{␊
805␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
806␉␉}␊
807␉}␊
808␊
809␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊
810␉{␊
811␉␉switch(p->CPU.Family)␊
812␉␉{␊
813␉␉␉case 0xF: /* K8 */␊
814␉␉␉{␊
815␉␉␉␉uint64_t fidvid = 0;␊
816␉␉␉␉uint64_t cpuMult;␊
817␉␉␉␉uint64_t fid;␊
818␊
819␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊
820␉␉␉␉fid = bitfield(fidvid, 5, 0);␊
821␊
822␉␉␉␉cpuMult = (fid + 8) / 2;␊
823␉␉␉␉currcoef = cpuMult;␊
824␊
825␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊
826␉␉␉␉currdiv = cpuMultN2;␊
827␉␉␉␉/****** Addon END ******/␊
828␉␉␉}␊
829␉␉␉␉break;␊
830␊
831␉␉␉case 0x10: /*** AMD Family 10h ***/␊
832␉␉␉{␊
833␉␉␉␉uint64_t cofvid = 0;␊
834␉␉␉␉uint64_t cpuMult;␊
835␉␉␉␉uint64_t divisor = 0;␊
836␉␉␉␉uint64_t did;␊
837␉␉␉␉uint64_t fid;␊
838␊
839␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
840␉␉␉␉did = bitfield(cofvid, 8, 6);␊
841␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
842␉␉␉␉if (did == 0) divisor = 2;␊
843␉␉␉␉else if (did == 1) divisor = 4;␊
844␉␉␉␉else if (did == 2) divisor = 8;␊
845␉␉␉␉else if (did == 3) divisor = 16;␊
846␉␉␉␉else if (did == 4) divisor = 32;␊
847␊
848␉␉␉␉cpuMult = (fid + 16) / divisor;␊
849␉␉␉␉currcoef = cpuMult;␊
850␊
851␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
852␉␉␉␉currdiv = cpuMultN2;␊
853␊
854␉␉␉␉/****** Addon END ******/␊
855␉␉␉}␊
856␉␉␉break;␊
857␊
858␉␉␉case 0x11: /*** AMD Family 11h ***/␊
859␉␉␉{␊
860␉␉␉␉uint64_t cofvid = 0;␊
861␉␉␉␉uint64_t cpuMult;␊
862␉␉␉␉uint64_t divisor = 0;␊
863␉␉␉␉uint64_t did;␊
864␉␉␉␉uint64_t fid;␊
865␊
866␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
867␉␉␉␉did = bitfield(cofvid, 8, 6);␊
868␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
869␉␉␉␉if (did == 0) divisor = 2;␊
870␉␉␉␉else if (did == 1) divisor = 4;␊
871␉␉␉␉else if (did == 2) divisor = 8;␊
872␉␉␉␉else if (did == 3) divisor = 16;␊
873␉␉␉␉else if (did == 4) divisor = 32;␊
874␊
875␉␉␉␉cpuMult = (fid + 8) / divisor;␊
876␉␉␉␉currcoef = cpuMult;␊
877␊
878␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
879␉␉␉␉currdiv = cpuMultN2;␊
880␊
881␉␉␉␉/****** Addon END ******/␊
882␉␉␉}␊
883 break;␊
884␊
885␉␉␉case 0x12: /*** AMD Family 12h ***/␊
886␉␉␉{␊
887␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊
888␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊
889␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊
890␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
891␊
892␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊
893␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊
894␉␉␉␉uint64_t divisor;␊
895␉␉␉␉switch (CpuDid)␊
896␉␉␉␉{␊
897␉␉␉␉␉case 0: divisor = 1; break;␊
898␉␉␉␉␉case 1: divisor = (3/2); break;␊
899␉␉␉␉␉case 2: divisor = 2; break;␊
900␉␉␉␉␉case 3: divisor = 3; break;␊
901␉␉␉␉␉case 4: divisor = 4; break;␊
902␉␉␉␉␉case 5: divisor = 6; break;␊
903␉␉␉␉␉case 6: divisor = 8; break;␊
904␉␉␉␉␉case 7: divisor = 12; break;␊
905␉␉␉␉␉case 8: divisor = 16; break;␊
906␉␉␉␉␉default: divisor = 1; break;␊
907␉␉␉␉}␊
908␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊
909␊
910␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
911␉␉␉␉currdiv = cpuMultN2;␊
912␊
913␉␉␉}␊
914␉␉␉␉break;␊
915␊
916␉␉␉case 0x14: /* K14 */␊
917␊
918␉␉␉{␊
919␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊
920␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊
921␉␉␉␉uint64_t prfsts;␊
922␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
923␊
924␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊
925␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊
926␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊
927␊
928␉␉␉␉uint64_t frequencyId = 0x10;␊
929␉␉␉␉currcoef = (frequencyId + 0x10) /␊
930␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊
931␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊
932␉␉␉␉currdiv += bitfield(msr, 3, 0);␊
933␊
934␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊
935␉␉␉␉currdiv = cpuMultN2;␊
936␉␉␉}␊
937␊
938␉␉␉␉break;␊
939␊
940␉␉␉case 0x15: /*** AMD Family 15h ***/␊
941␉␉␉case 0x06: /*** AMD Family 06h ***/␊
942␉␉␉{␊
943␊
944␉␉␉␉uint64_t cofvid = 0;␊
945␉␉␉␉uint64_t cpuMult;␊
946␉␉␉␉uint64_t divisor = 0;␊
947␉␉␉␉uint64_t did;␊
948␉␉␉␉uint64_t fid;␊
949␊
950␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
951␉␉␉␉did = bitfield(cofvid, 8, 6);␊
952␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
953␉␉␉␉if (did == 0) divisor = 2;␊
954␉␉␉␉else if (did == 1) divisor = 4;␊
955␉␉␉␉else if (did == 2) divisor = 8;␊
956␉␉␉␉else if (did == 3) divisor = 16;␊
957␉␉␉␉else if (did == 4) divisor = 32;␊
958␊
959␉␉␉␉cpuMult = (fid + 16) / divisor;␊
960␉␉␉␉currcoef = cpuMult;␊
961␊
962␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
963␉␉␉␉currdiv = cpuMultN2;␊
964␉␉␉}␊
965␉␉␉␉break;␊
966␊
967␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊
968␉␉␉{␊
969␉␉␉␉uint64_t cofvid = 0;␊
970␉␉␉␉uint64_t cpuMult;␊
971␉␉␉␉uint64_t divisor = 0;␊
972␉␉␉␉uint64_t did;␊
973␉␉␉␉uint64_t fid;␊
974␊
975␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊
976␉␉␉␉did = bitfield(cofvid, 8, 6);␊
977␉␉␉␉fid = bitfield(cofvid, 5, 0);␊
978␉␉␉␉if (did == 0) divisor = 1;␊
979␉␉␉␉else if (did == 1) divisor = 2;␊
980␉␉␉␉else if (did == 2) divisor = 4;␊
981␉␉␉␉else if (did == 3) divisor = 8;␊
982␉␉␉␉else if (did == 4) divisor = 16;␊
983␊
984␉␉␉␉cpuMult = (fid + 16) / divisor;␊
985␉␉␉␉currcoef = cpuMult;␊
986␊
987␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊
988␉␉␉␉currdiv = cpuMultN2;␊
989␉␉␉␉/****** Addon END ******/␊
990␉␉␉}␊
991␉␉␉␉break;␊
992␊
993␉␉␉default:␊
994␉␉␉{␊
995␉␉␉␉typedef unsigned long long vlong;␊
996␉␉␉␉uint64_t prfsts;␊
997␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊
998␉␉␉␉uint64_t r;␊
999␉␉␉␉vlong hz;␊
1000␉␉␉␉r = (prfsts>>6) & 0x07;␊
1001␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊
1002␊
1003␉␉␉␉currcoef = hz / (200 * Mega);␊
1004␉␉␉}␊
1005␉␉}␊
1006␊
1007␉␉if (currcoef)␊
1008␉␉{␊
1009␉␉␉if (currdiv)␊
1010␉␉␉{␊
1011␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊
1012␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1013␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊
1014␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1015␊
1016␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
1017␉␉␉}␊
1018␉␉␉else␊
1019␉␉␉{␊
1020␉␉␉␉busFrequency = (tscFreq / currcoef);␊
1021␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊
1022␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊
1023␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊
1024␉␉␉␉DBG("%d\n", currcoef);␊
1025␉␉␉}␊
1026␉␉}␊
1027␉␉else if (!cpuFrequency)␊
1028␉␉{␊
1029␉␉␉cpuFrequency = tscFreq;␊
1030␉␉}␊
1031␉}␊
1032␊
1033#if 0␊
1034␉if (!busFrequency)␊
1035␉{␊
1036␉␉busFrequency = (DEFAULT_FSB * 1000);␊
1037␉␉DBG("\tCPU: busFrequency = 0! using the default value for FSB!\n");␊
1038␉␉cpuFrequency = tscFreq;␊
1039␉}␊
1040␊
1041␉DBG("\tcpu freq = 0x%016llxn", timeRDTSC() * 20);␊
1042␊
1043#endif␊
1044␊
1045␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊
1046␊
1047␉p->CPU.MaxCoef = maxcoef = currcoef;␊
1048␉p->CPU.MaxDiv = maxdiv = currdiv;␊
1049␉p->CPU.CurrCoef = currcoef;␊
1050␉p->CPU.CurrDiv = currdiv;␊
1051␉p->CPU.TSCFrequency = tscFreq;␊
1052␉p->CPU.FSBFrequency = busFrequency;␊
1053␉p->CPU.CPUFrequency = cpuFrequency;␊
1054␊
1055␉// keep formatted with spaces instead of tabs␊
1056␊
1057␉DBG("\tCPUID Raw Values:\n");␊
1058␉for (i = 0; i < CPUID_MAX; i++)␊
1059␉{␊
1060␉␉DBG("\t%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊
1061␉}␊
1062␉DBG("\n");␊
1063␉DBG("\tBrand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊
1064␉DBG("\tVendor: 0x%X\n",␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊
1065␉DBG("\tFamily: 0x%X\n",␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊
1066␉DBG("\tExtFamily: 0x%X\n",␉p->CPU.ExtFamily);␊
1067␉DBG("\tSignature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊
1068␉/*switch (p->CPU.Type) {␊
1069␉␉case PT_OEM:␊
1070␉␉␉DBG("\tProcessor type: Intel Original OEM Processor\n");␊
1071␉␉␉break;␊
1072␉␉case PT_OD:␊
1073␉␉␉DBG("\tProcessor type: Intel Over Drive Processor\n");␊
1074␉␉␉break;␊
1075␉␉case PT_DUAL:␊
1076␉␉␉DBG("\tProcessor type: Intel Dual Processor\n");␊
1077␉␉␉break;␊
1078␉␉case PT_RES:␊
1079␉␉␉DBG("\tProcessor type: Intel Reserved\n");␊
1080␉␉␉break;␊
1081␉␉default:␊
1082␉␉␉break;␊
1083␉}*/␊
1084␉DBG("\tModel: 0x%X\n",␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊
1085␉DBG("\tExtModel: 0x%X\n",␉p->CPU.ExtModel);␊
1086␉DBG("\tStepping: 0x%X\n",␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊
1087␉DBG("\tMaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊
1088␉DBG("\tCurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊
1089␉DBG("\tMaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊
1090␉DBG("\tCurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊
1091␉DBG("\tTSCFreq: %dMHz\n",␉p->CPU.TSCFrequency / 1000000);␊
1092␉DBG("\tFSBFreq: %dMHz\n",␉p->CPU.FSBFrequency / 1000000);␊
1093␉DBG("\tCPUFreq: %dMHz\n",␉p->CPU.CPUFrequency / 1000000);␊
1094␉DBG("\tCores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊
1095␉DBG("\tLogical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊
1096␉DBG("\tFeatures: 0x%08x\n",␉p->CPU.Features);␊
1097␊
1098␉verbose("\n");␊
1099#if DEBUG_CPU␊
1100␉pause();␊
1101#endif␊
1102}␊
1103

Archive Download this file

Revision: 2783