1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␊ |
19 | #endif␊ |
20 | ␊ |
21 | ␊ |
22 | bool getProcessorInformationExternalClock(returnType *value)␊ |
23 | {␊ |
24 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
25 | ␉␉switch (Platform.CPU.Family) {␊ |
26 | ␉␉␉case 0x06:␊ |
27 | ␉␉␉{␊ |
28 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
29 | ␉␉␉␉{␊ |
30 | // sets external clock to 0␊ |
31 | // removes FSB info from system profiler as on real mac's.␊ |
32 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊ |
33 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊ |
34 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊ |
35 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␊ |
36 | ␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊ |
37 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊ |
38 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊ |
39 | case CPU_MODEL_BROADWELL:␊ |
40 | case CPU_MODEL_BRODWELL_SVR:␊ |
41 | case CPU_MODEL_BRODWELL_MSVR:␊ |
42 | ␊ |
43 | ␉␉␉␉␉␉value->word = 0;␊ |
44 | ␉␉␉␉␉␉break;␊ |
45 | ␉␉␉␉␉default:␊ |
46 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
47 | ␉␉␉␉}␊ |
48 | ␉␉␉}␊ |
49 | ␉␉␉␉break;␊ |
50 | ␊ |
51 | ␉␉␉default:␊ |
52 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
53 | ␉␉}␊ |
54 | ␉} else {␊ |
55 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
56 | ␉}␊ |
57 | ␊ |
58 | ␉return true;␊ |
59 | }␊ |
60 | ␊ |
61 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
62 | {␊ |
63 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
64 | ␉return true;␊ |
65 | }␊ |
66 | ␊ |
67 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
68 | {␊ |
69 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
70 | ␉␉switch (Platform.CPU.Family) {␊ |
71 | ␉␉␉case 0x06:␊ |
72 | ␉␉␉{␊ |
73 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
74 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␊ |
75 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉// Intel Pentium M␊ |
76 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
77 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
78 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
79 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
80 | ␉␉␉␉␉␉return false;␊ |
81 | ␊ |
82 | ␉␉␉␉␉case 0x19:␊ |
83 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
84 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
85 | ␉␉␉␉␉case CPU_MODEL_DALES:␊ |
86 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
87 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
88 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
89 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
90 | //␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm) // MacMan removed not valid for this CPU␊ |
91 | //␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm) // MacMan removed not valid for this CPU␊ |
92 | //␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON: // MacMan moved␊ |
93 | //␉␉␉␉␉case CPU_MODEL_HASWELL: // MacMan removed not valid for this CPU␊ |
94 | //␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)// MacMan moved␊ |
95 | ␉␉␉␉␉{␊ |
96 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
97 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
98 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
99 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
100 | ␉␉␉␉␉␉unsigned int i;␊ |
101 | ␉␉␉␉␉␉␊ |
102 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
103 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
104 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++) {␊ |
105 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
106 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
107 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
108 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
109 | ␉␉␉␉␉␉␉␊ |
110 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00) {␊ |
111 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊ |
112 | ␉␉␉␉␉␉␉}␊ |
113 | ␉␉␉␉␉␉}␊ |
114 | ␊ |
115 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
116 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
117 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
118 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
119 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
120 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
121 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0) {␊ |
122 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
123 | ␉␉␉␉␉␉}␊ |
124 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
125 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
126 | ␉␉␉␉␉␉return true;␊ |
127 | ␉␉␉␉␉}␊ |
128 | // MacMan the following CPUs have fixed DMI2 speeds␊ |
129 | case CPU_MODEL_IVYBRIDGE_XEON: // Intel Core i7, Xeon E5 v2 LGA2011 (22nm)␊ |
130 | ␉␉␉␉␉case CPU_MODEL_JAKETOWN: // Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
131 | case CPU_MODEL_HASWELL_SVR: // Intel Core i7, Xeon E5 LGA2011v3␊ |
132 | {␊ |
133 | unsigned long dmi2speed;␊ |
134 | dmi2speed = 5000;␊ |
135 | DBG("dmi2speed %d\n", dmi2speed);␊ |
136 | ␉␉␉␉␉␉value->word = dmi2speed;␊ |
137 | ␉␉␉␉␉␉return true;␊ |
138 | }␊ |
139 | ␉␉␉␉␉default:␊ |
140 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
141 | ␉␉␉␉}␊ |
142 | ␉␉␉}␊ |
143 | ␉␉␉default:␊ |
144 | ␉␉␉␉break;␊ |
145 | ␉␉}␊ |
146 | ␉}␊ |
147 | ␉return false;␊ |
148 | }␊ |
149 | ␊ |
150 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
151 | {␊ |
152 | ␉if (Platform.CPU.NoCores >= 4) {␊ |
153 | ␉␉return 0x501;␉// 1281 - Quad-Core Xeon␊ |
154 | ␉} else if (Platform.CPU.NoCores == 1) {␊ |
155 | ␉␉return 0x201;␉// 513 - Core Solo␊ |
156 | ␉};␊ |
157 | ␉␊ |
158 | ␉return 0x301;␉␉// 769 - Core 2 Duo␊ |
159 | }␊ |
160 | ␊ |
161 | bool getSMBOemProcessorType(returnType *value)␊ |
162 | {␊ |
163 | ␉static bool done = false;␊ |
164 | ␊ |
165 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
166 | ␊ |
167 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) { // Intel␊ |
168 | ␉␉if (!done) {␊ |
169 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
170 | ␉␉␉done = true;␊ |
171 | ␉␉}␊ |
172 | ␉␉// Bungo: fixes Oem Processor Type - better matching IMHO␊ |
173 | // MacMan changed OEM Processor Type ␊ |
174 | ␉␉switch (Platform.CPU.Family) {␊ |
175 | ␉␉␉case 0x06:␊ |
176 | ␉␉␉{␊ |
177 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
178 | ␊ |
179 | ␉␉␉␉␉case CPU_MODEL_DOTHAN:␉␉␉␉// 0x0D - Intel Pentium M model D␊ |
180 | ␉␉␉␉␉␉value->word = 0x101;␉␉␉// 257␊ |
181 | ␉␉␉␉␉␉return true;␊ |
182 | ␊ |
183 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
184 | ␉␉␉␉␉case CPU_MODEL_CELERON:␊ |
185 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
186 | ␉␉␉␉␉␉return true;␊ |
187 | ␊ |
188 | ␉␉␉␉␉case CPU_MODEL_XEON_MP:␉␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
189 | ␉␉␉␉␉␉value->word = 0x401;␉␉␉// 1025␊ |
190 | ␉␉␉␉␉␉return true;␊ |
191 | ␊ |
192 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
193 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
194 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
195 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉␉// 1026 - Xeon␊ |
196 | ␉␉␉␉␉␉}␊ |
197 | ␉␉␉␉␉case CPU_MODEL_PENTIUM_M:␉␉␉// 0x09 - Banias␊ |
198 | ␉␉␉␉␉case CPU_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
199 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
200 | ␉␉␉␉␉␉return true;␊ |
201 | ␊ |
202 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
203 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
204 | case CPU_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
205 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
206 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
207 | ␉␉␉␉␉␉␉return true;␊ |
208 | ␉␉␉␉␉␉}␊ |
209 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
210 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
211 | ␉␉␉␉␉␉␉return true;␊ |
212 | ␉␉␉␉␉␉}␊ |
213 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
214 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
215 | ␉␉␉␉␉␉␉return true;␊ |
216 | ␉␉␉␉␉␉}␊ |
217 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
218 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
219 | ␉␉␉␉␉␉␉return true;␊ |
220 | ␉␉␉␉␉␉}␊ |
221 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
222 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
223 | ␉␉␉␉␉␉}␊ |
224 | ␉␉␉␉␉␉return true;␊ |
225 | ␊ |
226 | case CPU_MODEL_NEHALEM:␉␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
227 | case CPU_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx, Xeon L75xx, LGA1567 (45nm)␊ |
228 | case CPU_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
229 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
230 | case CPU_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
231 | case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F - ␊ |
232 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
233 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
234 | ␉␉␉␉␉␉␉return true;␊ |
235 | ␉␉␉␉␉␉}␊ |
236 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
237 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
238 | ␉␉␉␉␉␉␉return true;␊ |
239 | ␉␉␉␉␉␉}␊ |
240 | ␉␉␉␉␉␉return true;␊ |
241 | ␊ |
242 | ␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
243 | case CPU_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
244 | case CPU_MODEL_BROADWELL: // 0x3C - Intel Core i3, i5, i7 (14nm)␊ |
245 | case CPU_MODEL_BRODWELL_SVR: // 0x4F␊ |
246 | case CPU_MODEL_BRODWELL_MSVR: // 0x56␊ |
247 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
248 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
249 | ␉␉␉␉␉␉␉return true;␊ |
250 | ␉␉␉␉␉␉}␊ |
251 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
252 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
253 | ␉␉␉␉␉␉␉return true;␊ |
254 | ␉␉␉␉␉␉}␊ |
255 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
256 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
257 | ␉␉␉␉␉␉␉return true;␊ |
258 | ␉␉␉␉␉␉}␊ |
259 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
260 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
261 | ␉␉␉␉␉␉␉return true;␊ |
262 | ␉␉␉␉␉␉}␊ |
263 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
264 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
265 | ␉␉␉␉␉␉}␊ |
266 | ␉␉␉␉␉␉return true;␊ |
267 | ␊ |
268 | ␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊ |
269 | ␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561␊ |
270 | ␉␉␉␉␉␉return true;␊ |
271 | ␊ |
272 | ␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊ |
273 | ␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
274 | ␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊ |
275 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)")) {␊ |
276 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
277 | ␉␉␉␉␉␉␉return true;␊ |
278 | ␉␉␉␉␉␉}␊ |
279 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊ |
280 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
281 | ␉␉␉␉␉␉␉return true;␊ |
282 | ␉␉␉␉␉␉}␊ |
283 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5")) {␊ |
284 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
285 | ␉␉␉␉␉␉␉return true;␊ |
286 | ␉␉␉␉␉␉}␊ |
287 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i7")) {␊ |
288 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
289 | ␉␉␉␉␉␉␉return true;␊ |
290 | ␉␉␉␉␉␉}␊ |
291 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2) {␊ |
292 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
293 | ␉␉␉␉␉␉}␊ |
294 | ␉␉␉␉␉␉return true;␊ |
295 | ␊ |
296 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
297 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
298 | ␉␉␉␉␉␉return true;␊ |
299 | ␊ |
300 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
301 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
302 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
303 | ␉␉␉␉␉␉return true;␊ |
304 | ␉␉␉␉␉default:␊ |
305 | ␉␉␉␉␉␉break; //Unsupported CPU type␊ |
306 | ␉␉␉␉}␊ |
307 | ␉␉␉}␊ |
308 | ␉␉␉default:␊ |
309 | ␉␉␉␉break;␊ |
310 | ␉␉}␊ |
311 | ␉}␊ |
312 | ␉␊ |
313 | ␉return false;␊ |
314 | }␊ |
315 | ␊ |
316 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
317 | {␊ |
318 | ␉static int idx = -1;␊ |
319 | ␉int␉map;␊ |
320 | ␊ |
321 | if (!bootInfo->memDetect) {␊ |
322 | return false;␊ |
323 | }␊ |
324 | ␊ |
325 | ␉idx++;␊ |
326 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
327 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
328 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0) {␊ |
329 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
330 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
331 | ␉␉␉return true;␊ |
332 | ␉␉}␊ |
333 | ␉}␊ |
334 | ␊ |
335 | value->byte = 2; // means Unknown␊ |
336 | return true;␊ |
337 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
338 | //␉return true;␊ |
339 | }␊ |
340 | ␊ |
341 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
342 | {␊ |
343 | ␉value->word = 0xFFFF;␊ |
344 | ␉return true;␊ |
345 | }␊ |
346 | ␊ |
347 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
348 | {␊ |
349 | ␉static int idx = -1;␊ |
350 | ␉int␉map;␊ |
351 | ␊ |
352 | if (!bootInfo->memDetect) {␊ |
353 | return false;␊ |
354 | }␊ |
355 | ␊ |
356 | ␉idx++;␊ |
357 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
358 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
359 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0) {␊ |
360 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
361 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
362 | ␉␉␉return true;␊ |
363 | ␉␉}␊ |
364 | ␉}␊ |
365 | ␊ |
366 | value->dword = 0; // means Unknown␊ |
367 | return true;␊ |
368 | //␉value->dword = 800;␊ |
369 | //␉return true;␊ |
370 | }␊ |
371 | ␊ |
372 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
373 | {␊ |
374 | ␉static int idx = -1;␊ |
375 | ␉int␉map;␊ |
376 | ␊ |
377 | if (!bootInfo->memDetect) {␊ |
378 | return false;␊ |
379 | }␊ |
380 | ␊ |
381 | ␉idx++;␊ |
382 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
383 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
384 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0) {␊ |
385 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
386 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
387 | ␉␉␉return true;␊ |
388 | ␉␉}␊ |
389 | ␉}␊ |
390 | ␊ |
391 | ␉value->string = NOT_AVAILABLE;␊ |
392 | ␉return true;␊ |
393 | }␊ |
394 | ␊ |
395 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
396 | {␊ |
397 | ␉static int idx = -1;␊ |
398 | ␉int␉map;␊ |
399 | ␊ |
400 | if (!bootInfo->memDetect) {␊ |
401 | return false;␊ |
402 | }␊ |
403 | ␊ |
404 | ␉idx++;␊ |
405 | ␊ |
406 | //␉DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
407 | ␊ |
408 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
409 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
410 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0) {␊ |
411 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
412 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
413 | ␉␉␉return true;␊ |
414 | ␉␉}␊ |
415 | ␉}␊ |
416 | ␊ |
417 | ␉value->string = NOT_AVAILABLE;␊ |
418 | ␉return true;␊ |
419 | }␊ |
420 | ␊ |
421 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
422 | {␊ |
423 | ␉static int idx = -1;␊ |
424 | ␉int␉map;␊ |
425 | ␊ |
426 | if (!bootInfo->memDetect) {␊ |
427 | return false;␊ |
428 | }␊ |
429 | ␊ |
430 | ␉idx++;␊ |
431 | ␉if (idx < MAX_RAM_SLOTS) {␊ |
432 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
433 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0) {␊ |
434 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
435 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
436 | ␉␉␉return true;␊ |
437 | ␉␉}␊ |
438 | ␉}␊ |
439 | ␊ |
440 | ␉value->string = NOT_AVAILABLE;␊ |
441 | ␉return true;␊ |
442 | }␊ |
443 | ␊ |
444 | ␊ |
445 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
446 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
447 | static const char * const SMTAG = "_SM_";␊ |
448 | static const char* const DMITAG = "_DMI_";␊ |
449 | ␊ |
450 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
451 | {␊ |
452 | ␉SMBEntryPoint␉*smbios;␊ |
453 | ␉/*␊ |
454 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
455 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
456 | ␉ */␊ |
457 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
458 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
459 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
460 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
461 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
462 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0) {␊ |
463 | ␉␉␉return smbios;␊ |
464 | ␉ }␊ |
465 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
466 | ␉}␊ |
467 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
468 | ␉pause();␊ |
469 | ␉return NULL;␊ |
470 | }␊ |
471 | ␊ |
472 | |