1 | /*␊ |
2 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
3 | * AsereBLN: 2009: cleanup and bugfix␊ |
4 | * Bronya: 2015 Improve AMD support, cleanup and bugfix␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "platform.h"␊ |
9 | #include "cpu.h"␊ |
10 | #include "bootstruct.h"␊ |
11 | #include "boot.h"␊ |
12 | ␊ |
13 | #ifndef DEBUG_CPU␊ |
14 | ␉#define DEBUG_CPU 0␊ |
15 | #endif␊ |
16 | ␊ |
17 | #if DEBUG_CPU␊ |
18 | ␉#define DBG(x...)␉␉printf(x)␊ |
19 | #else␊ |
20 | ␉#define DBG(x...)␊ |
21 | #endif␊ |
22 | ␊ |
23 | ␊ |
24 | #define UI_CPUFREQ_ROUNDING_FACTOR␉10000000␊ |
25 | ␊ |
26 | clock_frequency_info_t gPEClockFrequencyInfo;␊ |
27 | ␊ |
28 | static __unused uint64_t rdtsc32(void)␊ |
29 | {␊ |
30 | ␉unsigned int lo,hi;␊ |
31 | ␉__asm__ __volatile__ ("rdtsc" : "=a" (lo), "=d" (hi));␊ |
32 | ␉return ((uint64_t)hi << 32) | lo;␊ |
33 | }␊ |
34 | ␊ |
35 | /*␊ |
36 | * timeRDTSC()␊ |
37 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
38 | * It pauses until the value is latched in the counter␊ |
39 | * and then reads the time stamp counter to return to the caller.␊ |
40 | */␊ |
41 | static uint64_t timeRDTSC(void)␊ |
42 | {␊ |
43 | ␉int␉␉attempts = 0;␊ |
44 | ␉uint32_t ␉latchTime;␊ |
45 | ␉uint64_t␉saveTime,intermediate;␊ |
46 | ␉unsigned int␉timerValue, lastValue;␊ |
47 | ␉//boolean_t␉int_enabled;␊ |
48 | ␉/*␊ |
49 | ␉ * Table of correction factors to account for␊ |
50 | ␉ *␉ - timer counter quantization errors, and␊ |
51 | ␉ *␉ - undercounts 0..5␊ |
52 | ␉ */␊ |
53 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
54 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
55 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
56 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
57 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
58 | ␉uint64_t␉scale[6] = {␊ |
59 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
60 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
61 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
62 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
63 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
64 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
65 | ␉};␊ |
66 | ␊ |
67 | ␉//int_enabled = ml_set_interrupts_enabled(false);␊ |
68 | ␊ |
69 | restart:␊ |
70 | ␉if (attempts >= 3) // increase to up to 9 attempts.␊ |
71 | ␉{␊ |
72 | ␉␉// This will flash-reboot. TODO: Use tscPanic instead.␊ |
73 | ␉␉//printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
74 | ␉}␊ |
75 | ␉attempts++;␊ |
76 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
77 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
78 | ␉latchTime = rdtsc32();␉// get the time stamp to time␊ |
79 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
80 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
81 | ␉saveTime = rdtsc32();␉// now time how long a 20th a second is...␊ |
82 | ␉get_PIT2(&lastValue);␊ |
83 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
84 | ␉do {␊ |
85 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
86 | ␉␉if (timerValue > lastValue)␊ |
87 | ␉␉{␊ |
88 | ␉␉␉// Timer wrapped␊ |
89 | ␉␉␉set_PIT2(0);␊ |
90 | ␉␉␉disable_PIT2();␊ |
91 | ␉␉␉goto restart;␊ |
92 | ␉␉}␊ |
93 | ␉␉lastValue = timerValue;␊ |
94 | ␉} while (timerValue > 5);␊ |
95 | ␉//printf("timerValue␉ %d\n",timerValue);␊ |
96 | ␉//printf("intermediate 0x%016llX\n",intermediate);␊ |
97 | ␉//printf("saveTime␉ 0x%016llX\n",saveTime);␊ |
98 | ␊ |
99 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
100 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
101 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
102 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
103 | ␊ |
104 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
105 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
106 | ␊ |
107 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
108 | ␉return intermediate;␊ |
109 | }␊ |
110 | ␊ |
111 | /*␊ |
112 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
113 | */␊ |
114 | static uint64_t __unused measure_tsc_frequency(void)␊ |
115 | {␊ |
116 | ␉uint64_t tscStart;␊ |
117 | ␉uint64_t tscEnd;␊ |
118 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
119 | ␉unsigned long pollCount;␊ |
120 | ␉uint64_t retval = 0;␊ |
121 | ␉int i;␊ |
122 | ␊ |
123 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
124 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
125 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
126 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
127 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
128 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
129 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
130 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
131 | ␉ */␊ |
132 | ␉for(i = 0; i < 10; ++i)␊ |
133 | ␉{␊ |
134 | ␉␉enable_PIT2();␊ |
135 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
136 | ␉␉tscStart = rdtsc64();␊ |
137 | ␉␉pollCount = poll_PIT2_gate();␊ |
138 | ␉␉tscEnd = rdtsc64();␊ |
139 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
140 | ␉␉if (pollCount <= 1)␊ |
141 | ␉␉{␊ |
142 | ␉␉␉continue;␊ |
143 | ␉␉}␊ |
144 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
145 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
146 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
147 | ␉␉ */␊ |
148 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊ |
149 | ␉␉{␊ |
150 | ␉␉␉continue;␊ |
151 | ␉␉}␊ |
152 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
153 | ␉␉if ( (tscEnd - tscStart) < tscDelta )␊ |
154 | ␉␉{␊ |
155 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
156 | ␉␉}␊ |
157 | ␉}␊ |
158 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
159 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
160 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
161 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
162 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
163 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
164 | ␉ */␊ |
165 | ␊ |
166 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
167 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
168 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
169 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
170 | ␉ */␊ |
171 | ␉if (tscDelta > (1ULL<<32))␊ |
172 | ␉{␊ |
173 | ␉␉retval = 0;␊ |
174 | ␉}␊ |
175 | ␉else␊ |
176 | ␉{␊ |
177 | ␉␉retval = tscDelta * 1000 / 30;␊ |
178 | ␉}␊ |
179 | ␉disable_PIT2();␊ |
180 | ␉return retval;␊ |
181 | }␊ |
182 | ␊ |
183 | static uint64_t␉rtc_set_cyc_per_sec(uint64_t cycles);␊ |
184 | #define RTC_FAST_DENOM␉0xFFFFFFFF␊ |
185 | ␊ |
186 | inline static uint32_t␊ |
187 | create_mul_quant_GHZ(int shift, uint32_t quant)␊ |
188 | {␊ |
189 | ␉return (uint32_t)((((uint64_t)NSEC_PER_SEC/20) << shift) / quant);␊ |
190 | }␊ |
191 | ␊ |
192 | struct␉{␊ |
193 | ␉mach_timespec_t␉␉␉calend_offset;␊ |
194 | ␉boolean_t␉␉␉calend_is_set;␊ |
195 | ␊ |
196 | ␉int64_t␉␉␉␉calend_adjtotal;␊ |
197 | ␉int32_t␉␉␉␉calend_adjdelta;␊ |
198 | ␊ |
199 | ␉uint32_t␉␉␉boottime;␊ |
200 | ␊ |
201 | ␉mach_timebase_info_data_t␉timebase_const;␊ |
202 | ␊ |
203 | ␉decl_simple_lock_data(,lock)␉/* real-time clock device lock */␊ |
204 | } rtclock;␊ |
205 | ␊ |
206 | uint32_t␉␉rtc_quant_shift;␉/* clock to nanos right shift */␊ |
207 | uint32_t␉␉rtc_quant_scale;␉/* clock to nanos multiplier */␊ |
208 | uint64_t␉␉rtc_cyc_per_sec;␉/* processor cycles per sec */␊ |
209 | uint64_t␉␉rtc_cycle_count;␉/* clocks in 1/20th second */␊ |
210 | ␊ |
211 | static uint64_t rtc_set_cyc_per_sec(uint64_t cycles)␊ |
212 | {␊ |
213 | ␊ |
214 | ␉if (cycles > (NSEC_PER_SEC/20))␊ |
215 | ␉{␊ |
216 | ␉␉// we can use just a "fast" multiply to get nanos␊ |
217 | ␉␉rtc_quant_shift = 32;␊ |
218 | ␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊ |
219 | ␉␉rtclock.timebase_const.numer = rtc_quant_scale; // timeRDTSC is 1/20␊ |
220 | ␉␉rtclock.timebase_const.denom = (uint32_t)RTC_FAST_DENOM;␊ |
221 | ␉}␊ |
222 | ␉else␊ |
223 | ␉{␊ |
224 | ␉␉rtc_quant_shift = 26;␊ |
225 | ␉␉rtc_quant_scale = create_mul_quant_GHZ(rtc_quant_shift, (uint32_t)cycles);␊ |
226 | ␉␉rtclock.timebase_const.numer = NSEC_PER_SEC/20; // timeRDTSC is 1/20␊ |
227 | ␉␉rtclock.timebase_const.denom = (uint32_t)cycles;␊ |
228 | ␉}␊ |
229 | ␉rtc_cyc_per_sec = cycles*20;␉// multiply it by 20 and we are done..␊ |
230 | ␉// BUT we also want to calculate...␊ |
231 | ␊ |
232 | ␉cycles = ((rtc_cyc_per_sec + (UI_CPUFREQ_ROUNDING_FACTOR/2))␊ |
233 | / UI_CPUFREQ_ROUNDING_FACTOR)␊ |
234 | ␉* UI_CPUFREQ_ROUNDING_FACTOR;␊ |
235 | ␊ |
236 | ␉/*␊ |
237 | ␉ * Set current measured speed.␊ |
238 | ␉ */␊ |
239 | ␉if (cycles >= 0x100000000ULL)␊ |
240 | ␉{␊ |
241 | ␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = 0xFFFFFFFFUL;␊ |
242 | ␉}␊ |
243 | ␉else␊ |
244 | ␉{␊ |
245 | ␉␉gPEClockFrequencyInfo.cpu_clock_rate_hz = (unsigned long)cycles;␊ |
246 | ␉}␊ |
247 | ␉gPEClockFrequencyInfo.cpu_frequency_hz = cycles;␊ |
248 | ␊ |
249 | ␉//printf("[RTCLOCK_1] frequency %llu (%llu) %llu\n", cycles, rtc_cyc_per_sec,timeRDTSC() * 20);␊ |
250 | ␉return(rtc_cyc_per_sec);␊ |
251 | }␊ |
252 | ␊ |
253 | // Bronya C1E fix␊ |
254 | void post_startup_cpu_fixups(void)␊ |
255 | {␊ |
256 | ␉/*␊ |
257 | ␉ * Some AMD processors support C1E state. Entering this state will␊ |
258 | ␉ * cause the local APIC timer to stop, which we can't deal with at␊ |
259 | ␉ * this time.␊ |
260 | ␉ */␊ |
261 | ␊ |
262 | ␉uint64_t reg;␊ |
263 | ␉verbose("\tLooking to disable C1E if is already enabled by the BIOS:\n");␊ |
264 | ␉reg = rdmsr64(MSR_AMD_INT_PENDING_CMP_HALT);␊ |
265 | ␉/* Disable C1E state if it is enabled by the BIOS */␊ |
266 | ␉if ((reg >> AMD_ACTONCMPHALT_SHIFT) & AMD_ACTONCMPHALT_MASK)␊ |
267 | ␉{␊ |
268 | ␉␉reg &= ~(AMD_ACTONCMPHALT_MASK << AMD_ACTONCMPHALT_SHIFT);␊ |
269 | ␉␉wrmsr64(MSR_AMD_INT_PENDING_CMP_HALT, reg);␊ |
270 | ␉␉verbose("\tC1E disabled!\n");␊ |
271 | ␉}␊ |
272 | }␊ |
273 | ␊ |
274 | /*␊ |
275 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
276 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
277 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
278 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
279 | * - busFrequency = tscFrequency / multi␊ |
280 | * - cpuFrequency = busFrequency * multi␊ |
281 | */␊ |
282 | ␊ |
283 | /* Decimal powers: */␊ |
284 | #define kilo (1000ULL)␊ |
285 | #define Mega (kilo * kilo)␊ |
286 | #define Giga (kilo * Mega)␊ |
287 | #define Tera (kilo * Giga)␊ |
288 | #define Peta (kilo * Tera)␊ |
289 | ␊ |
290 | #define quad(hi,lo)␉(((uint64_t)(hi)) << 32 | (lo))␊ |
291 | ␊ |
292 | void get_cpuid(PlatformInfo_t *p)␊ |
293 | {␊ |
294 | ␊ |
295 | ␉char␉␉str[128];␊ |
296 | ␉uint32_t␉reg[4];␊ |
297 | ␉char␉␉*s␉␉␉= 0;␊ |
298 | ␊ |
299 | ␊ |
300 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊ |
301 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊ |
302 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊ |
303 | ␊ |
304 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊ |
305 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]); // Get the max extended cpuid␊ |
306 | ␊ |
307 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
308 | ␉{␊ |
309 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
310 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
311 | ␉}␊ |
312 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
313 | ␉{␊ |
314 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
315 | ␉}␊ |
316 | ␊ |
317 | // ==============================================================␊ |
318 | ␊ |
319 | ␉/* get BrandString (if supported) */␊ |
320 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
321 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
322 | ␉{␊ |
323 | ␉␉bzero(str, 128);␊ |
324 | ␉␉/*␊ |
325 | ␉␉ * The BrandString 48 bytes (max), guaranteed to␊ |
326 | ␉␉ * be NULL terminated.␊ |
327 | ␉␉ */␊ |
328 | ␉␉do_cpuid(0x80000002, reg);␊ |
329 | ␉␉memcpy(&str[0], (char *)reg, 16);␊ |
330 | ␉␉do_cpuid(0x80000003, reg);␊ |
331 | ␉␉memcpy(&str[16], (char *)reg, 16);␊ |
332 | ␉␉do_cpuid(0x80000004, reg);␊ |
333 | ␉␉memcpy(&str[32], (char *)reg, 16);␊ |
334 | ␉␉for (s = str; *s != '\0'; s++)␊ |
335 | ␉␉{␊ |
336 | ␉␉␉if (*s != ' ')␊ |
337 | ␉␉␉{␊ |
338 | ␉␉␉␉break;␊ |
339 | ␉␉␉}␊ |
340 | ␉␉}␊ |
341 | ␉␉strlcpy(p->CPU.BrandString, s, 48);␊ |
342 | ␊ |
343 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
344 | ␉␉{␊ |
345 | ␉␉␉/*␊ |
346 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
347 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
348 | ␉␉␉ */␊ |
349 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
350 | ␉␉}␊ |
351 | ␉␉p->CPU.BrandString[47] = '\0';␊ |
352 | //␉␉DBG("\tBrandstring = %s\n", p->CPU.BrandString);␊ |
353 | ␉}␊ |
354 | ␊ |
355 | // ==============================================================␊ |
356 | ␊ |
357 | ␉switch(p->CPU.BrandString[0])␊ |
358 | ␉{␊ |
359 | ␉␉case 'A':␊ |
360 | ␉␉␉/* AMD Processors */␊ |
361 | ␉␉␉// The cache information is only in ecx and edx so only save␊ |
362 | ␉␉␉// those registers␊ |
363 | ␊ |
364 | ␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]); // Monitor/Mwait␊ |
365 | ␊ |
366 | ␉␉␉do_cpuid(0x80000005, p->CPU.CPUID[CPUID_85]); // TLB/Cache/Prefetch␊ |
367 | ␉␉␉do_cpuid(0x80000006, p->CPU.CPUID[CPUID_86]); // TLB/Cache/Prefetch␊ |
368 | ␉␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
369 | ␊ |
370 | ␉␉␉break;␊ |
371 | ␊ |
372 | ␉␉case 'G':␊ |
373 | ␉␉␉/* Intel Processors */␊ |
374 | ␉␉␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]); // Cache Index for Inte␊ |
375 | ␊ |
376 | ␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5)␉// Monitor/Mwait␊ |
377 | ␉␉␉{␊ |
378 | ␉␉␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
379 | ␉␉␉}␊ |
380 | ␊ |
381 | ␉␉␉if (p->CPU.CPUID[CPUID_0][0] >= 6)␉// Thermal/Power␊ |
382 | ␉␉␉{␊ |
383 | ␉␉␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
384 | ␉␉␉}␊ |
385 | ␊ |
386 | ␉␉␉break;␊ |
387 | ␉}␊ |
388 | }␊ |
389 | void scan_cpu(PlatformInfo_t *p)␊ |
390 | {␊ |
391 | ␉verbose("[ CPU INFO ]\n");␊ |
392 | ␉get_cpuid(p);␊ |
393 | ␊ |
394 | ␉uint64_t␉busFCvtt2n;␊ |
395 | ␉uint64_t␉tscFCvtt2n;␊ |
396 | ␉uint64_t␉tscFreq␉␉␉= 0;␊ |
397 | ␉uint64_t␉busFrequency␉␉= 0;␊ |
398 | ␉uint64_t␉cpuFrequency␉␉= 0;␊ |
399 | ␉uint64_t␉msr␉␉␉= 0;␊ |
400 | ␉uint64_t␉flex_ratio␉␉= 0;␊ |
401 | ␉uint64_t␉cpuid_features;␊ |
402 | ␊ |
403 | ␉uint32_t␉max_ratio␉␉= 0;␊ |
404 | ␉uint32_t␉min_ratio␉␉= 0;␊ |
405 | ␉uint32_t␉reg[4];␊ |
406 | ␉uint32_t␉cores_per_package␉= 0;␊ |
407 | ␉uint32_t␉logical_per_package␉= 1;␊ |
408 | ␉uint32_t␉threads_per_core␉= 1;␊ |
409 | ␊ |
410 | ␉uint8_t␉␉bus_ratio_max␉␉= 0;␊ |
411 | ␉uint8_t␉␉bus_ratio_min␉␉= 0;␊ |
412 | ␉uint8_t␉␉currdiv␉␉␉= 0;␊ |
413 | ␉uint8_t␉␉currcoef␉␉= 0;␊ |
414 | ␉uint8_t␉␉maxdiv␉␉␉= 0;␊ |
415 | ␉uint8_t␉␉maxcoef␉␉␉= 0;␊ |
416 | ␉uint8_t␉␉pic0_mask;␊ |
417 | ␉uint8_t␉␉cpuMultN2␉␉= 0;␊ |
418 | ␊ |
419 | ␉const char␉*newratio;␊ |
420 | ␊ |
421 | ␉int␉␉len␉␉␉= 0;␊ |
422 | ␉int␉␉myfsb␉␉␉= 0;␊ |
423 | ␉int␉␉i␉␉␉= 0;␊ |
424 | ␊ |
425 | ␊ |
426 | /* http://www.flounder.com/cpuid_explorer2.htm␊ |
427 | EAX (Intel):␊ |
428 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
429 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
430 | |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊ |
431 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
432 | ␊ |
433 | EAX (AMD):␊ |
434 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
435 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
436 | |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊ |
437 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
438 | */␊ |
439 | ␉///////////////////-- MaxFn,Vendor --////////////////////////␊ |
440 | ␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊ |
441 | ␊ |
442 | ␉///////////////////-- Signature, stepping, features -- //////␊ |
443 | ␉cpuid_features = quad(p->CPU.CPUID[CPUID_1][ecx], p->CPU.CPUID[CPUID_1][edx]);␊ |
444 | ␉if (bit(28) & p->CPU.CPUID[CPUID_1][edx]) // HTT/Multicore␊ |
445 | ␉{␊ |
446 | ␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊ |
447 | ␉}␊ |
448 | ␉else␊ |
449 | ␉{␊ |
450 | ␉␉logical_per_package = 1;␊ |
451 | ␉}␊ |
452 | ␊ |
453 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
454 | ␉p->CPU.Stepping␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␉// stepping = cpu_feat_eax & 0xF;␊ |
455 | ␉p->CPU.Model␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␉// model = (cpu_feat_eax >> 4) & 0xF;␊ |
456 | ␉p->CPU.Family␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␉// family = (cpu_feat_eax >> 8) & 0xF;␊ |
457 | ␉//p->CPU.Type␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
458 | ␉p->CPU.ExtModel␉␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
459 | ␉p->CPU.ExtFamily␉= (uint8_t)bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
460 | ␊ |
461 | ␉if (p->CPU.Family == 0x0f)␊ |
462 | ␉{␊ |
463 | ␉␉p->CPU.Family += p->CPU.ExtFamily;␊ |
464 | ␉}␊ |
465 | ␊ |
466 | ␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊ |
467 | ␉{␊ |
468 | ␉␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
469 | ␉}␊ |
470 | ␊ |
471 | ␉switch (p->CPU.Vendor)␊ |
472 | ␉{␊ |
473 | ␉␉case CPUID_VENDOR_INTEL:␊ |
474 | ␉␉{␊ |
475 | ␉␉␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊ |
476 | ␉␉␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊ |
477 | ␉␉␉{␊ |
478 | ␉␉␉␉for (i = 0; i < 0xFF; i++) // safe loop␊ |
479 | ␉␉␉␉{␊ |
480 | ␉␉␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊ |
481 | ␉␉␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊ |
482 | ␉␉␉␉␉{␊ |
483 | ␉␉␉␉␉␉break;␊ |
484 | ␉␉␉␉␉}␊ |
485 | ␉␉␉␉␉cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊ |
486 | ␉␉␉␉}␊ |
487 | ␉␉␉}␊ |
488 | ␊ |
489 | ␉␉␉if (i > 0)␊ |
490 | ␉␉␉{␊ |
491 | ␉␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊ |
492 | ␉␉␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊ |
493 | ␉␉␉}␊ |
494 | ␊ |
495 | ␉␉␉if (cores_per_package == 0)␊ |
496 | ␉␉␉{␊ |
497 | ␉␉␉␉cores_per_package = 1;␊ |
498 | ␉␉␉}␊ |
499 | ␊ |
500 | ␉␉␉switch (p->CPU.Model)␊ |
501 | ␉␉␉{␊ |
502 | ␉␉␉␉case CPUID_MODEL_NEHALEM: // Intel Core i7 LGA1366 (45nm)␊ |
503 | ␉␉␉␉case CPUID_MODEL_FIELDS: // Intel Core i5, i7 LGA1156 (45nm)␊ |
504 | ␉␉␉␉case CPUID_MODEL_CLARKDALE: // Intel Core i3, i5, i7 LGA1156 (32nm)␊ |
505 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
506 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
507 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
508 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
509 | ␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊ |
510 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
511 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
512 | ␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊ |
513 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
514 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊ |
515 | ␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊ |
516 | ␉␉␉␉case CPUID_MODEL_BRODWELL_SVR:␊ |
517 | ␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊ |
518 | ␉␉␉␉//case CPUID_MODEL_:␊ |
519 | ␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT); // 0x35␊ |
520 | ␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊ |
521 | ␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
522 | ␉␉␉␉␉break;␊ |
523 | ␊ |
524 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
525 | ␉␉␉␉case CPUID_MODEL_WESTMERE: // Intel Core i7 LGA1366 (32nm) 6 Core␊ |
526 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
527 | ␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
528 | ␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊ |
529 | ␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
530 | ␉␉␉␉␉break;␊ |
531 | ␉␉␉␉case CPUID_MODEL_ATOM_3700:␊ |
532 | ␉␉␉␉case CPUID_MODEL_ATOM:␊ |
533 | ␉␉␉␉␉p->CPU.NoCores␉␉= 2;␊ |
534 | ␉␉␉␉␉p->CPU.NoThreads␉= 2;␊ |
535 | ␉␉␉␉␉break;␊ |
536 | ␉␉␉␉default:␊ |
537 | ␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊ |
538 | ␉␉␉␉␉break;␊ |
539 | ␉␉␉}␊ |
540 | ␊ |
541 | ␉␉␉if (p->CPU.NoCores == 0)␊ |
542 | ␉␉␉{␊ |
543 | ␉␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊ |
544 | ␉␉␉␉p->CPU.NoThreads␉= logical_per_package;␊ |
545 | ␉␉␉}␊ |
546 | ␊ |
547 | ␉␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
548 | ␉␉␉// workaround for N270. I don't know why it detected wrong␊ |
549 | ␉␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊ |
550 | ␉␉␉{␊ |
551 | ␉␉␉␉p->CPU.NoCores␉␉= 1;␊ |
552 | ␉␉␉␉p->CPU.NoThreads␉= 2;␊ |
553 | ␉␉␉}␊ |
554 | ␊ |
555 | ␊ |
556 | ␉␉␉// workaround for Xeon Harpertown and Yorkfield␊ |
557 | ␉␉␉if ((p->CPU.Model == CPUID_MODEL_PENRYN) &&␊ |
558 | ␉␉␉␉(p->CPU.NoCores␉== 0))␊ |
559 | ␉␉␉{␊ |
560 | ␉␉␉␉if ((strstr(p->CPU.BrandString, "X54")) ||␊ |
561 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "E54")) ||␊ |
562 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "W35")) ||␊ |
563 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "X34")) ||␊ |
564 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "X33")) ||␊ |
565 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "L33")) ||␊ |
566 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "X32")) ||␊ |
567 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "L3426")) ||␊ |
568 | ␉␉␉␉␉(strstr(p->CPU.BrandString, "L54")))␊ |
569 | ␉␉␉␉{␊ |
570 | ␉␉␉␉␉p->CPU.NoCores␉␉= 4;␊ |
571 | ␉␉␉␉␉p->CPU.NoThreads␉= 4;␊ |
572 | ␉␉␉␉} else if (strstr(p->CPU.BrandString, "W36")) {␊ |
573 | ␉␉␉␉␉p->CPU.NoCores␉␉= 6;␊ |
574 | ␉␉␉␉␉p->CPU.NoThreads␉= 6;␊ |
575 | ␉␉␉␉} else { //other Penryn and Wolfdale␊ |
576 | ␉␉␉␉␉p->CPU.NoCores␉␉= 0;␊ |
577 | ␉␉␉␉␉p->CPU.NoThreads␉= 0;␊ |
578 | ␉␉␉␉}␊ |
579 | ␉␉␉}␊ |
580 | ␊ |
581 | ␉␉␉// workaround for Quad␊ |
582 | ␉␉␉if ( strstr(p->CPU.BrandString, "Quad") )␊ |
583 | ␉␉␉{␊ |
584 | ␉␉␉␉p->CPU.NoCores␉␉= 4;␊ |
585 | ␉␉␉␉p->CPU.NoThreads␉= 4;␊ |
586 | ␉␉␉}␊ |
587 | ␉␉}␊ |
588 | ␊ |
589 | ␉␉break;␊ |
590 | ␊ |
591 | ␉␉case CPUID_VENDOR_AMD:␊ |
592 | ␉␉{␊ |
593 | ␉␉␉post_startup_cpu_fixups();␊ |
594 | ␉␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_88][ecx], 7, 0) + 1;␊ |
595 | ␉␉␉threads_per_core = cores_per_package;␊ |
596 | ␊ |
597 | ␉␉␉if (cores_per_package == 0)␊ |
598 | ␉␉␉{␊ |
599 | ␉␉␉␉cores_per_package = 1;␊ |
600 | ␉␉␉}␊ |
601 | ␊ |
602 | ␉␉␉p->CPU.NoCores␉␉= cores_per_package;␊ |
603 | ␉␉␉p->CPU.NoThreads␉= logical_per_package;␊ |
604 | ␊ |
605 | ␉␉␉if (p->CPU.NoCores == 0)␊ |
606 | ␉␉␉{␊ |
607 | ␉␉␉␉p->CPU.NoCores = 1;␊ |
608 | ␉␉␉␉p->CPU.NoThreads␉= 1;␊ |
609 | ␉␉␉}␊ |
610 | ␉␉}␊ |
611 | ␉␉break;␊ |
612 | ␊ |
613 | ␉␉default :␊ |
614 | ␉␉␉stop("Unsupported CPU detected! System halted.");␊ |
615 | ␉}␊ |
616 | ␊ |
617 | ␉/* setup features */␊ |
618 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
619 | ␉{␊ |
620 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
621 | ␉}␊ |
622 | ␊ |
623 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
624 | ␉{␊ |
625 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
626 | ␉}␊ |
627 | ␊ |
628 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
629 | ␉{␊ |
630 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
631 | ␉}␊ |
632 | ␊ |
633 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
634 | ␉{␊ |
635 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
636 | ␉}␊ |
637 | ␊ |
638 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
639 | ␉{␊ |
640 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
641 | ␉}␊ |
642 | ␊ |
643 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
644 | ␉{␊ |
645 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
646 | ␉}␊ |
647 | ␊ |
648 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
649 | ␉{␊ |
650 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
651 | ␉}␊ |
652 | ␊ |
653 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
654 | ␉{␊ |
655 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
656 | ␉}␊ |
657 | ␊ |
658 | ␉if ((p->CPU.NoThreads > p->CPU.NoCores))␊ |
659 | ␉{␊ |
660 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
661 | ␉}␊ |
662 | ␊ |
663 | ␉pic0_mask = inb(0x21U);␊ |
664 | ␉outb(0x21U, 0xFFU); // mask PIC0 interrupts for duration of timing tests␊ |
665 | ␊ |
666 | ␉uint64_t cycles;␊ |
667 | ␉cycles = timeRDTSC();␊ |
668 | ␉tscFreq = rtc_set_cyc_per_sec(cycles);␊ |
669 | ␉DBG("cpu freq classic = 0x%016llx\n", tscFreq);␊ |
670 | ␉// if usual method failed␊ |
671 | ␉if ( tscFreq < 1000 )␉//TEST␊ |
672 | ␉{␊ |
673 | ␉␉tscFreq = measure_tsc_frequency();//timeRDTSC() * 20;//measure_tsc_frequency();␊ |
674 | ␉␉// DBG("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
675 | ␉}␊ |
676 | ␊ |
677 | ␉if (p->CPU.Vendor==CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊ |
678 | ␉{␊ |
679 | ␉␉int intelCPU = p->CPU.Model;␊ |
680 | ␉␉if (p->CPU.Family == 0x06)␊ |
681 | ␉␉{␊ |
682 | ␉␉␉/* Nehalem CPU model */␊ |
683 | ␉␉␉switch (p->CPU.Model)␊ |
684 | ␉␉␉{␊ |
685 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
686 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
687 | ␉␉␉␉case CPUID_MODEL_CLARKDALE:␊ |
688 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
689 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
690 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
691 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
692 | /* --------------------------------------------------------- */␊ |
693 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
694 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
695 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
696 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
697 | ␉␉␉␉case CPUID_MODEL_ATOM_3700:␊ |
698 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
699 | ␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊ |
700 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
701 | ␊ |
702 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
703 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊ |
704 | ␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␊ |
705 | ␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␊ |
706 | /* --------------------------------------------------------- */␊ |
707 | ␉␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
708 | ␉␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
709 | ␉␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
710 | ␉␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
711 | ␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
712 | ␉␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
713 | ␉␉␉␉␉if (bitfield(msr, 16, 16))␊ |
714 | ␉␉␉␉␉{␊ |
715 | ␉␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
716 | ␉␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊ |
717 | ␉␉␉␉␉␉// where the cpu multipler can't be changed to␊ |
718 | ␉␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
719 | ␉␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊ |
720 | ␉␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊ |
721 | ␉␉␉␉␉␉// causing the system to crash since tscGranularity␊ |
722 | ␉␉␉␉␉␉// is inadvertently set to 0.␊ |
723 | ␊ |
724 | ␉␉␉␉␉␉if (flex_ratio == 0)␊ |
725 | ␉␉␉␉␉␉{␊ |
726 | ␉␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊ |
727 | ␉␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
728 | ␉␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
729 | ␉␉␉␉␉␉␉DBG("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
730 | ␉␉␉␉␉␉}␊ |
731 | ␉␉␉␉␉␉else␊ |
732 | ␉␉␉␉␉␉{␊ |
733 | ␉␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
734 | ␉␉␉␉␉␉␉{␊ |
735 | ␉␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
736 | ␉␉␉␉␉␉␉}␊ |
737 | ␉␉␉␉␉␉}␊ |
738 | ␉␉␉␉␉}␊ |
739 | ␊ |
740 | ␉␉␉␉␉if (bus_ratio_max)␊ |
741 | ␉␉␉␉␉{␊ |
742 | ␉␉␉␉␉␉busFrequency = (tscFreq / bus_ratio_max);␊ |
743 | ␉␉␉␉␉}␊ |
744 | ␊ |
745 | ␉␉␉␉␉//valv: Turbo Ratio Limit␊ |
746 | ␉␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
747 | ␉␉␉␉␉{␊ |
748 | ␉␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
749 | ␊ |
750 | ␉␉␉␉␉␉cpuFrequency = bus_ratio_max * busFrequency;␊ |
751 | ␉␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
752 | ␉␉␉␉␉}␊ |
753 | ␉␉␉␉␉else␊ |
754 | ␉␉␉␉␉{␊ |
755 | ␉␉␉␉␉␉cpuFrequency = tscFreq;␊ |
756 | ␉␉␉␉␉}␊ |
757 | ␊ |
758 | ␉␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
759 | ␉␉␉␉␉{␊ |
760 | ␉␉␉␉␉␉max_ratio = atoi(newratio);␊ |
761 | ␉␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
762 | ␉␉␉␉␉␉if (len >= 3)␊ |
763 | ␉␉␉␉␉␉{␊ |
764 | ␉␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
765 | ␉␉␉␉␉␉}␊ |
766 | ␊ |
767 | ␉␉␉␉␉␉verbose("\tBus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
768 | ␊ |
769 | ␉␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
770 | ␉␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
771 | ␉␉␉␉␉␉{␊ |
772 | ␉␉␉␉␉␉␉cpuFrequency = (busFrequency * max_ratio) / 10;␊ |
773 | ␉␉␉␉␉␉␉if (len >= 3)␊ |
774 | ␉␉␉␉␉␉␉{␊ |
775 | ␉␉␉␉␉␉␉␉maxdiv = 1;␊ |
776 | ␉␉␉␉␉␉␉}␊ |
777 | ␉␉␉␉␉␉␉else␊ |
778 | ␉␉␉␉␉␉␉{␊ |
779 | ␉␉␉␉␉␉␉␉maxdiv = 0;␊ |
780 | ␉␉␉␉␉␉␉}␊ |
781 | ␉␉␉␉␉␉}␊ |
782 | ␉␉␉␉␉␉else␊ |
783 | ␉␉␉␉␉␉{␊ |
784 | ␉␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
785 | ␉␉␉␉␉␉}␊ |
786 | ␉␉␉␉␉}␊ |
787 | ␉␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
788 | ␉␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊ |
789 | ␉␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
790 | ␉␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
791 | ␊ |
792 | ␉␉␉␉myfsb = busFrequency / 1000000;␊ |
793 | ␉␉␉␉verbose("\tSticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
794 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
795 | ␊ |
796 | ␉␉␉␉break;␊ |
797 | ␊ |
798 | ␉␉␉default:␊ |
799 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
800 | ␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
801 | ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
802 | ␉␉␉␉// Non-integer bus ratio for the max-multi␊ |
803 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
804 | ␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊ |
805 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
806 | ␊ |
807 | ␉␉␉␉// This will always be model >= 3␊ |
808 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
809 | ␉␉␉␉{␊ |
810 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
811 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
812 | ␉␉␉␉}␊ |
813 | ␉␉␉␉else␊ |
814 | ␉␉␉␉{␊ |
815 | ␉␉␉␉␉// On lower models, currcoef defines TSC freq␊ |
816 | ␉␉␉␉␉// XXX␊ |
817 | ␉␉␉␉␉maxcoef = currcoef;␊ |
818 | ␉␉␉␉}␊ |
819 | ␊ |
820 | ␉␉␉␉if (!currcoef)␊ |
821 | ␉␉␉␉{␊ |
822 | ␉␉␉␉␉currcoef = maxcoef;␊ |
823 | ␉␉␉␉}␊ |
824 | ␊ |
825 | ␉␉␉␉if (maxcoef)␊ |
826 | ␉␉␉␉{␊ |
827 | ␉␉␉␉␉if (maxdiv)␊ |
828 | ␉␉␉␉␉{␊ |
829 | ␉␉␉␉␉␉busFrequency = ((tscFreq * 2) / ((maxcoef * 2) + 1));␊ |
830 | ␉␉␉␉␉}␊ |
831 | ␉␉␉␉␉else␊ |
832 | ␉␉␉␉␉{␊ |
833 | ␉␉␉␉␉␉busFrequency = (tscFreq / maxcoef);␊ |
834 | ␉␉␉␉␉}␊ |
835 | ␊ |
836 | ␉␉␉␉␉if (currdiv)␊ |
837 | ␉␉␉␉␉{␊ |
838 | ␉␉␉␉␉␉cpuFrequency = (busFrequency * ((currcoef * 2) + 1) / 2);␊ |
839 | ␉␉␉␉␉}␊ |
840 | ␉␉␉␉␉else␊ |
841 | ␉␉␉␉␉{␊ |
842 | ␉␉␉␉␉␉cpuFrequency = (busFrequency * currcoef);␊ |
843 | ␉␉␉␉␉}␊ |
844 | ␊ |
845 | ␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
846 | ␉␉␉␉}␊ |
847 | ␉␉␉␉break;␊ |
848 | ␉␉␉}␊ |
849 | ␉␉}␊ |
850 | ␉␉// Mobile CPU␊ |
851 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
852 | ␉␉{␊ |
853 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
854 | ␉␉}␊ |
855 | ␉}␊ |
856 | ␊ |
857 | ␉else if (p->CPU.Vendor==CPUID_VENDOR_AMD)␊ |
858 | ␉{␊ |
859 | ␉␉switch(p->CPU.Family)␊ |
860 | ␉␉{␊ |
861 | ␉␉␉case 0xF: /* K8 */␊ |
862 | ␉␉␉{␊ |
863 | ␉␉␉␉uint64_t fidvid = 0;␊ |
864 | ␉␉␉␉uint64_t cpuMult;␊ |
865 | ␉␉␉␉uint64_t fid;␊ |
866 | ␊ |
867 | ␉␉␉␉fidvid = rdmsr64(K8_FIDVID_STATUS);␊ |
868 | ␉␉␉␉fid = bitfield(fidvid, 5, 0);␊ |
869 | ␊ |
870 | ␉␉␉␉cpuMult = (fid + 8) / 2;␊ |
871 | ␉␉␉␉currcoef = cpuMult;␊ |
872 | ␊ |
873 | ␉␉␉␉cpuMultN2 = (fidvid & (uint64_t)bit(0));␊ |
874 | ␉␉␉␉currdiv = cpuMultN2;␊ |
875 | ␉␉␉␉/****** Addon END ******/␊ |
876 | ␉␉␉}␊ |
877 | ␉␉␉␉break;␊ |
878 | ␊ |
879 | ␉␉␉case 0x10: /*** AMD Family 10h ***/␊ |
880 | ␉␉␉{␊ |
881 | ␉␉␉␉uint64_t cofvid = 0;␊ |
882 | ␉␉␉␉uint64_t cpuMult;␊ |
883 | ␉␉␉␉uint64_t divisor = 0;␊ |
884 | ␉␉␉␉uint64_t did;␊ |
885 | ␉␉␉␉uint64_t fid;␊ |
886 | ␊ |
887 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
888 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
889 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
890 | ␉␉␉␉if (did == 0) divisor = 2;␊ |
891 | ␉␉␉␉else if (did == 1) divisor = 4;␊ |
892 | ␉␉␉␉else if (did == 2) divisor = 8;␊ |
893 | ␉␉␉␉else if (did == 3) divisor = 16;␊ |
894 | ␉␉␉␉else if (did == 4) divisor = 32;␊ |
895 | ␊ |
896 | ␉␉␉␉cpuMult = (fid + 16) / divisor;␊ |
897 | ␉␉␉␉currcoef = cpuMult;␊ |
898 | ␊ |
899 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
900 | ␉␉␉␉currdiv = cpuMultN2;␊ |
901 | ␊ |
902 | ␉␉␉␉/****** Addon END ******/␊ |
903 | ␉␉␉}␊ |
904 | ␉␉␉break;␊ |
905 | ␊ |
906 | ␉␉␉case 0x11: /*** AMD Family 11h ***/␊ |
907 | ␉␉␉{␊ |
908 | ␉␉␉␉uint64_t cofvid = 0;␊ |
909 | ␉␉␉␉uint64_t cpuMult;␊ |
910 | ␉␉␉␉uint64_t divisor = 0;␊ |
911 | ␉␉␉␉uint64_t did;␊ |
912 | ␉␉␉␉uint64_t fid;␊ |
913 | ␊ |
914 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
915 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
916 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
917 | ␉␉␉␉if (did == 0) divisor = 2;␊ |
918 | ␉␉␉␉else if (did == 1) divisor = 4;␊ |
919 | ␉␉␉␉else if (did == 2) divisor = 8;␊ |
920 | ␉␉␉␉else if (did == 3) divisor = 16;␊ |
921 | ␉␉␉␉else if (did == 4) divisor = 32;␊ |
922 | ␊ |
923 | ␉␉␉␉cpuMult = (fid + 8) / divisor;␊ |
924 | ␉␉␉␉currcoef = cpuMult;␊ |
925 | ␊ |
926 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
927 | ␉␉␉␉currdiv = cpuMultN2;␊ |
928 | ␊ |
929 | ␉␉␉␉/****** Addon END ******/␊ |
930 | ␉␉␉}␊ |
931 | break;␊ |
932 | ␊ |
933 | ␉␉␉case 0x12: /*** AMD Family 12h ***/␊ |
934 | ␉␉␉{␊ |
935 | ␉␉␉␉// 8:4 CpuFid: current CPU core frequency ID␊ |
936 | ␉␉␉␉// 3:0 CpuDid: current CPU core divisor ID␊ |
937 | ␉␉␉␉uint64_t prfsts,CpuFid,CpuDid;␊ |
938 | ␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊ |
939 | ␊ |
940 | ␉␉␉␉CpuDid = bitfield(prfsts, 3, 0) ;␊ |
941 | ␉␉␉␉CpuFid = bitfield(prfsts, 8, 4) ;␊ |
942 | ␉␉␉␉uint64_t divisor;␊ |
943 | ␉␉␉␉switch (CpuDid)␊ |
944 | ␉␉␉␉{␊ |
945 | ␉␉␉␉␉case 0: divisor = 1; break;␊ |
946 | ␉␉␉␉␉case 1: divisor = (3/2); break;␊ |
947 | ␉␉␉␉␉case 2: divisor = 2; break;␊ |
948 | ␉␉␉␉␉case 3: divisor = 3; break;␊ |
949 | ␉␉␉␉␉case 4: divisor = 4; break;␊ |
950 | ␉␉␉␉␉case 5: divisor = 6; break;␊ |
951 | ␉␉␉␉␉case 6: divisor = 8; break;␊ |
952 | ␉␉␉␉␉case 7: divisor = 12; break;␊ |
953 | ␉␉␉␉␉case 8: divisor = 16; break;␊ |
954 | ␉␉␉␉␉default: divisor = 1; break;␊ |
955 | ␉␉␉␉}␊ |
956 | ␉␉␉␉currcoef = (CpuFid + 0x10) / divisor;␊ |
957 | ␊ |
958 | ␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊ |
959 | ␉␉␉␉currdiv = cpuMultN2;␊ |
960 | ␊ |
961 | ␉␉␉}␊ |
962 | ␉␉␉␉break;␊ |
963 | ␊ |
964 | ␉␉␉case 0x14: /* K14 */␊ |
965 | ␊ |
966 | ␉␉␉{␊ |
967 | ␉␉␉␉// 8:4: current CPU core divisor ID most significant digit␊ |
968 | ␉␉␉␉// 3:0: current CPU core divisor ID least significant digit␊ |
969 | ␉␉␉␉uint64_t prfsts;␊ |
970 | ␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊ |
971 | ␊ |
972 | ␉␉␉␉uint64_t CpuDidMSD,CpuDidLSD;␊ |
973 | ␉␉␉␉CpuDidMSD = bitfield(prfsts, 8, 4) ;␊ |
974 | ␉␉␉␉CpuDidLSD = bitfield(prfsts, 3, 0) ;␊ |
975 | ␊ |
976 | ␉␉␉␉uint64_t frequencyId = 0x10;␊ |
977 | ␉␉␉␉currcoef = (frequencyId + 0x10) /␊ |
978 | ␉␉␉␉␉(CpuDidMSD + (CpuDidLSD * 0.25) + 1);␊ |
979 | ␉␉␉␉currdiv = ((CpuDidMSD) + 1) << 2;␊ |
980 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
981 | ␊ |
982 | ␉␉␉␉cpuMultN2 = (prfsts & (uint64_t)bit(0));␊ |
983 | ␉␉␉␉currdiv = cpuMultN2;␊ |
984 | ␉␉␉}␊ |
985 | ␊ |
986 | ␉␉␉␉break;␊ |
987 | ␊ |
988 | ␉␉␉case 0x15: /*** AMD Family 15h ***/␊ |
989 | ␉␉␉case 0x06: /*** AMD Family 06h ***/␊ |
990 | ␉␉␉{␊ |
991 | ␊ |
992 | ␉␉␉␉uint64_t cofvid = 0;␊ |
993 | ␉␉␉␉uint64_t cpuMult;␊ |
994 | ␉␉␉␉uint64_t divisor = 0;␊ |
995 | ␉␉␉␉uint64_t did;␊ |
996 | ␉␉␉␉uint64_t fid;␊ |
997 | ␊ |
998 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
999 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
1000 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
1001 | ␉␉␉␉if (did == 0) divisor = 2;␊ |
1002 | ␉␉␉␉else if (did == 1) divisor = 4;␊ |
1003 | ␉␉␉␉else if (did == 2) divisor = 8;␊ |
1004 | ␉␉␉␉else if (did == 3) divisor = 16;␊ |
1005 | ␉␉␉␉else if (did == 4) divisor = 32;␊ |
1006 | ␊ |
1007 | ␉␉␉␉cpuMult = (fid + 16) / divisor;␊ |
1008 | ␉␉␉␉currcoef = cpuMult;␊ |
1009 | ␊ |
1010 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
1011 | ␉␉␉␉currdiv = cpuMultN2;␊ |
1012 | ␉␉␉}␊ |
1013 | ␉␉␉␉break;␊ |
1014 | ␊ |
1015 | ␉␉␉case 0x16: /*** AMD Family 16h kabini ***/␊ |
1016 | ␉␉␉{␊ |
1017 | ␉␉␉␉uint64_t cofvid = 0;␊ |
1018 | ␉␉␉␉uint64_t cpuMult;␊ |
1019 | ␉␉␉␉uint64_t divisor = 0;␊ |
1020 | ␉␉␉␉uint64_t did;␊ |
1021 | ␉␉␉␉uint64_t fid;␊ |
1022 | ␊ |
1023 | ␉␉␉␉cofvid = rdmsr64(K10_COFVID_STATUS);␊ |
1024 | ␉␉␉␉did = bitfield(cofvid, 8, 6);␊ |
1025 | ␉␉␉␉fid = bitfield(cofvid, 5, 0);␊ |
1026 | ␉␉␉␉if (did == 0) divisor = 1;␊ |
1027 | ␉␉␉␉else if (did == 1) divisor = 2;␊ |
1028 | ␉␉␉␉else if (did == 2) divisor = 4;␊ |
1029 | ␉␉␉␉else if (did == 3) divisor = 8;␊ |
1030 | ␉␉␉␉else if (did == 4) divisor = 16;␊ |
1031 | ␊ |
1032 | ␉␉␉␉cpuMult = (fid + 16) / divisor;␊ |
1033 | ␉␉␉␉currcoef = cpuMult;␊ |
1034 | ␊ |
1035 | ␉␉␉␉cpuMultN2 = (cofvid & (uint64_t)bit(0));␊ |
1036 | ␉␉␉␉currdiv = cpuMultN2;␊ |
1037 | ␉␉␉␉/****** Addon END ******/␊ |
1038 | ␉␉␉}␊ |
1039 | ␉␉␉␉break;␊ |
1040 | ␊ |
1041 | ␉␉␉default:␊ |
1042 | ␉␉␉{␊ |
1043 | ␉␉␉␉typedef unsigned long long vlong;␊ |
1044 | ␉␉␉␉uint64_t prfsts;␊ |
1045 | ␉␉␉␉prfsts = rdmsr64(K10_COFVID_STATUS);␊ |
1046 | ␉␉␉␉uint64_t r;␊ |
1047 | ␉␉␉␉vlong hz;␊ |
1048 | ␉␉␉␉r = (prfsts>>6) & 0x07;␊ |
1049 | ␉␉␉␉hz = (((prfsts & 0x3f)+0x10)*100000000ll)/(1<<r);␊ |
1050 | ␊ |
1051 | ␉␉␉␉currcoef = hz / (200 * Mega);␊ |
1052 | ␉␉␉}␊ |
1053 | ␉␉}␊ |
1054 | ␊ |
1055 | ␉␉if (currcoef)␊ |
1056 | ␉␉{␊ |
1057 | ␉␉␉if (currdiv)␊ |
1058 | ␉␉␉{␊ |
1059 | ␉␉␉␉busFrequency = ((tscFreq * 2) / ((currcoef * 2) + 1));␊ |
1060 | ␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊ |
1061 | ␉␉␉␉tscFCvtt2n = busFCvtt2n * 2 / (1 + (2 * currcoef));␊ |
1062 | ␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊ |
1063 | ␊ |
1064 | ␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
1065 | ␉␉␉}␊ |
1066 | ␉␉␉else␊ |
1067 | ␉␉␉{␊ |
1068 | ␉␉␉␉busFrequency = (tscFreq / currcoef);␊ |
1069 | ␉␉␉␉busFCvtt2n = ((1 * Giga) << 32) / busFrequency;␊ |
1070 | ␉␉␉␉tscFCvtt2n = busFCvtt2n / currcoef;␊ |
1071 | ␉␉␉␉cpuFrequency = ((1 * Giga) << 32) / tscFCvtt2n;␊ |
1072 | ␉␉␉␉DBG("%d\n", currcoef);␊ |
1073 | ␉␉␉}␊ |
1074 | ␉␉}␊ |
1075 | ␉␉else if (!cpuFrequency)␊ |
1076 | ␉␉{␊ |
1077 | ␉␉␉cpuFrequency = tscFreq;␊ |
1078 | ␉␉}␊ |
1079 | ␉}␊ |
1080 | ␊ |
1081 | #if 0␊ |
1082 | ␉if (!busFrequency)␊ |
1083 | ␉{␊ |
1084 | ␉␉busFrequency = (DEFAULT_FSB * 1000);␊ |
1085 | ␉␉DBG("\tCPU: busFrequency = 0! using the default value for FSB!\n");␊ |
1086 | ␉␉cpuFrequency = tscFreq;␊ |
1087 | ␉}␊ |
1088 | ␊ |
1089 | ␉DBG("\tcpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
1090 | ␊ |
1091 | #endif␊ |
1092 | ␊ |
1093 | ␉outb(0x21U, pic0_mask); // restore PIC0 interrupts␊ |
1094 | ␊ |
1095 | ␉p->CPU.MaxCoef = maxcoef = currcoef;␊ |
1096 | ␉p->CPU.MaxDiv = maxdiv = currdiv;␊ |
1097 | ␉p->CPU.CurrCoef = currcoef;␊ |
1098 | ␉p->CPU.CurrDiv = currdiv;␊ |
1099 | ␉p->CPU.TSCFrequency = tscFreq;␊ |
1100 | ␉p->CPU.FSBFrequency = busFrequency;␊ |
1101 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
1102 | ␊ |
1103 | ␉// keep formatted with spaces instead of tabs␊ |
1104 | ␊ |
1105 | ␉DBG("\tCPUID Raw Values:\n");␊ |
1106 | ␉for (i = 0; i < CPUID_MAX; i++)␊ |
1107 | ␉{␊ |
1108 | ␉␉DBG("\t%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊ |
1109 | ␉}␊ |
1110 | ␉DBG("\n");␊ |
1111 | ␉DBG("\tBrand String: %s\n",␉␉p->CPU.BrandString);␉␉// Processor name (BIOS)␊ |
1112 | ␉DBG("\tVendor: 0x%X\n",␉p->CPU.Vendor);␉␉␉// Vendor ex: GenuineIntel␊ |
1113 | ␉DBG("\tFamily: 0x%X\n",␉p->CPU.Family);␉␉␉// Family ex: 6 (06h)␊ |
1114 | ␉DBG("\tExtFamily: 0x%X\n",␉p->CPU.ExtFamily);␊ |
1115 | ␉DBG("\tSignature: 0x%08X\n",␉p->CPU.Signature);␉␉// CPUID signature␊ |
1116 | ␉/*switch (p->CPU.Type) {␊ |
1117 | ␉␉case PT_OEM:␊ |
1118 | ␉␉␉DBG("\tProcessor type: Intel Original OEM Processor\n");␊ |
1119 | ␉␉␉break;␊ |
1120 | ␉␉case PT_OD:␊ |
1121 | ␉␉␉DBG("\tProcessor type: Intel Over Drive Processor\n");␊ |
1122 | ␉␉␉break;␊ |
1123 | ␉␉case PT_DUAL:␊ |
1124 | ␉␉␉DBG("\tProcessor type: Intel Dual Processor\n");␊ |
1125 | ␉␉␉break;␊ |
1126 | ␉␉case PT_RES:␊ |
1127 | ␉␉␉DBG("\tProcessor type: Intel Reserved\n");␊ |
1128 | ␉␉␉break;␊ |
1129 | ␉␉default:␊ |
1130 | ␉␉␉break;␊ |
1131 | ␉}*/␊ |
1132 | ␉DBG("\tModel: 0x%X\n",␉p->CPU.Model);␉␉␉// Model ex: 37 (025h)␊ |
1133 | ␉DBG("\tExtModel: 0x%X\n",␉p->CPU.ExtModel);␊ |
1134 | ␉DBG("\tStepping: 0x%X\n",␉p->CPU.Stepping);␉␉// Stepping ex: 5 (05h)␊ |
1135 | ␉DBG("\tMaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊ |
1136 | ␉DBG("\tCurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊ |
1137 | ␉DBG("\tMaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊ |
1138 | ␉DBG("\tCurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊ |
1139 | ␉DBG("\tTSCFreq: %dMHz\n",␉p->CPU.TSCFrequency / 1000000);␊ |
1140 | ␉DBG("\tFSBFreq: %dMHz\n",␉p->CPU.FSBFrequency / 1000000);␊ |
1141 | ␉DBG("\tCPUFreq: %dMHz\n",␉p->CPU.CPUFrequency / 1000000);␊ |
1142 | ␉DBG("\tCores: %d\n",␉␉p->CPU.NoCores);␉␉// Cores␊ |
1143 | ␉DBG("\tLogical processor: %d\n",␉␉p->CPU.NoThreads);␉␉// Logical procesor␊ |
1144 | ␉DBG("\tFeatures: 0x%08x\n",␉p->CPU.Features);␊ |
1145 | ␊ |
1146 | ␉verbose("\n");␊ |
1147 | #if DEBUG_CPU␊ |
1148 | ␉pause();␊ |
1149 | #endif␊ |
1150 | }␊ |
1151 | |