1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | #include "bootstruct.h"␊ |
10 | ␊ |
11 | #ifndef DEBUG_SMBIOS␊ |
12 | #define DEBUG_SMBIOS 0␊ |
13 | #endif␊ |
14 | ␊ |
15 | #if DEBUG_SMBIOS␊ |
16 | #define DBG(x...)␉printf(x)␊ |
17 | #else␊ |
18 | #define DBG(x...)␉msglog(x)␊ |
19 | #endif␊ |
20 | ␊ |
21 | #define XEON "Xeon"␊ |
22 | #define CORE_I3 "Core(TM) i3"␊ |
23 | #define CORE_I5 "Core(TM) i5"␊ |
24 | #define CORE_I7 "Core(TM) i7"␊ |
25 | ␊ |
26 | bool getProcessorInformationExternalClock(returnType *value)␊ |
27 | {␊ |
28 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
29 | ␉{␊ |
30 | ␉␉switch (Platform.CPU.Family)␊ |
31 | ␉␉{␊ |
32 | ␉␉␉case 0x06:␊ |
33 | ␉␉␉␉switch (Platform.CPU.Model) {␊ |
34 | ␉␉␉␉␉// set external clock to 0 for SANDY␊ |
35 | ␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
36 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
37 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
38 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊ |
39 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
40 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
41 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
42 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
43 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
44 | ␉␉␉␉␉␉value->word = 0;␊ |
45 | ␉␉␉␉␉␉break;␊ |
46 | ␉␉␉␉␉default:␊ |
47 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
48 | break;␊ |
49 | ␉␉␉␉}␊ |
50 | ␉␉␉␉break;␊ |
51 | ␊ |
52 | ␉␉␉default:␊ |
53 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
54 | break;␊ |
55 | ␉␉}␊ |
56 | ␉}␊ |
57 | ␉else␊ |
58 | ␉{␊ |
59 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
60 | ␉}␊ |
61 | ␊ |
62 | ␉return true;␊ |
63 | }␊ |
64 | ␊ |
65 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
66 | {␊ |
67 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
68 | ␉return true;␊ |
69 | }␊ |
70 | ␊ |
71 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
72 | {␊ |
73 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
74 | ␉{␊ |
75 | ␉␉switch (Platform.CPU.Family)␊ |
76 | ␉␉{␊ |
77 | ␉␉␉case 0x06:␊ |
78 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
79 | ␉␉␉␉{␊ |
80 | /*␊ |
81 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
82 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊ |
83 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
84 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
85 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
86 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
87 | ␉␉␉␉␉␉return false;␊ |
88 | */␊ |
89 | ␉␉␉␉␉case 0x19:␊ |
90 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
91 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
92 | ␉␉␉␉␉case CPUID_MODEL_DALES:␊ |
93 | case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
94 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
95 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
96 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
97 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
98 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
99 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
100 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊ |
101 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
102 | {␊ |
103 | // thanks to dgobe for i3/i5/i7 bus speed detection␊ |
104 | int nhm_bus = 0x3F;␊ |
105 | static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
106 | unsigned long did, vid;␊ |
107 | unsigned int i;␊ |
108 | ␊ |
109 | // Nehalem supports Scrubbing␊ |
110 | // First, locate the PCI bus where the MCH is located␊ |
111 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊ |
112 | ␉␉␉␉␉␉{␊ |
113 | vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
114 | did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
115 | vid &= 0xFFFF;␊ |
116 | did &= 0xFF00;␊ |
117 | ␊ |
118 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
119 | ␉␉␉␉␉␉␉{␊ |
120 | nhm_bus = possible_nhm_bus[i];␊ |
121 | }␊ |
122 | }␊ |
123 | ␊ |
124 | unsigned long qpimult, qpibusspeed;␊ |
125 | qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
126 | qpimult &= 0x7F;␊ |
127 | verbose("qpimult %d\n", qpimult);␊ |
128 | qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
129 | // Rek: rounding decimals to match original mac profile info␊ |
130 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)␊ |
131 | ␉␉␉␉␉␉{␊ |
132 | qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
133 | }␊ |
134 | verbose("qpibusspeed %d\n", qpibusspeed);␊ |
135 | value->word = qpibusspeed;␊ |
136 | return true;␊ |
137 | }␊ |
138 | break;␊ |
139 | ␊ |
140 | ␉␉␉␉␉default:␊ |
141 | ␉␉␉␉␉␉break;␊ |
142 | ␉␉␉␉}␊ |
143 | break;␊ |
144 | ␊ |
145 | ␉␉␉default:␊ |
146 | ␉␉␉␉break;␊ |
147 | ␉␉}␊ |
148 | ␉}␊ |
149 | ␊ |
150 | ␉return false; //Unsupported CPU type␊ |
151 | }␊ |
152 | ␊ |
153 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
154 | {␊ |
155 | ␉if (Platform.CPU.NoCores >= 4)␊ |
156 | ␉{␊ |
157 | ␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊ |
158 | ␉}␊ |
159 | ␉else if (Platform.CPU.NoCores == 2)␊ |
160 | ␉{␊ |
161 | ␉␉return 0x301;␉// 513 - Core 2 Duo␊ |
162 | ␉}␊ |
163 | ␉␊ |
164 | ␉return 0x201;␉␉// 769 - Core Duo␊ |
165 | }␊ |
166 | ␊ |
167 | bool getSMBOemProcessorType(returnType *value)␊ |
168 | {␊ |
169 | ␉static bool done = false;␊ |
170 | ␊ |
171 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
172 | ␊ |
173 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
174 | ␉{␊ |
175 | ␉␉if (!done)␊ |
176 | ␉␉{␊ |
177 | ␉␉␉//DBG("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
178 | ␉␉␉done = true;␊ |
179 | ␉␉}␊ |
180 | ␉␉// Bungo: fixes Oem Processor Type - better matching IMHO, needs testing␊ |
181 | ␉␉switch (Platform.CPU.Family)␊ |
182 | ␉␉{␊ |
183 | ␉␉␉case 0x06:␊ |
184 | ␉␉␉case 0x0F:␊ |
185 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
186 | ␉␉␉␉{␊ |
187 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
188 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊ |
189 | case CPUID_MODEL_NOCONA:␊ |
190 | ␉␉␉␉␉case CPUID_MODEL_IRWINDALE:␊ |
191 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon"))␊ |
192 | ␉␉␉␉␉␉{␊ |
193 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
194 | ␉␉␉␉␉␉}␊ |
195 | ␉␉␉␉␉␉return true;␊ |
196 | ␊ |
197 | ␉␉␉␉␉case CPUID_MODEL_PRESLER:␊ |
198 | ␉␉␉␉␉case CPUID_MODEL_CELERON:␊ |
199 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
200 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
201 | ␉␉␉␉␉␉return true;␊ |
202 | ␊ |
203 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
204 | ␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
205 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
206 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
207 | ␉␉␉␉␉␉{␊ |
208 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
209 | return true;␊ |
210 | ␉␉␉␉␉␉}␊ |
211 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
212 | ␉␉␉␉␉␉{␊ |
213 | ␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo , Pentium Dual Core etc.␊ |
214 | ␉␉␉␉␉␉}␊ |
215 | ␉␉␉␉␉␉else␊ |
216 | ␉␉␉␉␉␉{␊ |
217 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊ |
218 | ␉␉␉␉␉␉}␊ |
219 | ␉␉␉␉␉␉return true;␊ |
220 | ␊ |
221 | ␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
222 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
223 | ␉␉␉␉␉␉return true;␊ |
224 | ␊ |
225 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊ |
226 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
227 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
228 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
229 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
230 | ␉␉␉␉␉␉{␊ |
231 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
232 | ␉␉␉␉␉␉␉return true;␊ |
233 | ␉␉␉␉␉␉}␊ |
234 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
235 | ␉␉␉␉␉␉{␊ |
236 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
237 | ␉␉␉␉␉␉␉return true;␊ |
238 | ␉␉␉␉␉␉}␊ |
239 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
240 | ␉␉␉␉␉␉{␊ |
241 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
242 | ␉␉␉␉␉␉␉return true;␊ |
243 | ␉␉␉␉␉␉}␊ |
244 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
245 | ␉␉␉␉␉␉{␊ |
246 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
247 | ␉␉␉␉␉␉␉return true;␊ |
248 | ␉␉␉␉␉␉}␊ |
249 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
250 | ␉␉␉␉␉␉{␊ |
251 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Pentium Dual Core as Core i3␊ |
252 | ␉␉␉␉␉␉}␊ |
253 | ␉␉␉␉␉␉return true;␊ |
254 | ␊ |
255 | ␉␉␉␉␉case CPUID_MODEL_DALES_32NM:␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
256 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
257 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
258 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
259 | ␉␉␉␉␉␉{␊ |
260 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
261 | ␉␉␉␉␉␉␉return true;␊ |
262 | ␉␉␉␉␉␉}␊ |
263 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
264 | ␉␉␉␉␉␉{␊ |
265 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
266 | ␉␉␉␉␉␉␉return true;␊ |
267 | ␉␉␉␉␉␉}␊ |
268 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
269 | ␉␉␉␉␉␉{␊ |
270 | ␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊ |
271 | ␉␉␉␉␉␉␉return true;␊ |
272 | ␉␉␉␉␉␉}␊ |
273 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
274 | ␉␉␉␉␉␉{␊ |
275 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
276 | ␉␉␉␉␉␉␉return true;␊ |
277 | ␉␉␉␉␉␉}␊ |
278 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
279 | ␉␉␉␉␉␉{␊ |
280 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Pentium Dual Core as Core i3␊ |
281 | ␉␉␉␉␉␉}␊ |
282 | ␉␉␉␉␉␉return true;␊ |
283 | ␊ |
284 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
285 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
286 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
287 | ␉␉␉␉␉␉{␊ |
288 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
289 | ␉␉␉␉␉␉␉return true;␊ |
290 | ␉␉␉␉␉␉}␊ |
291 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
292 | ␉␉␉␉␉␉{␊ |
293 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
294 | ␉␉␉␉␉␉␉return true;␊ |
295 | ␉␉␉␉␉␉}␊ |
296 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
297 | ␉␉␉␉␉␉{␊ |
298 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
299 | ␉␉␉␉␉␉␉return true;␊ |
300 | ␉␉␉␉␉␉}␊ |
301 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
302 | ␉␉␉␉␉␉{␊ |
303 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
304 | ␉␉␉␉␉␉␉return true;␊ |
305 | ␉␉␉␉␉␉}␊ |
306 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
307 | ␉␉␉␉␉␉{␊ |
308 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Pentium Dual Core as Core i3␊ |
309 | ␉␉␉␉␉␉}␊ |
310 | ␉␉␉␉␉␉return true;␊ |
311 | ␊ |
312 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
313 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
314 | ␉␉␉␉␉␉{␊ |
315 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
316 | ␉␉␉␉␉␉␉return true;␊ |
317 | ␉␉␉␉␉␉}␊ |
318 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
319 | ␉␉␉␉␉␉{␊ |
320 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊ |
321 | ␉␉␉␉␉␉␉return true;␊ |
322 | ␉␉␉␉␉␉}␊ |
323 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
324 | ␉␉␉␉␉␉{␊ |
325 | ␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊ |
326 | ␉␉␉␉␉␉␉return true;␊ |
327 | ␉␉␉␉␉␉}␊ |
328 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
329 | ␉␉␉␉␉␉{␊ |
330 | ␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊ |
331 | ␉␉␉␉␉␉␉return true;␊ |
332 | ␉␉␉␉␉␉}␊ |
333 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
334 | ␉␉␉␉␉␉{␊ |
335 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Pentium Dual Core as Core i3␊ |
336 | ␉␉␉␉␉␉}␊ |
337 | ␉␉␉␉␉␉return true;␊ |
338 | ␊ |
339 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␉␉// 0x3E - Mac Pro 6,1␊ |
340 | ␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊ |
341 | ␉␉␉␉␉␉return true;␊ |
342 | ␊ |
343 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C -␊ |
344 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊ |
345 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊ |
346 | ␉␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␉␉␉// 0x46␊ |
347 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
348 | ␉␉␉␉␉␉{␊ |
349 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
350 | ␉␉␉␉␉␉␉return true;␊ |
351 | ␉␉␉␉␉␉}␊ |
352 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
353 | ␉␉␉␉␉␉{␊ |
354 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
355 | ␉␉␉␉␉␉␉return true;␊ |
356 | ␉␉␉␉␉␉}␊ |
357 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
358 | ␉␉␉␉␉␉{␊ |
359 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
360 | ␉␉␉␉␉␉␉return true;␊ |
361 | ␉␉␉␉␉␉}␊ |
362 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
363 | ␉␉␉␉␉␉{␊ |
364 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
365 | ␉␉␉␉␉␉␉return true;␊ |
366 | ␉␉␉␉␉␉}␊ |
367 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
368 | ␉␉␉␉␉␉{␊ |
369 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Pentium Dual Core as Core i3␊ |
370 | ␉␉␉␉␉␉}␊ |
371 | ␉␉␉␉␉␉return true;␊ |
372 | ␊ |
373 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
374 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
375 | ␉␉␉␉␉␉return true;␊ |
376 | ␊ |
377 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
378 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
379 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
380 | ␉␉␉␉␉␉return true;␊ |
381 | ␉␉␉␉␉default:␊ |
382 | ␉␉␉␉␉␉break; // Unsupported CPU type␊ |
383 | ␉␉␉␉}␊ |
384 | break;␊ |
385 | ␊ |
386 | default:␊ |
387 | ␉␉␉␉break;␊ |
388 | ␉␉}␊ |
389 | ␉}␊ |
390 | ␉␊ |
391 | ␉return false;␊ |
392 | }␊ |
393 | ␊ |
394 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
395 | {␊ |
396 | ␉static int idx = -1;␊ |
397 | ␉int␉map;␊ |
398 | ␊ |
399 | ␉if (!bootInfo->memDetect)␊ |
400 | ␉{␊ |
401 | ␉␉return false;␊ |
402 | ␉}␊ |
403 | ␊ |
404 | ␉idx++;␊ |
405 | ␉if (idx < MAX_RAM_SLOTS)␊ |
406 | ␉{␊ |
407 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
408 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
409 | ␉␉{␊ |
410 | ␉␉␉verbose("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
411 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
412 | ␉␉␉return true;␊ |
413 | ␉␉}␊ |
414 | ␉}␊ |
415 | ␊ |
416 | ␉value->byte = 2; // means Unknown␊ |
417 | ␉return true;␊ |
418 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
419 | //␉return true;␊ |
420 | }␊ |
421 | ␊ |
422 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
423 | {␊ |
424 | ␉value->word = 0xFFFF;␊ |
425 | ␉return true;␊ |
426 | }␊ |
427 | ␊ |
428 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
429 | {␊ |
430 | ␉static int idx = -1;␊ |
431 | ␉int␉map;␊ |
432 | ␊ |
433 | ␉if (!bootInfo->memDetect)␊ |
434 | ␉{␊ |
435 | ␉␉return false;␊ |
436 | ␉}␊ |
437 | ␊ |
438 | ␉idx++;␊ |
439 | ␉if (idx < MAX_RAM_SLOTS)␊ |
440 | ␉{␊ |
441 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
442 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
443 | ␉␉{␊ |
444 | ␉␉␉verbose("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
445 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
446 | ␉␉␉return true;␊ |
447 | ␉␉}␊ |
448 | ␉}␊ |
449 | ␊ |
450 | ␉value->dword = 0; // means Unknown␊ |
451 | ␉return true;␊ |
452 | //␉value->dword = 800;␊ |
453 | //␉return true;␊ |
454 | }␊ |
455 | ␊ |
456 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
457 | {␊ |
458 | ␉static int idx = -1;␊ |
459 | ␉int␉map;␊ |
460 | ␊ |
461 | ␉if (!bootInfo->memDetect)␊ |
462 | ␉{␊ |
463 | ␉␉return false;␊ |
464 | ␉}␊ |
465 | ␊ |
466 | ␉idx++;␊ |
467 | ␉if (idx < MAX_RAM_SLOTS)␊ |
468 | ␉{␊ |
469 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
470 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
471 | ␉␉{␊ |
472 | ␉␉␉verbose("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
473 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
474 | ␉␉␉return true;␊ |
475 | ␉␉}␊ |
476 | ␉}␊ |
477 | ␊ |
478 | ␉value->string = NOT_AVAILABLE;␊ |
479 | ␉return true;␊ |
480 | }␊ |
481 | ␊ |
482 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
483 | {␊ |
484 | ␉static int idx = -1;␊ |
485 | ␉int␉map;␊ |
486 | ␊ |
487 | ␉if (!bootInfo->memDetect)␊ |
488 | ␉{␊ |
489 | ␉␉return false;␊ |
490 | ␉}␊ |
491 | ␊ |
492 | ␉idx++;␊ |
493 | ␊ |
494 | ␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n",idx,MAX_RAM_SLOTS);␊ |
495 | ␊ |
496 | ␉if (idx < MAX_RAM_SLOTS)␊ |
497 | ␉{␊ |
498 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
499 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
500 | ␉␉{␊ |
501 | ␉␉␉verbose("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
502 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
503 | ␉␉␉return true;␊ |
504 | ␉␉}␊ |
505 | ␉}␊ |
506 | ␊ |
507 | ␉value->string = NOT_AVAILABLE;␊ |
508 | ␉return true;␊ |
509 | }␊ |
510 | ␊ |
511 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
512 | {␊ |
513 | ␉static int idx = -1;␊ |
514 | ␉int␉map;␊ |
515 | ␊ |
516 | ␉if (!bootInfo->memDetect)␊ |
517 | ␉{␊ |
518 | ␉␉return false;␊ |
519 | ␉}␊ |
520 | ␊ |
521 | ␉idx++;␊ |
522 | ␉if (idx < MAX_RAM_SLOTS)␊ |
523 | ␉{␊ |
524 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
525 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
526 | ␉␉{␊ |
527 | ␉␉␉verbose("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
528 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
529 | ␉␉␉return true;␊ |
530 | ␉␉}␊ |
531 | ␉}␊ |
532 | ␊ |
533 | ␉value->string = NOT_AVAILABLE;␊ |
534 | ␉return true;␊ |
535 | }␊ |
536 | ␊ |
537 | ␊ |
538 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
539 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
540 | static const char * const SMTAG = "_SM_";␊ |
541 | static const char* const DMITAG = "_DMI_";␊ |
542 | ␊ |
543 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
544 | {␊ |
545 | ␉SMBEntryPoint␉*smbios;␊ |
546 | ␉/*␊ |
547 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
548 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
549 | ␉ */␊ |
550 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
551 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊ |
552 | ␉{␊ |
553 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
554 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
555 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
556 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
557 | ␉␉{␊ |
558 | ␉␉␉return smbios;␊ |
559 | ␉ }␊ |
560 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
561 | ␉}␊ |
562 | ␉error("ERROR: Unable to find SMBIOS!\n");␊ |
563 | ␉pause("");␊ |
564 | ␉return NULL;␊ |
565 | }␊ |
566 | ␊ |
567 | |