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Source at commit 304 created 13 years 11 months ago. By zef, Fixed cache size configuration in msdos.c. | |
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1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #include "libsaio.h"␊ |
8 | #include "bootstruct.h"␊ |
9 | #include "pci.h"␊ |
10 | #include "pci_root.h"␊ |
11 | ␊ |
12 | #ifndef DEBUG_PCI␊ |
13 | #define DEBUG_PCI 0␊ |
14 | #endif␊ |
15 | ␊ |
16 | #if DEBUG_PCI␊ |
17 | #define DBG(x...)␉␉printf(x)␊ |
18 | #else␊ |
19 | #define DBG(x...)␊ |
20 | #endif␊ |
21 | ␊ |
22 | pci_dt_t␉*root_pci_dev;␊ |
23 | ␊ |
24 | ␊ |
25 | uint8_t pci_config_read8(uint32_t pci_addr, uint8_t reg)␊ |
26 | {␊ |
27 | ␉pci_addr |= reg & ~3;␊ |
28 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
29 | ␉return inb(PCI_DATA_REG + (reg & 3));␊ |
30 | }␊ |
31 | ␊ |
32 | uint16_t pci_config_read16(uint32_t pci_addr, uint8_t reg)␊ |
33 | {␊ |
34 | ␉pci_addr |= reg & ~3;␊ |
35 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
36 | ␉return inw(PCI_DATA_REG + (reg & 2));␊ |
37 | }␊ |
38 | ␊ |
39 | uint32_t pci_config_read32(uint32_t pci_addr, uint8_t reg)␊ |
40 | {␊ |
41 | ␉pci_addr |= reg & ~3;␊ |
42 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
43 | ␉return inl(PCI_DATA_REG);␊ |
44 | }␊ |
45 | ␊ |
46 | void pci_config_write8(uint32_t pci_addr, uint8_t reg, uint8_t data)␊ |
47 | {␊ |
48 | ␉pci_addr |= reg & ~3;␊ |
49 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
50 | ␉outb(PCI_DATA_REG + (reg & 3), data);␊ |
51 | }␊ |
52 | ␊ |
53 | void pci_config_write16(uint32_t pci_addr, uint8_t reg, uint16_t data)␊ |
54 | {␊ |
55 | ␉pci_addr |= reg & ~3;␊ |
56 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
57 | ␉outw(PCI_DATA_REG + (reg & 2), data);␊ |
58 | }␊ |
59 | ␊ |
60 | void pci_config_write32(uint32_t pci_addr, uint8_t reg, uint32_t data)␊ |
61 | {␊ |
62 | ␉pci_addr |= reg & ~3;␊ |
63 | ␉outl(PCI_ADDR_REG, pci_addr);␊ |
64 | ␉outl(PCI_DATA_REG, data);␊ |
65 | }␊ |
66 | ␊ |
67 | void scan_pci_bus(pci_dt_t *start, uint8_t bus)␊ |
68 | {␊ |
69 | ␉pci_dt_t␉*new;␊ |
70 | ␉pci_dt_t␉**current = &start->children;␊ |
71 | ␉uint32_t␉id;␊ |
72 | ␉uint32_t␉pci_addr;␊ |
73 | ␉uint8_t␉␉dev;␊ |
74 | ␉uint8_t␉␉func;␊ |
75 | ␉uint8_t␉␉secondary_bus;␊ |
76 | ␉uint8_t␉␉header_type;␊ |
77 | ␊ |
78 | ␉for (dev = 0; dev < 32; dev++) {␊ |
79 | ␉␉for (func = 0; func < 8; func++) {␊ |
80 | ␉␉␉pci_addr = PCIADDR(bus, dev, func);␊ |
81 | ␉␉␉id = pci_config_read32(pci_addr, PCI_VENDOR_ID);␊ |
82 | ␉␉␉if (!id || id == 0xffffffff) {␊ |
83 | ␉␉␉␉continue;␊ |
84 | ␉␉␉}␊ |
85 | ␉␉␉new = (pci_dt_t*)malloc(sizeof(pci_dt_t));␊ |
86 | ␉␉␉bzero(new, sizeof(pci_dt_t));␊ |
87 | ␉␉␉new->dev.addr␉= pci_addr;␊ |
88 | ␉␉␉new->vendor_id␉= id & 0xffff;␊ |
89 | ␉␉␉new->device_id␉= (id >> 16) & 0xffff;␊ |
90 | ␉␉␉new->class_id␉= pci_config_read16(pci_addr, PCI_CLASS_DEVICE);␊ |
91 | ␉␉␉new->parent␉= start;␊ |
92 | ␊ |
93 | ␉␉␉header_type = pci_config_read8(pci_addr, PCI_HEADER_TYPE);␊ |
94 | ␉␉␉switch (header_type & 0x7f) {␊ |
95 | ␉␉␉case PCI_HEADER_TYPE_BRIDGE:␊ |
96 | ␉␉␉case PCI_HEADER_TYPE_CARDBUS:␊ |
97 | ␉␉␉␉secondary_bus = pci_config_read8(pci_addr, PCI_SECONDARY_BUS);␊ |
98 | ␉␉␉␉if (secondary_bus != 0) {␊ |
99 | ␉␉␉␉␉scan_pci_bus(new, secondary_bus);␊ |
100 | ␉␉␉␉}␊ |
101 | ␉␉␉␉break;␊ |
102 | ␉␉␉}␊ |
103 | ␉␉␉*current = new;␊ |
104 | ␉␉␉current = &new->next;␊ |
105 | ␊ |
106 | ␉␉␉if ((func == 0) && ((header_type & 0x80) == 0)) {␊ |
107 | ␉␉␉␉break;␊ |
108 | ␉␉␉}␊ |
109 | ␉␉}␊ |
110 | ␉}␊ |
111 | }␊ |
112 | ␊ |
113 | void enable_pci_devs(void)␊ |
114 | {␊ |
115 | ␉uint16_t id;␊ |
116 | ␉uint32_t rcba, *fd;␊ |
117 | ␊ |
118 | ␉id = pci_config_read16(PCIADDR(0, 0x00, 0), 0x00);␊ |
119 | ␉/* make sure we're on Intel chipset */␊ |
120 | ␉if (id != 0x8086)␊ |
121 | ␉␉return;␊ |
122 | ␉rcba = pci_config_read32(PCIADDR(0, 0x1f, 0), 0xf0) & ~1;␊ |
123 | ␉fd = (uint32_t *)(rcba + 0x3418);␊ |
124 | ␉/* set SMBus Disable (SD) to 0 */␊ |
125 | ␉*fd &= ~0x8;␊ |
126 | ␉/* and all devices? */␊ |
127 | ␉//*fd = 0x1;␊ |
128 | }␊ |
129 | ␊ |
130 | ␊ |
131 | void build_pci_dt(void)␊ |
132 | {␊ |
133 | ␉root_pci_dev = malloc(sizeof(pci_dt_t));␊ |
134 | ␉bzero(root_pci_dev, sizeof(pci_dt_t));␊ |
135 | ␉enable_pci_devs();␊ |
136 | ␉scan_pci_bus(root_pci_dev, 0);␊ |
137 | #if DEBUG_PCI␊ |
138 | ␉dump_pci_dt(root_pci_dev->children);␊ |
139 | ␉pause();␊ |
140 | #endif␊ |
141 | }␊ |
142 | ␊ |
143 | static char dev_path[256];␊ |
144 | char *get_pci_dev_path(pci_dt_t *pci_dt)␊ |
145 | {␊ |
146 | ␉pci_dt_t␉*current;␊ |
147 | ␉pci_dt_t␉*end;␊ |
148 | ␉char␉␉tmp[64];␊ |
149 | ␊ |
150 | ␉dev_path[0] = 0;␊ |
151 | ␉end = root_pci_dev;␊ |
152 | ␉␊ |
153 | ␉int uid = getPciRootUID();␊ |
154 | ␉while (end != pci_dt)␊ |
155 | ␉{␊ |
156 | ␉␉current = pci_dt;␊ |
157 | ␉␉while (current->parent != end)␊ |
158 | ␉␉␉current = current->parent;␉␉␉␊ |
159 | ␉␉end = current;␊ |
160 | ␉␉if (current->parent == root_pci_dev)␊ |
161 | ␉␉{␊ |
162 | ␉␉␉sprintf(tmp, "PciRoot(0x%x)/Pci(0x%x,0x%x)", uid, ␊ |
163 | ␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
164 | ␉␉} else {␊ |
165 | ␉␉␉sprintf(tmp, "/Pci(0x%x,0x%x)", ␊ |
166 | ␉␉␉␉current->dev.bits.dev, current->dev.bits.func);␊ |
167 | ␉␉}␊ |
168 | ␉␉strcat(dev_path, tmp);␊ |
169 | ␉}␊ |
170 | ␉return dev_path;␊ |
171 | }␊ |
172 | ␊ |
173 | void dump_pci_dt(pci_dt_t *pci_dt)␊ |
174 | {␊ |
175 | ␉pci_dt_t␉*current;␊ |
176 | ␊ |
177 | ␉current = pci_dt;␊ |
178 | ␉while (current) {␊ |
179 | ␉␉printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊ |
180 | ␉␉␉current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊ |
181 | ␉␉␉current->class_id, current->vendor_id, current->device_id, ␊ |
182 | ␉␉␉get_pci_dev_path(current));␊ |
183 | ␉␉dump_pci_dt(current->children);␊ |
184 | ␉␉current = current->next;␊ |
185 | ␉}␊ |
186 | }␊ |
187 |