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Source at commit 304 created 13 years 11 months ago. By zef, Fixed cache size configuration in msdos.c. | |
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1 | /*␊ |
2 | *␊ |
3 | * Copyright 2008 by Islam M. Ahmed Zaid. All rights reserved.␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PCI_H␊ |
8 | #define __LIBSAIO_PCI_H␊ |
9 | ␊ |
10 | typedef struct {␊ |
11 | ␉uint32_t␉␉:2;␊ |
12 | ␉uint32_t␉reg␉:6;␊ |
13 | ␉uint32_t␉func:3;␊ |
14 | ␉uint32_t␉dev␉:5;␊ |
15 | ␉uint32_t␉bus␉:8;␊ |
16 | ␉uint32_t␉␉:7;␊ |
17 | ␉uint32_t␉eb␉:1;␊ |
18 | } pci_addr_t;␊ |
19 | ␊ |
20 | typedef union {␊ |
21 | ␉pci_addr_t␉bits;␊ |
22 | ␉uint32_t␉addr;␊ |
23 | } pci_dev_t;␊ |
24 | ␊ |
25 | typedef struct pci_dt_t {␊ |
26 | ␉pci_dev_t␉␉dev;␊ |
27 | ␊ |
28 | ␉uint16_t␉vendor_id;␊ |
29 | ␉uint16_t␉device_id;␊ |
30 | ␉uint16_t␉class_id;␉␊ |
31 | ␊ |
32 | ␉struct pci_dt_t␉*parent;␊ |
33 | ␉struct pci_dt_t␉*children;␊ |
34 | ␉struct pci_dt_t␉*next;␊ |
35 | } pci_dt_t;␊ |
36 | ␊ |
37 | #define PCIADDR(bus, dev, func)␉(1 << 31) | (bus << 16) | (dev << 11) | (func << 8)␊ |
38 | #define PCI_ADDR_REG␉␉0xcf8␊ |
39 | #define PCI_DATA_REG␉␉0xcfc␊ |
40 | ␊ |
41 | extern pci_dt_t␉␉*root_pci_dev;␊ |
42 | extern uint8_t␉␉pci_config_read8(uint32_t, uint8_t);␊ |
43 | extern uint16_t␉␉pci_config_read16(uint32_t, uint8_t);␊ |
44 | extern uint32_t␉␉pci_config_read32(uint32_t, uint8_t);␊ |
45 | extern void␉␉pci_config_write8(uint32_t, uint8_t, uint8_t);␊ |
46 | extern void␉␉pci_config_write16(uint32_t, uint8_t, uint16_t);␊ |
47 | extern void␉␉pci_config_write32(uint32_t, uint8_t, uint32_t);␊ |
48 | extern char␉␉*get_pci_dev_path(pci_dt_t *);␊ |
49 | extern void␉␉build_pci_dt(void);␊ |
50 | extern void␉␉dump_pci_dt(pci_dt_t *);␊ |
51 | ␊ |
52 | //-----------------------------------------------------------------------------␊ |
53 | // added by iNDi␊ |
54 | ␊ |
55 | struct pci_rom_pci_header_t {␊ |
56 | ␉uint32_t␉signature;␉␉␉// 0x50434952 'PCIR'␊ |
57 | ␉uint16_t␉vendor;␊ |
58 | ␉uint16_t␉device;␊ |
59 | ␉uint16_t␉product;␊ |
60 | ␉uint16_t␉length;␊ |
61 | ␉uint8_t␉␉revision;␉␉␉// 0 = PCI 2.1␊ |
62 | ␉uint8_t␉␉class[3];␊ |
63 | ␉uint16_t␉rom_size;␉␉␉␊ |
64 | ␉uint16_t␉code_revision;␊ |
65 | ␉uint8_t␉␉code_type;␉␉␉// 0 = x86␊ |
66 | ␉uint8_t␉␉last_image;␉␉␉// 0x80␊ |
67 | ␉uint16_t␉reserverd;␊ |
68 | };␊ |
69 | ␊ |
70 | struct pci_rom_pnp_header_t {␊ |
71 | ␉uint32_t␉signature;␉␉␉// 0x24506E50 '$PnP'␊ |
72 | ␉uint8_t␉␉revision;␉␉␉// 1␊ |
73 | ␉uint8_t␉␉length;␉␉␉␉//␊ |
74 | ␉uint16_t␉offset;␉␉␉␉␊ |
75 | ␉uint8_t␉␉checksum;␊ |
76 | ␉uint32_t␉identifier;␊ |
77 | ␉uint16_t␉manufacturer;␊ |
78 | ␉uint16_t␉product;␊ |
79 | ␉uint8_t␉␉class[3];␊ |
80 | ␉uint8_t␉␉indicators;␊ |
81 | ␉uint16_t␉boot_vector;␊ |
82 | ␉uint16_t␉disconnect_vector;␊ |
83 | ␉uint16_t␉bootstrap_vector;␊ |
84 | ␉uint16_t␉reserved;␊ |
85 | ␉uint16_t␉resource_vector;␊ |
86 | };␊ |
87 | ␊ |
88 | struct pci_rom_bios_t {␊ |
89 | ␉uint16_t␉signature;␉␉␉// 0x55AA␊ |
90 | ␉uint8_t␉␉size;␉␉␉␉// Multiples of 512␊ |
91 | ␉␊ |
92 | ␉uint8_t␉␉checksum;␉␉␉// 0x00␊ |
93 | ␉uint16_t␉pci_header;␊ |
94 | ␉uint16_t␉pnp_header;␊ |
95 | };␊ |
96 | ␊ |
97 | /*␊ |
98 | * Under PCI, each device has 256 bytes of configuration address space,␊ |
99 | * of which the first 64 bytes are standardized as follows:␊ |
100 | */␊ |
101 | ␊ |
102 | #define PCI_VENDOR_ID␉␉␉␉0x00␉/* 16 bits */␊ |
103 | #define PCI_DEVICE_ID␉␉␉␉0x02␉/* 16 bits */␊ |
104 | #define PCI_COMMAND␉␉␉␉␉0x04␉/* 16 bits */␊ |
105 | #define PCI_COMMAND_IO␉␉␉␉0x1␉␉/* Enable response in I/O space */␊ |
106 | #define PCI_COMMAND_MEMORY␉␉␉0x2␉␉/* Enable response in Memory space */␊ |
107 | #define PCI_COMMAND_MASTER␉␉␉0x4␉␉/* Enable bus mastering */␊ |
108 | #define PCI_COMMAND_SPECIAL␉␉␉0x8␉␉/* Enable response to special cycles */␊ |
109 | #define PCI_COMMAND_INVALIDATE␉␉0x10␉/* Use memory write and invalidate */␊ |
110 | #define PCI_COMMAND_VGA_PALETTE␉␉0x20␉/* Enable palette snooping */␊ |
111 | #define PCI_COMMAND_PARITY␉␉␉0x40␉/* Enable parity checking */␊ |
112 | #define PCI_COMMAND_WAIT␉␉␉0x80␉/* Enable address/data stepping */␊ |
113 | #define PCI_COMMAND_SERR␉␉␉0x100␉/* Enable SERR */␊ |
114 | #define PCI_COMMAND_FAST_BACK␉␉0x200␉/* Enable back-to-back writes */␊ |
115 | #define PCI_COMMAND_DISABLE_INTx␉0x400␉/* PCIE: Disable INTx interrupts */␊ |
116 | ␊ |
117 | #define PCI_STATUS␉␉␉␉␉0x06␉/* 16 bits */␊ |
118 | #define PCI_STATUS_INTx␉␉␉␉0x08␉/* PCIE: INTx interrupt pending */␊ |
119 | #define PCI_STATUS_CAP_LIST␉␉␉0x10␉/* Support Capability List */␊ |
120 | #define PCI_STATUS_66MHZ␉␉␉0x20␉/* Support 66 Mhz PCI 2.1 bus */␊ |
121 | #define PCI_STATUS_UDF␉␉␉␉0x40␉/* Support User Definable Features [obsolete] */␊ |
122 | #define PCI_STATUS_FAST_BACK␉␉0x80␉/* Accept fast-back to back */␊ |
123 | #define PCI_STATUS_PARITY␉␉␉0x100␉/* Detected parity error */␊ |
124 | #define PCI_STATUS_DEVSEL_MASK␉␉0x600␉/* DEVSEL timing */␊ |
125 | #define PCI_STATUS_DEVSEL_FAST␉␉0x000␊ |
126 | #define PCI_STATUS_DEVSEL_MEDIUM␉0x200␊ |
127 | #define PCI_STATUS_DEVSEL_SLOW␉␉0x400␊ |
128 | #define PCI_STATUS_SIG_TARGET_ABORT 0x800␉/* Set on target abort */␊ |
129 | #define PCI_STATUS_REC_TARGET_ABORT 0x1000␉/* Master ack of " */␊ |
130 | #define PCI_STATUS_REC_MASTER_ABORT 0x2000␉/* Set on master abort */␊ |
131 | #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000␉/* Set when we drive SERR */␊ |
132 | #define PCI_STATUS_DETECTED_PARITY␉0x8000␉/* Set on parity error */␊ |
133 | ␊ |
134 | #define PCI_CLASS_REVISION␉␉␉0x08␉/* High 24 bits are class, low 8 revision */␊ |
135 | #define PCI_REVISION_ID␉␉␉␉0x08 /* Revision ID */␊ |
136 | #define PCI_CLASS_PROG␉␉␉␉0x09 /* Reg. Level Programming Interface */␊ |
137 | #define PCI_CLASS_DEVICE␉␉␉0x0a /* Device class */␊ |
138 | ␊ |
139 | #define PCI_CACHE_LINE_SIZE␉␉␉0x0c␉/* 8 bits */␊ |
140 | #define PCI_LATENCY_TIMER␉␉␉0x0d␉/* 8 bits */␊ |
141 | #define PCI_HEADER_TYPE␉␉␉␉0x0e␉/* 8 bits */␊ |
142 | #define PCI_HEADER_TYPE_NORMAL␉␉0␊ |
143 | #define PCI_HEADER_TYPE_BRIDGE␉␉1␊ |
144 | #define PCI_HEADER_TYPE_CARDBUS␉␉2␉␊ |
145 | ␊ |
146 | #define PCI_BIST␉␉␉␉␉0x0f␉/* 8 bits */␊ |
147 | #define PCI_BIST_CODE_MASK␉␉␉0x0f␉/* Return result */␊ |
148 | #define PCI_BIST_START␉␉␉␉0x40␉/* 1 to start BIST, 2 secs or less */␊ |
149 | #define PCI_BIST_CAPABLE␉␉␉0x80␉/* 1 if BIST capable */␊ |
150 | ␊ |
151 | /*␊ |
152 | * Base addresses specify locations in memory or I/O space.␊ |
153 | * Decoded size can be determined by writing a value of␊ |
154 | * 0xffffffff to the register, and reading it back. Only␊ |
155 | * 1 bits are decoded.␊ |
156 | */␊ |
157 | #define PCI_BASE_ADDRESS_0␉␉␉␉0x10␉/* 32 bits */␊ |
158 | #define PCI_BASE_ADDRESS_1␉␉␉␉0x14␉/* 32 bits [htype 0,1 only] */␊ |
159 | #define PCI_BASE_ADDRESS_2␉␉␉␉0x18␉/* 32 bits [htype 0 only] */␊ |
160 | #define PCI_BASE_ADDRESS_3␉␉␉␉0x1c␉/* 32 bits */␊ |
161 | #define PCI_BASE_ADDRESS_4␉␉␉␉0x20␉/* 32 bits */␊ |
162 | #define PCI_BASE_ADDRESS_5␉␉␉␉0x24␉/* 32 bits */␊ |
163 | #define PCI_BASE_ADDRESS_SPACE␉␉␉0x01␉/* 0 = memory, 1 = I/O */␊ |
164 | #define PCI_BASE_ADDRESS_SPACE_IO␉␉0x01␊ |
165 | #define PCI_BASE_ADDRESS_SPACE_MEMORY␉0x00␊ |
166 | #define PCI_BASE_ADDRESS_MEM_TYPE_MASK␉0x06␊ |
167 | #define PCI_BASE_ADDRESS_MEM_TYPE_32␉0x00␉/* 32 bit address */␊ |
168 | #define PCI_BASE_ADDRESS_MEM_TYPE_1M␉0x02␉/* Below 1M [obsolete] */␊ |
169 | #define PCI_BASE_ADDRESS_MEM_TYPE_64␉0x04␉/* 64 bit address */␊ |
170 | #define PCI_BASE_ADDRESS_MEM_PREFETCH␉0x08␉/* prefetchable? */␊ |
171 | #define PCI_BASE_ADDRESS_MEM_MASK␉(~(pciaddr_t)0x0f)␊ |
172 | #define PCI_BASE_ADDRESS_IO_MASK␉(~(pciaddr_t)0x03)␊ |
173 | /* bit 1 is reserved if address_space = 1 */␊ |
174 | ␊ |
175 | /* Header type 0 (normal devices) */␊ |
176 | #define PCI_CARDBUS_CIS␉␉␉␉␉0x28␊ |
177 | #define PCI_SUBSYSTEM_VENDOR_ID␉␉␉0x2c␊ |
178 | #define PCI_SUBSYSTEM_ID␉␉␉␉0x2e␊ |
179 | #define PCI_ROM_ADDRESS␉␉␉␉␉0x30␉␉/* Bits 31..11 are address, 10..1 reserved */␊ |
180 | #define PCI_ROM_ADDRESS_ENABLE␉␉␉0x01␊ |
181 | #define PCI_ROM_ADDRESS_MASK␉(~(pciaddr_t)0x7ff)␊ |
182 | ␊ |
183 | #define PCI_CAPABILITY_LIST␉␉␉␉0x34␉␉/* Offset of first capability list entry */␊ |
184 | ␊ |
185 | /* 0x35-0x3b are reserved */␊ |
186 | #define PCI_INTERRUPT_LINE␉␉␉␉0x3c␉␉/* 8 bits */␊ |
187 | #define PCI_INTERRUPT_PIN␉␉␉␉0x3d␉␉/* 8 bits */␊ |
188 | #define PCI_MIN_GNT␉␉␉␉␉␉0x3e␉␉/* 8 bits */␊ |
189 | #define PCI_MAX_LAT␉␉␉␉␉␉0x3f␉␉/* 8 bits */␊ |
190 | ␊ |
191 | /* Header type 1 (PCI-to-PCI bridges) */␊ |
192 | #define PCI_PRIMARY_BUS␉␉␉␉␉0x18␉␉/* Primary bus number */␊ |
193 | #define PCI_SECONDARY_BUS␉␉␉␉0x19␉␉/* Secondary bus number */␊ |
194 | #define PCI_SUBORDINATE_BUS␉␉␉␉0x1a␉␉/* Highest bus number behind the bridge */␊ |
195 | #define PCI_SEC_LATENCY_TIMER␉␉␉0x1b␉␉/* Latency timer for secondary interface */␊ |
196 | #define PCI_IO_BASE␉␉␉␉␉␉0x1c␉␉/* I/O range behind the bridge */␊ |
197 | #define PCI_IO_LIMIT␉␉␉␉␉0x1d␊ |
198 | #define PCI_IO_RANGE_TYPE_MASK␉␉␉0x0f␉␉/* I/O bridging type */␊ |
199 | #define PCI_IO_RANGE_TYPE_16␉␉␉0x00␊ |
200 | #define PCI_IO_RANGE_TYPE_32␉␉␉0x01␊ |
201 | #define PCI_IO_RANGE_MASK␉␉␉␉~0x0f␊ |
202 | #define PCI_SEC_STATUS␉␉␉␉␉0x1e␉␉/* Secondary status register */␊ |
203 | #define PCI_MEMORY_BASE␉␉␉␉␉0x20␉␉/* Memory range behind */␊ |
204 | #define PCI_MEMORY_LIMIT␉␉␉␉0x22␊ |
205 | #define PCI_MEMORY_RANGE_TYPE_MASK␉␉0x0f␊ |
206 | #define PCI_MEMORY_RANGE_MASK␉␉␉~0x0f␊ |
207 | #define PCI_PREF_MEMORY_BASE␉␉␉0x24␉␉/* Prefetchable memory range behind */␊ |
208 | #define PCI_PREF_MEMORY_LIMIT␉␉␉0x26␊ |
209 | #define PCI_PREF_RANGE_TYPE_MASK␉␉0x0f␊ |
210 | #define PCI_PREF_RANGE_TYPE_32␉␉␉0x00␊ |
211 | #define PCI_PREF_RANGE_TYPE_64␉␉␉0x01␊ |
212 | #define PCI_PREF_RANGE_MASK␉␉␉␉~0x0f␊ |
213 | #define PCI_PREF_BASE_UPPER32␉␉␉0x28␉␉/* Upper half of prefetchable memory range */␊ |
214 | #define PCI_PREF_LIMIT_UPPER32␉␉␉0x2c␊ |
215 | #define PCI_IO_BASE_UPPER16␉␉␉␉0x30␉␉/* Upper half of I/O addresses */␊ |
216 | #define PCI_IO_LIMIT_UPPER16␉␉␉0x32␊ |
217 | /* 0x34 same as for htype 0 */␊ |
218 | /* 0x35-0x3b is reserved */␊ |
219 | #define PCI_ROM_ADDRESS1␉␉␉␉0x38␉␉/* Same as PCI_ROM_ADDRESS, but for htype 1 */␊ |
220 | /* 0x3c-0x3d are same as for htype 0 */␊ |
221 | #define PCI_BRIDGE_CONTROL␉␉␉␉0x3e␊ |
222 | #define PCI_BRIDGE_CTL_PARITY␉␉␉0x01␉␉/* Enable parity detection on secondary interface */␊ |
223 | #define PCI_BRIDGE_CTL_SERR␉␉␉␉0x02␉␉/* The same for SERR forwarding */␊ |
224 | #define PCI_BRIDGE_CTL_NO_ISA␉␉␉0x04␉␉/* Disable bridging of ISA ports */␊ |
225 | #define PCI_BRIDGE_CTL_VGA␉␉␉␉0x08␉␉/* Forward VGA addresses */␊ |
226 | #define PCI_BRIDGE_CTL_MASTER_ABORT␉␉0x20␉␉/* Report master aborts */␊ |
227 | #define PCI_BRIDGE_CTL_BUS_RESET␉␉0x40␉␉/* Secondary bus reset */␊ |
228 | #define PCI_BRIDGE_CTL_FAST_BACK␉␉0x80␉␉/* Fast Back2Back enabled on secondary interface */␊ |
229 | #define PCI_BRIDGE_CTL_PRI_DISCARD_TIMER 0x100␉␉/* PCI-X? */␊ |
230 | #define PCI_BRIDGE_CTL_SEC_DISCARD_TIMER 0x200␉␉/* PCI-X? */␊ |
231 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_STATUS 0x400␉/* PCI-X? */␊ |
232 | #define PCI_BRIDGE_CTL_DISCARD_TIMER_SERR_EN 0x800␉/* PCI-X? */␊ |
233 | ␊ |
234 | /* Header type 2 (CardBus bridges) */␊ |
235 | /* 0x14-0x15 reserved */␊ |
236 | #define PCI_CB_SEC_STATUS␉␉␉␉0x16␉␉/* Secondary status */␊ |
237 | #define PCI_CB_PRIMARY_BUS␉␉␉␉0x18␉␉/* PCI bus number */␊ |
238 | #define PCI_CB_CARD_BUS␉␉␉␉␉0x19␉␉/* CardBus bus number */␊ |
239 | #define PCI_CB_SUBORDINATE_BUS␉␉␉0x1a␉␉/* Subordinate bus number */␊ |
240 | #define PCI_CB_LATENCY_TIMER␉␉␉0x1b␉␉/* CardBus latency timer */␊ |
241 | #define PCI_CB_MEMORY_BASE_0␉␉␉0x1c␊ |
242 | #define PCI_CB_MEMORY_LIMIT_0␉␉␉0x20␊ |
243 | #define PCI_CB_MEMORY_BASE_1␉␉␉0x24␊ |
244 | #define PCI_CB_MEMORY_LIMIT_1␉␉␉0x28␊ |
245 | #define PCI_CB_IO_BASE_0␉␉␉␉0x2c␊ |
246 | #define PCI_CB_IO_BASE_0_HI␉␉␉␉0x2e␊ |
247 | #define PCI_CB_IO_LIMIT_0␉␉␉␉0x30␊ |
248 | #define PCI_CB_IO_LIMIT_0_HI␉␉␉0x32␊ |
249 | #define PCI_CB_IO_BASE_1␉␉␉␉0x34␊ |
250 | #define PCI_CB_IO_BASE_1_HI␉␉␉␉0x36␊ |
251 | #define PCI_CB_IO_LIMIT_1␉␉␉␉0x38␊ |
252 | #define PCI_CB_IO_LIMIT_1_HI␉␉␉0x3a␊ |
253 | #define PCI_CB_IO_RANGE_MASK␉␉␉~0x03␊ |
254 | /* 0x3c-0x3d are same as for htype 0 */␊ |
255 | #define PCI_CB_BRIDGE_CONTROL␉␉␉0x3e␊ |
256 | #define PCI_CB_BRIDGE_CTL_PARITY␉␉0x01␉␉/* Similar to standard bridge control register */␊ |
257 | #define PCI_CB_BRIDGE_CTL_SERR␉␉␉0x02␊ |
258 | #define PCI_CB_BRIDGE_CTL_ISA␉␉␉0x04␊ |
259 | #define PCI_CB_BRIDGE_CTL_VGA␉␉␉0x08␊ |
260 | #define PCI_CB_BRIDGE_CTL_MASTER_ABORT␉0x20␊ |
261 | #define PCI_CB_BRIDGE_CTL_CB_RESET␉␉0x40␉␉/* CardBus reset */␊ |
262 | #define PCI_CB_BRIDGE_CTL_16BIT_INT␉␉0x80␉␉/* Enable interrupt for 16-bit cards */␊ |
263 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100␉␉/* Prefetch enable for both memory regions */␊ |
264 | #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200␊ |
265 | #define PCI_CB_BRIDGE_CTL_POST_WRITES␉0x400␊ |
266 | #define PCI_CB_SUBSYSTEM_VENDOR_ID␉␉0x40␊ |
267 | #define PCI_CB_SUBSYSTEM_ID␉␉␉␉0x42␊ |
268 | #define PCI_CB_LEGACY_MODE_BASE␉␉␉0x44␉␉/* 16-bit PC Card legacy mode base address (ExCa) */␊ |
269 | /* 0x48-0x7f reserved */␊ |
270 | ␊ |
271 | /* Capability lists */␊ |
272 | #define PCI_CAP_LIST_ID␉␉␉␉␉0␉␉␉/* Capability ID */␊ |
273 | #define PCI_CAP_ID_PM␉␉␉␉␉0x01␉␉/* Power Management */␊ |
274 | #define PCI_CAP_ID_AGP␉␉␉␉␉0x02␉␉/* Accelerated Graphics Port */␊ |
275 | #define PCI_CAP_ID_VPD␉␉␉␉␉0x03␉␉/* Vital Product Data */␊ |
276 | #define PCI_CAP_ID_SLOTID␉␉␉␉0x04␉␉/* Slot Identification */␊ |
277 | #define PCI_CAP_ID_MSI␉␉␉␉␉0x05␉␉/* Message Signaled Interrupts */␊ |
278 | #define PCI_CAP_ID_CHSWP␉␉␉␉0x06␉␉/* CompactPCI HotSwap */␊ |
279 | #define PCI_CAP_ID_PCIX␉␉␉␉␉0x07␉␉/* PCI-X */␊ |
280 | #define PCI_CAP_ID_HT␉␉␉␉␉0x08␉␉/* HyperTransport */␊ |
281 | #define PCI_CAP_ID_VNDR␉␉␉␉␉0x09␉␉/* Vendor specific */␊ |
282 | #define PCI_CAP_ID_DBG␉␉␉␉␉0x0A␉␉/* Debug port */␊ |
283 | #define PCI_CAP_ID_CCRC␉␉␉␉␉0x0B␉␉/* CompactPCI Central Resource Control */␊ |
284 | #define PCI_CAP_ID_HOTPLUG␉␉␉␉0x0C␉␉/* PCI hot-plug */␊ |
285 | #define PCI_CAP_ID_SSVID␉␉␉␉0x0D␉␉/* Bridge subsystem vendor/device ID */␊ |
286 | #define PCI_CAP_ID_AGP3␉␉␉␉␉0x0E␉␉/* AGP 8x */␊ |
287 | #define PCI_CAP_ID_SECURE␉␉␉␉0x0F␉␉/* Secure device (?) */␊ |
288 | #define PCI_CAP_ID_EXP␉␉␉␉␉0x10␉␉/* PCI Express */␊ |
289 | #define PCI_CAP_ID_MSIX␉␉␉␉␉0x11␉␉/* MSI-X */␊ |
290 | #define PCI_CAP_ID_SATA␉␉␉␉␉0x12␉␉/* Serial-ATA HBA */␊ |
291 | #define PCI_CAP_ID_AF␉␉␉␉␉0x13␉␉/* Advanced features of PCI devices integrated in PCIe root cplx */␊ |
292 | #define PCI_CAP_LIST_NEXT␉␉␉␉1␉␉␉/* Next capability in the list */␊ |
293 | #define PCI_CAP_FLAGS␉␉␉␉␉2␉␉␉/* Capability defined flags (16 bits) */␊ |
294 | #define PCI_CAP_SIZEOF␉␉␉␉␉4␊ |
295 | ␊ |
296 | /* Capabilities residing in the PCI Express extended configuration space */␊ |
297 | ␊ |
298 | #define PCI_EXT_CAP_ID_AER␉␉␉␉0x01␉␉/* Advanced Error Reporting */␊ |
299 | #define PCI_EXT_CAP_ID_VC␉␉␉␉0x02␉␉/* Virtual Channel */␊ |
300 | #define PCI_EXT_CAP_ID_DSN␉␉␉␉0x03␉␉/* Device Serial Number */␊ |
301 | #define PCI_EXT_CAP_ID_PB␉␉␉␉0x04␉␉/* Power Budgeting */␊ |
302 | #define PCI_EXT_CAP_ID_RCLINK␉␉␉0x05␉␉/* Root Complex Link Declaration */␊ |
303 | #define PCI_EXT_CAP_ID_RCILINK␉␉␉0x06␉␉/* Root Complex Internal Link Declaration */␊ |
304 | #define PCI_EXT_CAP_ID_RCECOLL␉␉␉0x07␉␉/* Root Complex Event Collector */␊ |
305 | #define PCI_EXT_CAP_ID_MFVC␉␉␉␉0x08␉␉/* Multi-Function Virtual Channel */␊ |
306 | #define PCI_EXT_CAP_ID_RBCB␉␉␉␉0x0a␉␉/* Root Bridge Control Block */␊ |
307 | #define PCI_EXT_CAP_ID_VNDR␉␉␉␉0x0b␉␉/* Vendor specific */␊ |
308 | #define PCI_EXT_CAP_ID_ACS␉␉␉␉0x0d␉␉/* Access Controls */␊ |
309 | #define PCI_EXT_CAP_ID_ARI␉␉␉␉0x0e␉␉/* Alternative Routing-ID Interpretation */␊ |
310 | #define PCI_EXT_CAP_ID_ATS␉␉␉␉0x0f␉␉/* Address Translation Service */␊ |
311 | #define PCI_EXT_CAP_ID_SRIOV␉␉␉0x10␉␉/* Single Root I/O Virtualization */␊ |
312 | ␊ |
313 | /* Power Management Registers */␊ |
314 | ␊ |
315 | #define PCI_PM_CAP_VER_MASK␉␉␉␉0x0007␉␉/* Version (2=PM1.1) */␊ |
316 | #define PCI_PM_CAP_PME_CLOCK␉␉␉0x0008␉␉/* Clock required for PME generation */␊ |
317 | #define PCI_PM_CAP_DSI␉␉␉␉␉0x0020␉␉/* Device specific initialization required */␊ |
318 | #define PCI_PM_CAP_AUX_C_MASK␉␉␉0x01c0␉␉/* Maximum aux current required in D3cold */␊ |
319 | #define PCI_PM_CAP_D1␉␉␉␉␉0x0200␉␉/* D1 power state support */␊ |
320 | #define PCI_PM_CAP_D2␉␉␉␉␉0x0400␉␉/* D2 power state support */␊ |
321 | #define PCI_PM_CAP_PME_D0␉␉␉␉0x0800␉␉/* PME can be asserted from D0 */␊ |
322 | #define PCI_PM_CAP_PME_D1␉␉␉␉0x1000␉␉/* PME can be asserted from D1 */␊ |
323 | #define PCI_PM_CAP_PME_D2␉␉␉␉0x2000␉␉/* PME can be asserted from D2 */␊ |
324 | #define PCI_PM_CAP_PME_D3_HOT␉␉␉0x4000␉␉/* PME can be asserted from D3hot */␊ |
325 | #define PCI_PM_CAP_PME_D3_COLD␉␉␉0x8000␉␉/* PME can be asserted from D3cold */␊ |
326 | #define PCI_PM_CTRL␉␉␉␉␉␉4␉␉␉/* PM control and status register */␊ |
327 | #define PCI_PM_CTRL_STATE_MASK␉␉␉0x0003␉␉/* Current power state (D0 to D3) */␊ |
328 | #define PCI_PM_CTRL_PME_ENABLE␉␉␉0x0100␉␉/* PME pin enable */␊ |
329 | #define PCI_PM_CTRL_DATA_SEL_MASK␉␉0x1e00␉␉/* PM table data index */␊ |
330 | #define PCI_PM_CTRL_DATA_SCALE_MASK␉␉0x6000␉␉/* PM table data scaling factor */␊ |
331 | #define PCI_PM_CTRL_PME_STATUS␉␉␉0x8000␉␉/* PME pin status */␊ |
332 | #define PCI_PM_PPB_EXTENSIONS␉␉␉6␉␉␉/* PPB support extensions */␊ |
333 | #define PCI_PM_PPB_B2_B3␉␉␉␉0x40␉␉/* If bridge enters D3hot, bus enters: 0=B3, 1=B2 */␊ |
334 | #define PCI_PM_BPCC_ENABLE␉␉␉␉0x80␉␉/* Secondary bus is power managed */␊ |
335 | #define PCI_PM_DATA_REGISTER␉␉␉7␉␉␉/* PM table contents read here */␊ |
336 | #define PCI_PM_SIZEOF␉␉␉␉␉8␊ |
337 | ␊ |
338 | /* AGP registers */␊ |
339 | ␊ |
340 | #define PCI_AGP_VERSION␉␉␉␉␉2␉␉␉/* BCD version number */␊ |
341 | #define PCI_AGP_RFU␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
342 | #define PCI_AGP_STATUS␉␉␉␉␉4␉␉␉/* Status register */␊ |
343 | #define PCI_AGP_STATUS_RQ_MASK␉␉␉0xff000000␉/* Maximum number of requests - 1 */␊ |
344 | #define PCI_AGP_STATUS_ISOCH␉␉␉0x10000␉␉/* Isochronous transactions supported */␊ |
345 | #define PCI_AGP_STATUS_ARQSZ_MASK␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
346 | #define PCI_AGP_STATUS_CAL_MASK␉␉␉0x1c00␉␉/* Calibration cycle timing */␊ |
347 | #define PCI_AGP_STATUS_SBA␉␉␉␉0x0200␉␉/* Sideband addressing supported */␊ |
348 | #define PCI_AGP_STATUS_ITA_COH␉␉␉0x0100␉␉/* In-aperture accesses always coherent */␊ |
349 | #define PCI_AGP_STATUS_GART64␉␉␉0x0080␉␉/* 64-bit GART entries supported */␊ |
350 | #define PCI_AGP_STATUS_HTRANS␉␉␉0x0040␉␉/* If 0, core logic can xlate host CPU accesses thru aperture */␊ |
351 | #define PCI_AGP_STATUS_64BIT␉␉␉0x0020␉␉/* 64-bit addressing cycles supported */␊ |
352 | #define PCI_AGP_STATUS_FW␉␉␉␉0x0010␉␉/* Fast write transfers supported */␊ |
353 | #define PCI_AGP_STATUS_AGP3␉␉␉␉0x0008␉␉/* AGP3 mode supported */␊ |
354 | #define PCI_AGP_STATUS_RATE4␉␉␉0x0004␉␉/* 4x transfer rate supported (RFU in AGP3 mode) */␊ |
355 | #define PCI_AGP_STATUS_RATE2␉␉␉0x0002␉␉/* 2x transfer rate supported (8x in AGP3 mode) */␊ |
356 | #define PCI_AGP_STATUS_RATE1␉␉␉0x0001␉␉/* 1x transfer rate supported (4x in AGP3 mode) */␊ |
357 | #define PCI_AGP_COMMAND␉␉␉␉␉8␉␉␉/* Control register */␊ |
358 | #define PCI_AGP_COMMAND_RQ_MASK␉␉␉0xff000000 /* Master: Maximum number of requests */␊ |
359 | #define PCI_AGP_COMMAND_ARQSZ_MASK␉␉0xe000␉␉/* log2(optimum async req size in bytes) - 4 */␊ |
360 | #define PCI_AGP_COMMAND_CAL_MASK␉␉0x1c00␉␉/* Calibration cycle timing */␊ |
361 | #define PCI_AGP_COMMAND_SBA␉␉␉␉0x0200␉␉/* Sideband addressing enabled */␊ |
362 | #define PCI_AGP_COMMAND_AGP␉␉␉␉0x0100␉␉/* Allow processing of AGP transactions */␊ |
363 | #define PCI_AGP_COMMAND_GART64␉␉␉0x0080␉␉/* 64-bit GART entries enabled */␊ |
364 | #define PCI_AGP_COMMAND_64BIT␉␉␉0x0020␉␉/* Allow generation of 64-bit addr cycles */␊ |
365 | #define PCI_AGP_COMMAND_FW␉␉␉␉0x0010␉␉/* Enable FW transfers */␊ |
366 | #define PCI_AGP_COMMAND_RATE4␉␉␉0x0004␉␉/* Use 4x rate (RFU in AGP3 mode) */␊ |
367 | #define PCI_AGP_COMMAND_RATE2␉␉␉0x0002␉␉/* Use 2x rate (8x in AGP3 mode) */␊ |
368 | #define PCI_AGP_COMMAND_RATE1␉␉␉0x0001␉␉/* Use 1x rate (4x in AGP3 mode) */␊ |
369 | #define PCI_AGP_SIZEOF␉␉␉␉␉12␊ |
370 | ␊ |
371 | /* Vital Product Data */␊ |
372 | ␊ |
373 | #define PCI_VPD_ADDR␉␉␉␉␉2␉␉␉/* Address to access (15 bits!) */␊ |
374 | #define PCI_VPD_ADDR_MASK␉␉␉␉0x7fff␉␉/* Address mask */␊ |
375 | #define PCI_VPD_ADDR_F␉␉␉␉␉0x8000␉␉/* Write 0, 1 indicates completion */␊ |
376 | #define PCI_VPD_DATA␉␉␉␉␉4␉␉␉/* 32-bits of data returned here */␊ |
377 | ␊ |
378 | /* Slot Identification */␊ |
379 | ␊ |
380 | #define PCI_SID_ESR␉␉␉␉␉␉2␉␉␉/* Expansion Slot Register */␊ |
381 | #define PCI_SID_ESR_NSLOTS␉␉␉␉0x1f␉␉/* Number of expansion slots available */␊ |
382 | #define PCI_SID_ESR_FIC␉␉␉␉␉0x20␉␉/* First In Chassis Flag */␊ |
383 | #define PCI_SID_CHASSIS_NR␉␉␉␉3␉␉␉/* Chassis Number */␊ |
384 | ␊ |
385 | /* Message Signaled Interrupts registers */␊ |
386 | ␊ |
387 | #define PCI_MSI_FLAGS␉␉␉␉␉2␉␉␉/* Various flags */␊ |
388 | #define PCI_MSI_FLAGS_MASK_BIT␉␉␉0x100␉␉/* interrupt masking & reporting supported */␊ |
389 | #define PCI_MSI_FLAGS_64BIT␉␉␉␉0x080␉␉/* 64-bit addresses allowed */␊ |
390 | #define PCI_MSI_FLAGS_QSIZE␉␉␉␉0x070␉␉/* Message queue size configured */␊ |
391 | #define PCI_MSI_FLAGS_QMASK␉␉␉␉0x00e␉␉/* Maximum queue size available */␊ |
392 | #define PCI_MSI_FLAGS_ENABLE␉␉␉0x001␉␉/* MSI feature enabled */␊ |
393 | #define PCI_MSI_RFU␉␉␉␉␉␉3␉␉␉/* Rest of capability flags */␊ |
394 | #define PCI_MSI_ADDRESS_LO␉␉␉␉4␉␉␉/* Lower 32 bits */␊ |
395 | #define PCI_MSI_ADDRESS_HI␉␉␉␉8␉␉␉/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */␊ |
396 | #define PCI_MSI_DATA_32␉␉␉␉␉8␉␉␉/* 16 bits of data for 32-bit devices */␊ |
397 | #define PCI_MSI_DATA_64␉␉␉␉␉12␉␉␉/* 16 bits of data for 64-bit devices */␊ |
398 | #define PCI_MSI_MASK_BIT_32␉␉␉␉12␉␉␉/* per-vector masking for 32-bit devices */␊ |
399 | #define PCI_MSI_MASK_BIT_64␉␉␉␉16␉␉␉/* per-vector masking for 64-bit devices */␊ |
400 | #define PCI_MSI_PENDING_32␉␉␉␉16␉␉␉/* per-vector interrupt pending for 32-bit devices */␊ |
401 | #define PCI_MSI_PENDING_64␉␉␉␉20␉␉␉/* per-vector interrupt pending for 64-bit devices */␊ |
402 | ␊ |
403 | /* PCI-X */␊ |
404 | #define PCI_PCIX_COMMAND 2 /* Command register offset */␊ |
405 | #define PCI_PCIX_COMMAND_DPERE 0x0001 /* Data Parity Error Recover Enable */␊ |
406 | #define PCI_PCIX_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */␊ |
407 | #define PCI_PCIX_COMMAND_MAX_MEM_READ_BYTE_COUNT 0x000c /* Maximum Memory Read Byte Count */␊ |
408 | #define PCI_PCIX_COMMAND_MAX_OUTSTANDING_SPLIT_TRANS 0x0070␊ |
409 | #define PCI_PCIX_COMMAND_RESERVED 0xf80␊ |
410 | #define PCI_PCIX_STATUS 4 /* Status register offset */␊ |
411 | #define PCI_PCIX_STATUS_FUNCTION 0x00000007␊ |
412 | #define PCI_PCIX_STATUS_DEVICE 0x000000f8␊ |
413 | #define PCI_PCIX_STATUS_BUS 0x0000ff00␊ |
414 | #define PCI_PCIX_STATUS_64BIT 0x00010000␊ |
415 | #define PCI_PCIX_STATUS_133MHZ 0x00020000␊ |
416 | #define PCI_PCIX_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */␊ |
417 | #define PCI_PCIX_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */␊ |
418 | #define PCI_PCIX_STATUS_DEVICE_COMPLEXITY 0x00100000 /* 0 = simple device, 1 = bridge device */␊ |
419 | #define PCI_PCIX_STATUS_DESIGNED_MAX_MEM_READ_BYTE_COUNT 0x00600000 /* 0 = 512 bytes, 1 = 1024, 2 = 2048, 3 = 4096 */␊ |
420 | #define PCI_PCIX_STATUS_DESIGNED_MAX_OUTSTANDING_SPLIT_TRANS 0x03800000␊ |
421 | #define PCI_PCIX_STATUS_DESIGNED_MAX_CUMULATIVE_READ_SIZE 0x1c000000␊ |
422 | #define PCI_PCIX_STATUS_RCVD_SC_ERR_MESS 0x20000000 /* Received Split Completion Error Message */␊ |
423 | #define PCI_PCIX_STATUS_266MHZ␉␉␉␉␉␉␉␉␉0x40000000 /* 266 MHz capable */␊ |
424 | #define PCI_PCIX_STATUS_533MHZ␉␉␉␉ 0x80000000 /* 533 MHz capable */␊ |
425 | #define PCI_PCIX_SIZEOF␉␉4␊ |
426 | ␊ |
427 | /* PCI-X Bridges */␊ |
428 | #define PCI_PCIX_BRIDGE_SEC_STATUS 2 /* Secondary bus status register offset */␊ |
429 | #define PCI_PCIX_BRIDGE_SEC_STATUS_64BIT 0x0001␊ |
430 | #define PCI_PCIX_BRIDGE_SEC_STATUS_133MHZ 0x0002␊ |
431 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_DISCARDED 0x0004 /* Split Completion Discarded on secondary bus */␊ |
432 | #define PCI_PCIX_BRIDGE_SEC_STATUS_UNEXPECTED_SC 0x0008 /* Unexpected Split Completion on secondary bus */␊ |
433 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SC_OVERRUN 0x0010 /* Split Completion Overrun on secondary bus */␊ |
434 | #define PCI_PCIX_BRIDGE_SEC_STATUS_SPLIT_REQUEST_DELAYED 0x0020␊ |
435 | #define PCI_PCIX_BRIDGE_SEC_STATUS_CLOCK_FREQ 0x01c0␊ |
436 | #define PCI_PCIX_BRIDGE_SEC_STATUS_RESERVED 0xfe00␊ |
437 | #define PCI_PCIX_BRIDGE_STATUS 4 /* Primary bus status register offset */␊ |
438 | #define PCI_PCIX_BRIDGE_STATUS_FUNCTION 0x00000007␊ |
439 | #define PCI_PCIX_BRIDGE_STATUS_DEVICE 0x000000f8␊ |
440 | #define PCI_PCIX_BRIDGE_STATUS_BUS 0x0000ff00␊ |
441 | #define PCI_PCIX_BRIDGE_STATUS_64BIT 0x00010000␊ |
442 | #define PCI_PCIX_BRIDGE_STATUS_133MHZ 0x00020000␊ |
443 | #define PCI_PCIX_BRIDGE_STATUS_SC_DISCARDED 0x00040000 /* Split Completion Discarded */␊ |
444 | #define PCI_PCIX_BRIDGE_STATUS_UNEXPECTED_SC 0x00080000 /* Unexpected Split Completion */␊ |
445 | #define PCI_PCIX_BRIDGE_STATUS_SC_OVERRUN 0x00100000 /* Split Completion Overrun */␊ |
446 | #define PCI_PCIX_BRIDGE_STATUS_SPLIT_REQUEST_DELAYED 0x00200000␊ |
447 | #define PCI_PCIX_BRIDGE_STATUS_RESERVED 0xffc00000␊ |
448 | #define PCI_PCIX_BRIDGE_UPSTREAM_SPLIT_TRANS_CTRL 8 /* Upstream Split Transaction Register offset */␊ |
449 | #define PCI_PCIX_BRIDGE_DOWNSTREAM_SPLIT_TRANS_CTRL 12 /* Downstream Split Transaction Register offset */␊ |
450 | #define PCI_PCIX_BRIDGE_STR_CAPACITY 0x0000ffff␊ |
451 | #define PCI_PCIX_BRIDGE_STR_COMMITMENT_LIMIT 0xffff0000␊ |
452 | #define PCI_PCIX_BRIDGE_SIZEOF 12␊ |
453 | ␊ |
454 | /* PCI Express */␊ |
455 | #define PCI_EXP_FLAGS␉␉0x2␉/* Capabilities register */␊ |
456 | #define PCI_EXP_FLAGS_VERS␉0x000f␉/* Capability version */␊ |
457 | #define PCI_EXP_FLAGS_TYPE␉0x00f0␉/* Device/Port type */␊ |
458 | #define PCI_EXP_TYPE_ENDPOINT␉0x0␉/* Express Endpoint */␊ |
459 | #define PCI_EXP_TYPE_LEG_END␉0x1␉/* Legacy Endpoint */␊ |
460 | #define PCI_EXP_TYPE_ROOT_PORT 0x4␉/* Root Port */␊ |
461 | #define PCI_EXP_TYPE_UPSTREAM␉0x5␉/* Upstream Port */␊ |
462 | #define PCI_EXP_TYPE_DOWNSTREAM 0x6␉/* Downstream Port */␊ |
463 | #define PCI_EXP_TYPE_PCI_BRIDGE 0x7␉/* PCI/PCI-X Bridge */␊ |
464 | #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8␉/* PCI/PCI-X to PCIE Bridge */␊ |
465 | #define PCI_EXP_TYPE_ROOT_INT_EP 0x9␉/* Root Complex Integrated Endpoint */␊ |
466 | #define PCI_EXP_TYPE_ROOT_EC 0xa␉/* Root Complex Event Collector */␊ |
467 | #define PCI_EXP_FLAGS_SLOT␉0x0100␉/* Slot implemented */␊ |
468 | #define PCI_EXP_FLAGS_IRQ␉0x3e00␉/* Interrupt message number */␊ |
469 | #define PCI_EXP_DEVCAP␉␉0x4␉/* Device capabilities */␊ |
470 | #define PCI_EXP_DEVCAP_PAYLOAD␉0x07␉/* Max_Payload_Size */␊ |
471 | #define PCI_EXP_DEVCAP_PHANTOM␉0x18␉/* Phantom functions */␊ |
472 | #define PCI_EXP_DEVCAP_EXT_TAG␉0x20␉/* Extended tags */␊ |
473 | #define PCI_EXP_DEVCAP_L0S␉0x1c0␉/* L0s Acceptable Latency */␊ |
474 | #define PCI_EXP_DEVCAP_L1␉0xe00␉/* L1 Acceptable Latency */␊ |
475 | #define PCI_EXP_DEVCAP_ATN_BUT␉0x1000␉/* Attention Button Present */␊ |
476 | #define PCI_EXP_DEVCAP_ATN_IND␉0x2000␉/* Attention Indicator Present */␊ |
477 | #define PCI_EXP_DEVCAP_PWR_IND␉0x4000␉/* Power Indicator Present */␊ |
478 | #define PCI_EXP_DEVCAP_RBE␉0x8000␉/* Role-Based Error Reporting */␊ |
479 | #define PCI_EXP_DEVCAP_PWR_VAL␉0x3fc0000 /* Slot Power Limit Value */␊ |
480 | #define PCI_EXP_DEVCAP_PWR_SCL␉0xc000000 /* Slot Power Limit Scale */␊ |
481 | #define PCI_EXP_DEVCAP_FLRESET␉0x10000000 /* Function-Level Reset */␊ |
482 | #define PCI_EXP_DEVCTL␉␉0x8␉/* Device Control */␊ |
483 | #define PCI_EXP_DEVCTL_CERE␉0x0001␉/* Correctable Error Reporting En. */␊ |
484 | #define PCI_EXP_DEVCTL_NFERE␉0x0002␉/* Non-Fatal Error Reporting Enable */␊ |
485 | #define PCI_EXP_DEVCTL_FERE␉0x0004␉/* Fatal Error Reporting Enable */␊ |
486 | #define PCI_EXP_DEVCTL_URRE␉0x0008␉/* Unsupported Request Reporting En. */␊ |
487 | #define PCI_EXP_DEVCTL_RELAXED␉0x0010␉/* Enable Relaxed Ordering */␊ |
488 | #define PCI_EXP_DEVCTL_PAYLOAD␉0x00e0␉/* Max_Payload_Size */␊ |
489 | #define PCI_EXP_DEVCTL_EXT_TAG␉0x0100␉/* Extended Tag Field Enable */␊ |
490 | #define PCI_EXP_DEVCTL_PHANTOM␉0x0200␉/* Phantom Functions Enable */␊ |
491 | #define PCI_EXP_DEVCTL_AUX_PME␉0x0400␉/* Auxiliary Power PM Enable */␊ |
492 | #define PCI_EXP_DEVCTL_NOSNOOP␉0x0800␉/* Enable No Snoop */␊ |
493 | #define PCI_EXP_DEVCTL_READRQ␉0x7000␉/* Max_Read_Request_Size */␊ |
494 | #define PCI_EXP_DEVCTL_BCRE␉0x8000␉/* Bridge Configuration Retry Enable */␊ |
495 | #define PCI_EXP_DEVCTL_FLRESET␉0x8000␉/* Function-Level Reset [bit shared with BCRE] */␊ |
496 | #define PCI_EXP_DEVSTA␉␉0xa␉/* Device Status */␊ |
497 | #define PCI_EXP_DEVSTA_CED␉0x01␉/* Correctable Error Detected */␊ |
498 | #define PCI_EXP_DEVSTA_NFED␉0x02␉/* Non-Fatal Error Detected */␊ |
499 | #define PCI_EXP_DEVSTA_FED␉0x04␉/* Fatal Error Detected */␊ |
500 | #define PCI_EXP_DEVSTA_URD␉0x08␉/* Unsupported Request Detected */␊ |
501 | #define PCI_EXP_DEVSTA_AUXPD␉0x10␉/* AUX Power Detected */␊ |
502 | #define PCI_EXP_DEVSTA_TRPND␉0x20␉/* Transactions Pending */␊ |
503 | #define PCI_EXP_LNKCAP␉␉0xc␉/* Link Capabilities */␊ |
504 | #define PCI_EXP_LNKCAP_SPEED␉0x0000f␉/* Maximum Link Speed */␊ |
505 | #define PCI_EXP_LNKCAP_WIDTH␉0x003f0␉/* Maximum Link Width */␊ |
506 | #define PCI_EXP_LNKCAP_ASPM␉0x00c00␉/* Active State Power Management */␊ |
507 | #define PCI_EXP_LNKCAP_L0S␉0x07000␉/* L0s Acceptable Latency */␊ |
508 | #define PCI_EXP_LNKCAP_L1␉0x38000␉/* L1 Acceptable Latency */␊ |
509 | #define PCI_EXP_LNKCAP_CLOCKPM␉0x40000␉/* Clock Power Management */␊ |
510 | #define PCI_EXP_LNKCAP_SURPRISE 0x80000 /* Surprise Down Error Reporting */␊ |
511 | #define PCI_EXP_LNKCAP_DLLA␉0x100000 /* Data Link Layer Active Reporting */␊ |
512 | #define PCI_EXP_LNKCAP_LBNC␉0x200000 /* Link Bandwidth Notification Capability */␊ |
513 | #define PCI_EXP_LNKCAP_PORT␉0xff000000 /* Port Number */␊ |
514 | #define PCI_EXP_LNKCTL␉␉0x10␉/* Link Control */␊ |
515 | #define PCI_EXP_LNKCTL_ASPM␉0x0003␉/* ASPM Control */␊ |
516 | #define PCI_EXP_LNKCTL_RCB␉0x0008␉/* Read Completion Boundary */␊ |
517 | #define PCI_EXP_LNKCTL_DISABLE␉0x0010␉/* Link Disable */␊ |
518 | #define PCI_EXP_LNKCTL_RETRAIN␉0x0020␉/* Retrain Link */␊ |
519 | #define PCI_EXP_LNKCTL_CLOCK␉0x0040␉/* Common Clock Configuration */␊ |
520 | #define PCI_EXP_LNKCTL_XSYNCH␉0x0080␉/* Extended Synch */␊ |
521 | #define PCI_EXP_LNKCTL_CLOCKPM␉0x0100␉/* Clock Power Management */␊ |
522 | #define PCI_EXP_LNKCTL_HWAUTWD␉0x0200␉/* Hardware Autonomous Width Disable */␊ |
523 | #define PCI_EXP_LNKCTL_BWMIE␉0x0400␉/* Bandwidth Mgmt Interrupt Enable */␊ |
524 | #define PCI_EXP_LNKCTL_AUTBWIE␉0x0800␉/* Autonomous Bandwidth Mgmt Interrupt Enable */␊ |
525 | #define PCI_EXP_LNKSTA␉␉0x12␉/* Link Status */␊ |
526 | #define PCI_EXP_LNKSTA_SPEED␉0x000f␉/* Negotiated Link Speed */␊ |
527 | #define PCI_EXP_LNKSTA_WIDTH␉0x03f0␉/* Negotiated Link Width */␊ |
528 | #define PCI_EXP_LNKSTA_TR_ERR␉0x0400␉/* Training Error (obsolete) */␊ |
529 | #define PCI_EXP_LNKSTA_TRAIN␉0x0800␉/* Link Training */␊ |
530 | #define PCI_EXP_LNKSTA_SL_CLK␉0x1000␉/* Slot Clock Configuration */␊ |
531 | #define PCI_EXP_LNKSTA_DL_ACT␉0x2000␉/* Data Link Layer in DL_Active State */␊ |
532 | #define PCI_EXP_LNKSTA_BWMGMT␉0x4000␉/* Bandwidth Mgmt Status */␊ |
533 | #define PCI_EXP_LNKSTA_AUTBW␉0x8000␉/* Autonomous Bandwidth Mgmt Status */␊ |
534 | #define PCI_EXP_SLTCAP␉␉0x14␉/* Slot Capabilities */␊ |
535 | #define PCI_EXP_SLTCAP_ATNB␉0x0001␉/* Attention Button Present */␊ |
536 | #define PCI_EXP_SLTCAP_PWRC␉0x0002␉/* Power Controller Present */␊ |
537 | #define PCI_EXP_SLTCAP_MRL␉0x0004␉/* MRL Sensor Present */␊ |
538 | #define PCI_EXP_SLTCAP_ATNI␉0x0008␉/* Attention Indicator Present */␊ |
539 | #define PCI_EXP_SLTCAP_PWRI␉0x0010␉/* Power Indicator Present */␊ |
540 | #define PCI_EXP_SLTCAP_HPS␉0x0020␉/* Hot-Plug Surprise */␊ |
541 | #define PCI_EXP_SLTCAP_HPC␉0x0040␉/* Hot-Plug Capable */␊ |
542 | #define PCI_EXP_SLTCAP_PWR_VAL␉0x00007f80 /* Slot Power Limit Value */␊ |
543 | #define PCI_EXP_SLTCAP_PWR_SCL␉0x00018000 /* Slot Power Limit Scale */␊ |
544 | #define PCI_EXP_SLTCAP_INTERLOCK 0x020000 /* Electromechanical Interlock Present */␊ |
545 | #define PCI_EXP_SLTCAP_NOCMDCOMP 0x040000 /* No Command Completed Support */␊ |
546 | #define PCI_EXP_SLTCAP_PSN␉0xfff80000 /* Physical Slot Number */␊ |
547 | #define PCI_EXP_SLTCTL␉␉0x18␉/* Slot Control */␊ |
548 | #define PCI_EXP_SLTCTL_ATNB␉0x0001␉/* Attention Button Pressed Enable */␊ |
549 | #define PCI_EXP_SLTCTL_PWRF␉0x0002␉/* Power Fault Detected Enable */␊ |
550 | #define PCI_EXP_SLTCTL_MRLS␉0x0004␉/* MRL Sensor Changed Enable */␊ |
551 | #define PCI_EXP_SLTCTL_PRSD␉0x0008␉/* Presence Detect Changed Enable */␊ |
552 | #define PCI_EXP_SLTCTL_CMDC␉0x0010␉/* Command Completed Interrupt Enable */␊ |
553 | #define PCI_EXP_SLTCTL_HPIE␉0x0020␉/* Hot-Plug Interrupt Enable */␊ |
554 | #define PCI_EXP_SLTCTL_ATNI␉0x00c0␉/* Attention Indicator Control */␊ |
555 | #define PCI_EXP_SLTCTL_PWRI␉0x0300␉/* Power Indicator Control */␊ |
556 | #define PCI_EXP_SLTCTL_PWRC␉0x0400␉/* Power Controller Control */␊ |
557 | #define PCI_EXP_SLTCTL_INTERLOCK 0x0800 /* Electromechanical Interlock Control */␊ |
558 | #define PCI_EXP_SLTCTL_LLCHG␉0x1000␉/* Data Link Layer State Changed Enable */␊ |
559 | #define PCI_EXP_SLTSTA␉␉0x1a␉/* Slot Status */␊ |
560 | #define PCI_EXP_SLTSTA_ATNB␉0x0001␉/* Attention Button Pressed */␊ |
561 | #define PCI_EXP_SLTSTA_PWRF␉0x0002␉/* Power Fault Detected */␊ |
562 | #define PCI_EXP_SLTSTA_MRLS␉0x0004␉/* MRL Sensor Changed */␊ |
563 | #define PCI_EXP_SLTSTA_PRSD␉0x0008␉/* Presence Detect Changed */␊ |
564 | #define PCI_EXP_SLTSTA_CMDC␉0x0010␉/* Command Completed */␊ |
565 | #define PCI_EXP_SLTSTA_MRL_ST␉0x0020␉/* MRL Sensor State */␊ |
566 | #define PCI_EXP_SLTSTA_PRES␉0x0040␉/* Presence Detect State */␊ |
567 | #define PCI_EXP_SLTSTA_INTERLOCK 0x0080 /* Electromechanical Interlock Status */␊ |
568 | #define PCI_EXP_SLTSTA_LLCHG␉0x0100␉/* Data Link Layer State Changed */␊ |
569 | #define PCI_EXP_RTCTL␉␉0x1c␉/* Root Control */␊ |
570 | #define PCI_EXP_RTCTL_SECEE␉0x0001␉/* System Error on Correctable Error */␊ |
571 | #define PCI_EXP_RTCTL_SENFEE␉0x0002␉/* System Error on Non-Fatal Error */␊ |
572 | #define PCI_EXP_RTCTL_SEFEE␉0x0004␉/* System Error on Fatal Error */␊ |
573 | #define PCI_EXP_RTCTL_PMEIE␉0x0008␉/* PME Interrupt Enable */␊ |
574 | #define PCI_EXP_RTCTL_CRSVIS␉0x0010␉/* Configuration Request Retry Status Visible to SW */␊ |
575 | #define PCI_EXP_RTCAP␉␉0x1e␉/* Root Capabilities */␊ |
576 | #define PCI_EXP_RTCAP_CRSVIS␉0x0010␉/* Configuration Request Retry Status Visible to SW */␊ |
577 | #define PCI_EXP_RTSTA␉␉0x20␉/* Root Status */␊ |
578 | #define PCI_EXP_RTSTA_PME_REQID 0x0000ffff /* PME Requester ID */␊ |
579 | #define PCI_EXP_RTSTA_PME_STATUS 0x00010000 /* PME Status */␊ |
580 | #define PCI_EXP_RTSTA_PME_PENDING 0x00020000 /* PME is Pending */␊ |
581 | #define PCI_EXP_DEVCAP2␉␉␉0x24␉/* Device capabilities 2 */␊ |
582 | #define PCI_EXP_DEVCTL2␉␉␉0x28␉/* Device Control */␊ |
583 | #define PCI_EXP_DEV2_TIMEOUT_RANGE(x)␉((x) & 0xf) /* Completion Timeout Ranges Supported */␊ |
584 | #define PCI_EXP_DEV2_TIMEOUT_VALUE(x)␉((x) & 0xf) /* Completion Timeout Value */␊ |
585 | #define PCI_EXP_DEV2_TIMEOUT_DIS␉0x0010␉/* Completion Timeout Disable Supported */␊ |
586 | #define PCI_EXP_DEV2_ARI␉␉0x0020␉/* ARI Forwarding */␊ |
587 | #define PCI_EXP_DEVSTA2␉␉␉0x2a␉/* Device Status */␊ |
588 | #define PCI_EXP_LNKCAP2␉␉␉0x2c␉/* Link Capabilities */␊ |
589 | #define PCI_EXP_LNKCTL2␉␉␉0x30␉/* Link Control */␊ |
590 | #define PCI_EXP_LNKCTL2_SPEED(x)␉((x) & 0xf) /* Target Link Speed */␊ |
591 | #define PCI_EXP_LNKCTL2_CMPLNC␉␉0x0010␉/* Enter Compliance */␊ |
592 | #define PCI_EXP_LNKCTL2_SPEED_DIS␉0x0020␉/* Hardware Autonomous Speed Disable */␊ |
593 | #define PCI_EXP_LNKCTL2_DEEMPHASIS(x)␉(((x) >> 6) & 1) /* Selectable De-emphasis */␊ |
594 | #define PCI_EXP_LNKCTL2_MARGIN(x)␉(((x) >> 7) & 7) /* Transmit Margin */␊ |
595 | #define PCI_EXP_LNKCTL2_MOD_CMPLNC␉0x0400␉/* Enter Modified Compliance */␊ |
596 | #define PCI_EXP_LNKCTL2_CMPLNC_SOS␉0x0800␉/* Compliance SOS */␊ |
597 | #define PCI_EXP_LNKCTL2_COM_DEEMPHASIS(x) (((x) >> 12) & 1) /* Compliance De-emphasis */␊ |
598 | #define PCI_EXP_LNKSTA2␉␉␉0x32␉/* Link Status */␊ |
599 | #define PCI_EXP_LINKSTA2_DEEMPHASIS(x)␉((x) & 1)␉/* Current De-emphasis Level */␊ |
600 | #define PCI_EXP_SLTCAP2␉␉␉0x34␉/* Slot Capabilities */␊ |
601 | #define PCI_EXP_SLTCTL2␉␉␉0x38␉/* Slot Control */␊ |
602 | #define PCI_EXP_SLTSTA2␉␉␉0x3a␉/* Slot Status */␊ |
603 | ␊ |
604 | /* MSI-X */␊ |
605 | #define PCI_MSIX_ENABLE␉␉0x8000␊ |
606 | #define PCI_MSIX_MASK␉␉0x4000␊ |
607 | #define PCI_MSIX_TABSIZE␉0x03ff␊ |
608 | #define PCI_MSIX_TABLE␉␉4␊ |
609 | #define PCI_MSIX_PBA␉␉8␊ |
610 | #define PCI_MSIX_BIR␉␉0x7␊ |
611 | ␊ |
612 | /* Subsystem vendor/device ID for PCI bridges */␊ |
613 | #define PCI_SSVID_VENDOR␉4␊ |
614 | #define PCI_SSVID_DEVICE␉6␊ |
615 | ␊ |
616 | /* Advanced Error Reporting */␊ |
617 | #define PCI_ERR_UNCOR_STATUS␉4␉␉␉/* Uncorrectable Error Status */␊ |
618 | #define PCI_ERR_UNC_TRAIN␉␉0x00000001␉/* Undefined in PCIe rev1.1 & 2.0 spec */␊ |
619 | #define PCI_ERR_UNC_DLP␉␉␉0x00000010␉/* Data Link Protocol */␊ |
620 | #define PCI_ERR_UNC_SDES␉␉0x00000020␉/* Surprise Down Error */␊ |
621 | #define PCI_ERR_UNC_POISON_TLP␉0x00001000␉/* Poisoned TLP */␊ |
622 | #define PCI_ERR_UNC_FCP␉␉␉0x00002000␉/* Flow Control Protocol */␊ |
623 | #define PCI_ERR_UNC_COMP_TIME␉0x00004000␉/* Completion Timeout */␊ |
624 | #define PCI_ERR_UNC_COMP_ABORT␉0x00008000␉/* Completer Abort */␊ |
625 | #define PCI_ERR_UNC_UNX_COMP␉0x00010000␉/* Unexpected Completion */␊ |
626 | #define PCI_ERR_UNC_RX_OVER␉␉0x00020000␉/* Receiver Overflow */␊ |
627 | #define PCI_ERR_UNC_MALF_TLP␉0x00040000␉/* Malformed TLP */␊ |
628 | #define PCI_ERR_UNC_ECRC␉␉0x00080000␉/* ECRC Error Status */␊ |
629 | #define PCI_ERR_UNC_UNSUP␉␉0x00100000␉/* Unsupported Request */␊ |
630 | #define PCI_ERR_UNC_ACS_VIOL␉0x00200000␉/* ACS Violation */␊ |
631 | #define PCI_ERR_UNCOR_MASK␉␉8␉␉␉/* Uncorrectable Error Mask */␊ |
632 | /* Same bits as above */␊ |
633 | #define PCI_ERR_UNCOR_SEVER␉␉12␉␉␉/* Uncorrectable Error Severity */␊ |
634 | /* Same bits as above */␊ |
635 | #define PCI_ERR_COR_STATUS␉␉16␉␉␉/* Correctable Error Status */␊ |
636 | #define PCI_ERR_COR_RCVR␉␉0x00000001␉/* Receiver Error Status */␊ |
637 | #define PCI_ERR_COR_BAD_TLP␉␉0x00000040␉/* Bad TLP Status */␊ |
638 | #define PCI_ERR_COR_BAD_DLLP␉0x00000080␉/* Bad DLLP Status */␊ |
639 | #define PCI_ERR_COR_REP_ROLL␉0x00000100␉/* REPLAY_NUM Rollover */␊ |
640 | #define PCI_ERR_COR_REP_TIMER␉0x00001000␉/* Replay Timer Timeout */␊ |
641 | #define PCI_ERR_COR_REP_ANFE␉0x00002000␉/* Advisory Non-Fatal Error */␊ |
642 | #define PCI_ERR_COR_MASK␉␉20␉␉␉/* Correctable Error Mask */␊ |
643 | /* Same bits as above */␊ |
644 | #define PCI_ERR_CAP␉␉␉␉24␉␉␉/* Advanced Error Capabilities */␊ |
645 | #define PCI_ERR_CAP_FEP(x)␉␉((x) & 31)␉/* First Error Pointer */␊ |
646 | #define PCI_ERR_CAP_ECRC_GENC␉0x00000020␉/* ECRC Generation Capable */␊ |
647 | #define PCI_ERR_CAP_ECRC_GENE␉0x00000040␉/* ECRC Generation Enable */␊ |
648 | #define PCI_ERR_CAP_ECRC_CHKC␉0x00000080␉/* ECRC Check Capable */␊ |
649 | #define PCI_ERR_CAP_ECRC_CHKE␉0x00000100␉/* ECRC Check Enable */␊ |
650 | #define PCI_ERR_HEADER_LOG␉␉28␉/* Header Log Register (16 bytes) */␊ |
651 | #define PCI_ERR_ROOT_COMMAND␉44␉/* Root Error Command */␊ |
652 | #define PCI_ERR_ROOT_STATUS␉␉48␊ |
653 | #define PCI_ERR_ROOT_COR_SRC␉52␊ |
654 | #define PCI_ERR_ROOT_SRC␉␉54␊ |
655 | ␊ |
656 | /* Virtual Channel */␊ |
657 | #define PCI_VC_PORT_REG1␉4␊ |
658 | #define PCI_VC_PORT_REG2␉8␊ |
659 | #define PCI_VC_PORT_CTRL␉12␊ |
660 | #define PCI_VC_PORT_STATUS␉14␊ |
661 | #define PCI_VC_RES_CAP␉␉16␊ |
662 | #define PCI_VC_RES_CTRL␉␉20␊ |
663 | #define PCI_VC_RES_STATUS␉26␊ |
664 | ␊ |
665 | /* Power Budgeting */␊ |
666 | #define PCI_PWR_DSR␉␉4␉/* Data Select Register */␊ |
667 | #define PCI_PWR_DATA␉␉8␉/* Data Register */␊ |
668 | #define PCI_PWR_DATA_BASE(x)␉((x) & 0xff)␉ /* Base Power */␊ |
669 | #define PCI_PWR_DATA_SCALE(x)␉(((x) >> 8) & 3) /* Data Scale */␊ |
670 | #define PCI_PWR_DATA_PM_SUB(x)␉(((x) >> 10) & 7) /* PM Sub State */␊ |
671 | #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */␊ |
672 | #define PCI_PWR_DATA_TYPE(x)␉(((x) >> 15) & 7) /* Type */␊ |
673 | #define PCI_PWR_DATA_RAIL(x)␉(((x) >> 18) & 7) /* Power Rail */␊ |
674 | #define PCI_PWR_CAP␉␉12␉/* Capability */␊ |
675 | #define PCI_PWR_CAP_BUDGET(x)␉((x) & 1)␉/* Included in system budget */␊ |
676 | ␊ |
677 | /* Access Control Services */␊ |
678 | #define PCI_ACS_CAP␉␉␉␉0x04␉/* ACS Capability Register */␊ |
679 | #define PCI_ACS_CAP_VALID␉␉0x0001␉/* ACS Source Validation */␊ |
680 | #define PCI_ACS_CAP_BLOCK␉␉0x0002␉/* ACS Translation Blocking */␊ |
681 | #define PCI_ACS_CAP_REQ_RED␉␉0x0004␉/* ACS P2P Request Redirect */␊ |
682 | #define PCI_ACS_CAP_CMPLT_RED␉0x0008␉/* ACS P2P Completion Redirect */␊ |
683 | #define PCI_ACS_CAP_FORWARD␉␉0x0010␉/* ACS Upstream Forwarding */␊ |
684 | #define PCI_ACS_CAP_EGRESS␉␉0x0020␉/* ACS P2P Egress Control */␊ |
685 | #define PCI_ACS_CAP_TRANS␉␉0x0040␉/* ACS Direct Translated P2P */␊ |
686 | #define PCI_ACS_CAP_VECTOR(x)␉(((x) >> 8) & 0xff) /* Egress Control Vector Size */␊ |
687 | #define PCI_ACS_CTRL␉␉␉0x06␉/* ACS Control Register */␊ |
688 | #define PCI_ACS_CTRL_VALID␉␉0x0001␉/* ACS Source Validation Enable */␊ |
689 | #define PCI_ACS_CTRL_BLOCK␉␉0x0002␉/* ACS Translation Blocking Enable */␊ |
690 | #define PCI_ACS_CTRL_REQ_RED␉0x0004␉/* ACS P2P Request Redirect Enable */␊ |
691 | #define PCI_ACS_CTRL_CMPLT_RED␉0x0008␉/* ACS P2P Completion Redirect Enable */␊ |
692 | #define PCI_ACS_CTRL_FORWARD␉0x0010␉/* ACS Upstream Forwarding Enable */␊ |
693 | #define PCI_ACS_CTRL_EGRESS␉␉0x0020␉/* ACS P2P Egress Control Enable */␊ |
694 | #define PCI_ACS_CTRL_TRANS␉␉0x0040␉/* ACS Direct Translated P2P Enable */␊ |
695 | #define PCI_ACS_EGRESS_CTRL␉␉0x08␉/* Egress Control Vector */␊ |
696 | ␊ |
697 | /* Alternative Routing-ID Interpretation */␊ |
698 | #define PCI_ARI_CAP␉␉␉␉0x04␉/* ARI Capability Register */␊ |
699 | #define PCI_ARI_CAP_MFVC␉␉0x0001␉/* MFVC Function Groups Capability */␊ |
700 | #define PCI_ARI_CAP_ACS␉␉␉0x0002␉/* ACS Function Groups Capability */␊ |
701 | #define PCI_ARI_CAP_NFN(x)␉␉(((x) >> 8) & 0xff) /* Next Function Number */␊ |
702 | #define PCI_ARI_CTRL␉␉␉0x06␉/* ARI Control Register */␊ |
703 | #define PCI_ARI_CTRL_MFVC␉␉0x0001␉/* MFVC Function Groups Enable */␊ |
704 | #define PCI_ARI_CTRL_ACS␉␉0x0002␉/* ACS Function Groups Enable */␊ |
705 | #define PCI_ARI_CTRL_FG(x)␉(((x) >> 4) & 7) /* Function Group */␊ |
706 | ␊ |
707 | /* Address Translation Service */␊ |
708 | #define PCI_ATS_CAP␉␉␉␉0x04␉/* ATS Capability Register */␊ |
709 | #define PCI_ATS_CAP_IQD(x)␉((x) & 0x1f) /* Invalidate Queue Depth */␊ |
710 | #define PCI_ATS_CTRL␉␉␉0x06␉/* ATS Control Register */␊ |
711 | #define PCI_ATS_CTRL_STU(x)␉((x) & 0x1f) /* Smallest Translation Unit */␊ |
712 | #define PCI_ATS_CTRL_ENABLE␉0x8000␉/* ATS Enable */␊ |
713 | ␊ |
714 | /* Single Root I/O Virtualization */␊ |
715 | #define PCI_IOV_CAP␉␉0x04␉/* SR-IOV Capability Register */␊ |
716 | #define PCI_IOV_CAP_VFM␉0x00000001 /* VF Migration Capable */␊ |
717 | #define PCI_IOV_CAP_IMN(x)␉((x) >> 21) /* VF Migration Interrupt Message Number */␊ |
718 | #define PCI_IOV_CTRL␉␉0x08␉/* SR-IOV Control Register */␊ |
719 | #define PCI_IOV_CTRL_VFE␉0x0001␉/* VF Enable */␊ |
720 | #define PCI_IOV_CTRL_VFME␉0x0002␉/* VF Migration Enable */␊ |
721 | #define PCI_IOV_CTRL_VFMIE␉0x0004␉/* VF Migration Interrupt Enable */␊ |
722 | #define PCI_IOV_CTRL_MSE␉0x0008␉/* VF MSE */␊ |
723 | #define PCI_IOV_CTRL_ARI␉0x0010␉/* ARI Capable Hierarchy */␊ |
724 | #define PCI_IOV_STATUS␉␉0x0a␉/* SR-IOV Status Register */␊ |
725 | #define PCI_IOV_STATUS_MS␉0x0001␉/* VF Migration Status */␊ |
726 | #define PCI_IOV_INITIALVF␉0x0c␉/* Number of VFs that are initially associated */␊ |
727 | #define PCI_IOV_TOTALVF␉␉0x0e␉/* Maximum number of VFs that could be associated */␊ |
728 | #define PCI_IOV_NUMVF␉␉0x10␉/* Number of VFs that are available */␊ |
729 | #define PCI_IOV_FDL␉␉0x12␉/* Function Dependency Link */␊ |
730 | #define PCI_IOV_OFFSET␉␉0x14␉/* First VF Offset */␊ |
731 | #define PCI_IOV_STRIDE␉␉0x16␉/* Routing ID offset from one VF to the next one */␊ |
732 | #define PCI_IOV_DID␉␉0x1a␉/* VF Device ID */␊ |
733 | #define PCI_IOV_SUPPS␉␉0x1c␉/* Supported Page Sizes */␊ |
734 | #define PCI_IOV_SYSPS␉␉0x20␉/* System Page Size */␊ |
735 | #define PCI_IOV_BAR_BASE␉0x24␉/* VF BAR0, VF BAR1, ... VF BAR5 */␊ |
736 | #define PCI_IOV_NUM_BAR␉␉6␉/* Number of VF BARs */␊ |
737 | #define PCI_IOV_MSAO␉␉0x3c␉/* VF Migration State Array Offset */␊ |
738 | #define PCI_IOV_MSA_BIR(x)␉((x) & 7) /* VF Migration State BIR */␊ |
739 | #define PCI_IOV_MSA_OFFSET(x)␉((x) & 0xfffffff8) /* VF Migration State Offset */␊ |
740 | ␊ |
741 | /*␊ |
742 | * The PCI interface treats multi-function devices as independent␊ |
743 | * devices. The slot/function address of each device is encoded␊ |
744 | * in a single byte as follows:␊ |
745 | *␊ |
746 | *␉7:3 = slot␊ |
747 | *␉2:0 = function␊ |
748 | */␊ |
749 | #define PCI_DEVFN(slot,func)␉((((slot) & 0x1f) << 3) | ((func) & 0x07))␊ |
750 | #define PCI_SLOT(devfn)␉␉(((devfn) >> 3) & 0x1f)␊ |
751 | #define PCI_FUNC(devfn)␉␉((devfn) & 0x07)␊ |
752 | ␊ |
753 | /* Device classes and subclasses */␊ |
754 | ␊ |
755 | #define PCI_CLASS_NOT_DEFINED␉␉0x0000␊ |
756 | #define PCI_CLASS_NOT_DEFINED_VGA␉0x0001␊ |
757 | ␊ |
758 | #define PCI_BASE_CLASS_STORAGE␉␉0x01␊ |
759 | #define PCI_CLASS_STORAGE_SCSI␉␉0x0100␊ |
760 | #define PCI_CLASS_STORAGE_IDE␉␉0x0101␊ |
761 | #define PCI_CLASS_STORAGE_FLOPPY␉0x0102␊ |
762 | #define PCI_CLASS_STORAGE_IPI␉␉0x0103␊ |
763 | #define PCI_CLASS_STORAGE_RAID␉␉0x0104␊ |
764 | #define PCI_CLASS_STORAGE_ATA␉␉0x0105␊ |
765 | #define PCI_CLASS_STORAGE_SATA␉␉0x0106␊ |
766 | #define PCI_CLASS_STORAGE_SAS␉␉0x0107␊ |
767 | #define PCI_CLASS_STORAGE_OTHER␉␉0x0180␊ |
768 | ␊ |
769 | #define PCI_BASE_CLASS_NETWORK␉␉0x02␊ |
770 | #define PCI_CLASS_NETWORK_ETHERNET␉0x0200␊ |
771 | #define PCI_CLASS_NETWORK_TOKEN_RING␉0x0201␊ |
772 | #define PCI_CLASS_NETWORK_FDDI␉␉0x0202␊ |
773 | #define PCI_CLASS_NETWORK_ATM␉␉0x0203␊ |
774 | #define PCI_CLASS_NETWORK_ISDN␉␉0x0204␊ |
775 | #define PCI_CLASS_NETWORK_OTHER␉␉0x0280␊ |
776 | ␊ |
777 | #define PCI_BASE_CLASS_DISPLAY␉␉0x03␊ |
778 | #define PCI_CLASS_DISPLAY_VGA␉␉0x0300␊ |
779 | #define PCI_CLASS_DISPLAY_XGA␉␉0x0301␊ |
780 | #define PCI_CLASS_DISPLAY_3D␉␉0x0302␊ |
781 | #define PCI_CLASS_DISPLAY_OTHER␉␉0x0380␊ |
782 | ␊ |
783 | #define PCI_BASE_CLASS_MULTIMEDIA␉0x04␊ |
784 | #define PCI_CLASS_MULTIMEDIA_VIDEO␉0x0400␊ |
785 | #define PCI_CLASS_MULTIMEDIA_AUDIO␉0x0401␊ |
786 | #define PCI_CLASS_MULTIMEDIA_PHONE␉0x0402␊ |
787 | #define PCI_CLASS_MULTIMEDIA_AUDIO_DEV␉0x0403␊ |
788 | #define PCI_CLASS_MULTIMEDIA_OTHER␉0x0480␊ |
789 | ␊ |
790 | #define PCI_BASE_CLASS_MEMORY␉␉0x05␊ |
791 | #define PCI_CLASS_MEMORY_RAM␉␉0x0500␊ |
792 | #define PCI_CLASS_MEMORY_FLASH␉␉0x0501␊ |
793 | #define PCI_CLASS_MEMORY_OTHER␉␉0x0580␊ |
794 | ␊ |
795 | #define PCI_BASE_CLASS_BRIDGE␉␉0x06␊ |
796 | #define PCI_CLASS_BRIDGE_HOST␉␉0x0600␊ |
797 | #define PCI_CLASS_BRIDGE_ISA␉␉0x0601␊ |
798 | #define PCI_CLASS_BRIDGE_EISA␉␉0x0602␊ |
799 | #define PCI_CLASS_BRIDGE_MC␉␉0x0603␊ |
800 | #define PCI_CLASS_BRIDGE_PCI␉␉0x0604␊ |
801 | #define PCI_CLASS_BRIDGE_PCMCIA␉␉0x0605␊ |
802 | #define PCI_CLASS_BRIDGE_NUBUS␉␉0x0606␊ |
803 | #define PCI_CLASS_BRIDGE_CARDBUS␉0x0607␊ |
804 | #define PCI_CLASS_BRIDGE_RACEWAY␉0x0608␊ |
805 | #define PCI_CLASS_BRIDGE_PCI_SEMI␉0x0609␊ |
806 | #define PCI_CLASS_BRIDGE_IB_TO_PCI␉0x060a␊ |
807 | #define PCI_CLASS_BRIDGE_OTHER␉␉0x0680␊ |
808 | ␊ |
809 | #define PCI_BASE_CLASS_COMMUNICATION␉0x07␊ |
810 | #define PCI_CLASS_COMMUNICATION_SERIAL␉0x0700␊ |
811 | #define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701␊ |
812 | #define PCI_CLASS_COMMUNICATION_MSERIAL␉0x0702␊ |
813 | #define PCI_CLASS_COMMUNICATION_MODEM␉0x0703␊ |
814 | #define PCI_CLASS_COMMUNICATION_OTHER␉0x0780␊ |
815 | ␊ |
816 | #define PCI_BASE_CLASS_SYSTEM␉␉0x08␊ |
817 | #define PCI_CLASS_SYSTEM_PIC␉␉0x0800␊ |
818 | #define PCI_CLASS_SYSTEM_DMA␉␉0x0801␊ |
819 | #define PCI_CLASS_SYSTEM_TIMER␉␉0x0802␊ |
820 | #define PCI_CLASS_SYSTEM_RTC␉␉0x0803␊ |
821 | #define PCI_CLASS_SYSTEM_PCI_HOTPLUG␉0x0804␊ |
822 | #define PCI_CLASS_SYSTEM_OTHER␉␉␉0x0880␊ |
823 | ␊ |
824 | #define PCI_BASE_CLASS_INPUT␉␉␉0x09␊ |
825 | #define PCI_CLASS_INPUT_KEYBOARD␉␉0x0900␊ |
826 | #define PCI_CLASS_INPUT_PEN␉␉␉␉0x0901␊ |
827 | #define PCI_CLASS_INPUT_MOUSE␉␉␉0x0902␊ |
828 | #define PCI_CLASS_INPUT_SCANNER␉␉␉0x0903␊ |
829 | #define PCI_CLASS_INPUT_GAMEPORT␉␉0x0904␊ |
830 | #define PCI_CLASS_INPUT_OTHER␉␉␉0x0980␊ |
831 | ␊ |
832 | #define PCI_BASE_CLASS_DOCKING␉␉␉0x0a␊ |
833 | #define PCI_CLASS_DOCKING_GENERIC␉␉0x0a00␊ |
834 | #define PCI_CLASS_DOCKING_OTHER␉␉␉0x0a80␊ |
835 | ␊ |
836 | #define PCI_BASE_CLASS_PROCESSOR␉␉0x0b␊ |
837 | #define PCI_CLASS_PROCESSOR_386␉␉␉0x0b00␊ |
838 | #define PCI_CLASS_PROCESSOR_486␉␉␉0x0b01␊ |
839 | #define PCI_CLASS_PROCESSOR_PENTIUM␉␉0x0b02␊ |
840 | #define PCI_CLASS_PROCESSOR_ALPHA␉␉0x0b10␊ |
841 | #define PCI_CLASS_PROCESSOR_POWERPC␉␉0x0b20␊ |
842 | #define PCI_CLASS_PROCESSOR_MIPS␉␉0x0b30␊ |
843 | #define PCI_CLASS_PROCESSOR_CO␉␉␉0x0b40␊ |
844 | ␊ |
845 | #define PCI_BASE_CLASS_SERIAL␉␉␉0x0c␊ |
846 | #define PCI_CLASS_SERIAL_FIREWIRE␉␉0x0c00␊ |
847 | #define PCI_CLASS_SERIAL_ACCESS␉␉␉0x0c01␊ |
848 | #define PCI_CLASS_SERIAL_SSA␉␉␉0x0c02␊ |
849 | #define PCI_CLASS_SERIAL_USB␉␉␉0x0c03␊ |
850 | #define PCI_CLASS_SERIAL_FIBER␉␉␉0x0c04␊ |
851 | #define PCI_CLASS_SERIAL_SMBUS␉␉␉0x0c05␊ |
852 | #define PCI_CLASS_SERIAL_INFINIBAND␉␉0x0c06␊ |
853 | ␊ |
854 | #define PCI_BASE_CLASS_WIRELESS␉␉␉0x0d␊ |
855 | #define PCI_CLASS_WIRELESS_IRDA␉␉␉0x0d00␊ |
856 | #define PCI_CLASS_WIRELESS_CONSUMER_IR␉0x0d01␊ |
857 | #define PCI_CLASS_WIRELESS_RF␉␉␉0x0d10␊ |
858 | #define PCI_CLASS_WIRELESS_OTHER␉␉0x0d80␊ |
859 | ␊ |
860 | #define PCI_BASE_CLASS_INTELLIGENT␉␉0x0e␊ |
861 | #define PCI_CLASS_INTELLIGENT_I2O␉␉0x0e00␊ |
862 | ␊ |
863 | #define PCI_BASE_CLASS_SATELLITE␉␉0x0f␊ |
864 | #define PCI_CLASS_SATELLITE_TV␉␉␉0x0f00␊ |
865 | #define PCI_CLASS_SATELLITE_AUDIO␉␉0x0f01␊ |
866 | #define PCI_CLASS_SATELLITE_VOICE␉␉0x0f03␊ |
867 | #define PCI_CLASS_SATELLITE_DATA␉␉0x0f04␊ |
868 | ␊ |
869 | #define PCI_BASE_CLASS_CRYPT␉␉␉0x10␊ |
870 | #define PCI_CLASS_CRYPT_NETWORK␉␉␉0x1000␊ |
871 | #define PCI_CLASS_CRYPT_ENTERTAINMENT␉0x1010␊ |
872 | #define PCI_CLASS_CRYPT_OTHER␉␉␉0x1080␊ |
873 | ␊ |
874 | #define PCI_BASE_CLASS_SIGNAL␉␉␉0x11␊ |
875 | #define PCI_CLASS_SIGNAL_DPIO␉␉␉0x1100␊ |
876 | #define PCI_CLASS_SIGNAL_PERF_CTR␉␉0x1101␊ |
877 | #define PCI_CLASS_SIGNAL_SYNCHRONIZER␉0x1110␊ |
878 | #define PCI_CLASS_SIGNAL_OTHER␉␉␉0x1180␊ |
879 | ␊ |
880 | #define PCI_CLASS_OTHERS␉␉␉␉0xff␊ |
881 | ␊ |
882 | /* Several ID's we need in the library */␊ |
883 | ␊ |
884 | #define PCI_VENDOR_ID_APPLE␉␉␉␉0x106b␊ |
885 | #define PCI_VENDOR_ID_AMD␉␉␉␉0x1002␊ |
886 | #define PCI_VENDOR_ID_ATI␉␉␉␉0x1002␊ |
887 | #define PCI_VENDOR_ID_INTEL␉␉␉␉0x8086␊ |
888 | #define PCI_VENDOR_ID_NVIDIA␉␉␉0x10de␊ |
889 | #define PCI_VENDOR_ID_REALTEK␉␉␉0x10ec␊ |
890 | #define PCI_VENDOR_ID_TEXAS_INSTRUMENTS␉0x104c␊ |
891 | #define PCI_VENDOR_ID_VIA␉␉␉␉0x1106␊ |
892 | ␊ |
893 | #endif /* !__LIBSAIO_PCI_H */␊ |
894 |