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Source at commit 341 created 13 years 8 months ago.
By meklort, Updates module code, dependencies now work correctly. Added KernelPatcher module (currently doesn't hook in anywhere). I need to fix the module loader so that the kernel patcher module loads / starts correctly.
1/*␊
2 * usb.c␊
3 * ␊
4 *␊
5 * Created by mackerintel on 12/20/08.␊
6 * Copyright 2008 mackerintel. All rights reserved.␊
7 *␊
8 */␊
9␊
10#include "libsaio.h"␊
11#include "boot.h"␊
12#include "bootstruct.h"␊
13#include "pci.h"␊
14␊
15#ifndef DEBUG_USB␊
16#define DEBUG_USB 0␊
17#endif␊
18␊
19#if DEBUG_USB␊
20#define DBG(x...)␉printf(x)␊
21#else␊
22#define DBG(x...)␊
23#endif␊
24␊
25␊
26struct pciList␊
27{␊
28␉pci_dt_t* pciDev;␊
29␉struct pciList* next;␊
30};␊
31␊
32struct pciList* usbList = NULL;␊
33␊
34int legacy_off (pci_dt_t *pci_dev);␊
35int ehci_acquire (pci_dt_t *pci_dev);␊
36int uhci_reset (pci_dt_t *pci_dev);␊
37␊
38// Add usb device to the list␊
39void notify_usb_dev(pci_dt_t *pci_dev)␊
40{␊
41␉␊
42␉struct pciList* current = usbList;␊
43␉if(!usbList)␊
44␉{␊
45␉␉usbList = (struct pciList*)malloc(sizeof(struct pciList));␊
46␉␉usbList->next = NULL;␊
47␉␉usbList->pciDev = pci_dev;␊
48␉␉␊
49␉}␊
50␉else␊
51␉{␊
52␉␉while(current != NULL && current->next != NULL)␊
53␉␉{␊
54␉␉␉current = current->next;␊
55␉␉}␊
56␉␉current->next = (struct pciList*)malloc(sizeof(struct pciList));␊
57␉␉current = current->next;␊
58␉␉␊
59␉␉current->pciDev = pci_dev;␊
60␉␉current->next = NULL;␊
61␉}␊
62}␊
63␊
64// Loop through the list and call the apropriate patch function␊
65int usb_loop()␊
66{␊
67␉int retVal = 1;␊
68␉bool fix_ehci, fix_uhci, fix_usb, fix_legacy;␊
69␉fix_ehci = fix_uhci = fix_usb = fix_legacy = true;␊
70␉␊
71␉␊
72␉␊
73␉if (getBoolForKey(kUSBBusFix, &fix_usb, &bootInfo->bootConfig))␊
74␉{␊
75␉␉fix_ehci = fix_uhci = fix_legacy = fix_usb;␉// Enable all if none set␊
76␉}␊
77␉else ␊
78␉{␊
79␉␉getBoolForKey(kEHCIacquire, &fix_ehci, &bootInfo->bootConfig);␊
80␉␉getBoolForKey(kUHCIreset, &fix_uhci, &bootInfo->bootConfig);␊
81␉␉getBoolForKey(kLegacyOff, &fix_legacy, &bootInfo->bootConfig);␊
82␉}␊
83␉␊
84␉␊
85␉struct pciList* current = usbList;␊
86␉␊
87␉while(current && current->next)␊
88␉{␊
89␉␉switch (pci_config_read8(current->pciDev->dev.addr, PCI_CLASS_PROG))␊
90␉␉{␊
91␉␉␉// EHCI␊
92␉␉␉case 0x20:␊
93␉␉ ␉if(fix_ehci) retVal &= ehci_acquire(current->pciDev);␊
94␉␉ ␉if(fix_legacy) retVal &= legacy_off(current->pciDev);␊
95␉␉␉␉␊
96␉␉␉␉break;␊
97␉␉␉␉␊
98␉␉␉// UHCI␊
99␉␉␉case 0x00:␊
100␉␉␉␉if (fix_uhci) retVal &= uhci_reset(current->pciDev);␊
101␉␉␉␉break;␊
102␉␉}␊
103␉␉␊
104␉␉current = current->next;␊
105␉}␊
106␉return retVal;␊
107}␊
108␊
109int legacy_off (pci_dt_t *pci_dev)␊
110{␊
111␉// Set usb legacy off modification by Signal64␊
112␉// NOTE: This *must* be called after the last file is loaded from the drive in the event that we are booting form usb.␊
113␉// NOTE2: This should be called after any getc() call. (aka, after the Wait=y keyworkd is used)␊
114␉// AKA: Make this run immediatly before the kernel is called␊
115␉uint32_t␉capaddr, opaddr; ␉␉␊
116␉uint8_t␉␉eecp;␉␉␉␊
117␉uint32_t␉usbcmd, usbsts, usbintr;␉␉␉␊
118␉uint32_t␉usblegsup, usblegctlsts;␉␉␊
119␉␊
120␉int isOSowned;␊
121␉int isBIOSowned;␊
122␉␊
123␉verbose("Setting Legacy USB Off on controller [%04x:%04x] at %02x:%2x.%x\n", ␊
124␉␉␉pci_dev->vendor_id, pci_dev->device_id,␊
125␉␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func);␊
126␉␊
127␉␊
128␉// capaddr = Capability Registers = dev.addr + offset stored in dev.addr + 0x10 (USBBASE)␊
129␉capaddr = pci_config_read32(pci_dev->dev.addr, 0x10);␉␊
130␉␊
131␉// opaddr = Operational Registers = capaddr + offset (8bit CAPLENGTH in Capability Registers + offset 0)␊
132␉opaddr = capaddr + *((unsigned char*)(capaddr)); ␉␉␊
133␉␊
134␉// eecp = EHCI Extended Capabilities offset = capaddr HCCPARAMS bits 15:8␊
135␉eecp=*((unsigned char*)(capaddr + 9));␊
136␉␊
137␉DBG("capaddr=%x opaddr=%x eecp=%x\n", capaddr, opaddr, eecp);␊
138␉␊
139␉usbcmd = *((unsigned int*)(opaddr));␉␉␉// Command Register␊
140␉usbsts = *((unsigned int*)(opaddr + 4));␉␉// Status Register␊
141␉usbintr = *((unsigned int*)(opaddr + 8));␉␉// Interrupt Enable Register␊
142␉␊
143␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
144␉␊
145␉// read PCI Config 32bit USBLEGSUP (eecp+0) ␊
146␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
147␉␊
148␉// informational only␊
149␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
150␉isOSowned = !!((usblegsup) & (1 << (24)));␊
151␉␊
152␉// read PCI Config 32bit USBLEGCTLSTS (eecp+4) ␊
153␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
154␉␊
155␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
156␉␊
157␉// Reset registers to Legacy OFF␊
158␉DBG("Clearing USBLEGCTLSTS\n");␊
159␉pci_config_write32(pci_dev->dev.addr, eecp + 4, 0);␉//usblegctlsts␊
160␉␊
161␉// if delay value is in milliseconds it doesn't appear to work. ␊
162␉// setting value to anything up to 65535 does not add the expected delay here.␊
163␉delay(100);␊
164␉␊
165␉usbcmd = *((unsigned int*)(opaddr));␊
166␉usbsts = *((unsigned int*)(opaddr + 4));␊
167␉usbintr = *((unsigned int*)(opaddr + 8));␊
168␉␊
169␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
170␉␊
171␉DBG("Clearing Registers\n");␊
172␉␊
173␉// clear registers to default␊
174␉usbcmd = (usbcmd & 0xffffff00);␊
175␉*((unsigned int*)(opaddr)) = usbcmd;␊
176␉*((unsigned int*)(opaddr + 8)) = 0;␉␉␉␉␉//usbintr - clear interrupt registers␊
177␉*((unsigned int*)(opaddr + 4)) = 0x1000;␉␉␉//usbsts - clear status registers ␉␊
178␉pci_config_write32(pci_dev->dev.addr, eecp, 1);␉␉//usblegsup␊
179␉␊
180␉// get the results␊
181␉usbcmd = *((unsigned int*)(opaddr));␊
182␉usbsts = *((unsigned int*)(opaddr + 4));␊
183␉usbintr = *((unsigned int*)(opaddr + 8));␊
184␉␊
185␉DBG("usbcmd=%08x usbsts=%08x usbintr=%08x\n", usbcmd, usbsts, usbintr);␊
186␉␊
187␉// read 32bit USBLEGSUP (eecp+0) ␊
188␉usblegsup = pci_config_read32(pci_dev->dev.addr, eecp);␊
189␉␊
190␉// informational only␊
191␉isBIOSowned = !!((usblegsup) & (1 << (16)));␊
192␉isOSowned = !!((usblegsup) & (1 << (24)));␊
193␉␊
194␉// read 32bit USBLEGCTLSTS (eecp+4) ␊
195␉usblegctlsts = pci_config_read32(pci_dev->dev.addr, eecp + 4);␊
196␉␊
197␉DBG("usblegsup=%08x isOSowned=%d isBIOSowned=%d usblegctlsts=%08x\n", usblegsup, isOSowned, isBIOSowned, usblegctlsts);␊
198␉␊
199␉verbose("Legacy USB Off Done\n");␉␊
200␉return 1;␊
201}␊
202␊
203␊
204␊
205int ehci_acquire (pci_dt_t *pci_dev)␊
206{␊
207␉int␉␉j, k;␊
208␉uint32_t␉base;␊
209␉uint8_t␉␉eecp;␊
210␉uint8_t␉␉legacy[8];␊
211␉bool␉␉isOwnershipConflict;␉␊
212␉bool␉␉alwaysHardBIOSReset;␊
213␊
214␉alwaysHardBIOSReset = false;␉␊
215␉if (!getBoolForKey(kEHCIhard, &alwaysHardBIOSReset, &bootInfo->bootConfig)) {␊
216␉␉alwaysHardBIOSReset = true;␊
217␉}␊
218␊
219␉pci_config_write16(pci_dev->dev.addr, 0x04, 0x0002);␊
220␉base = pci_config_read32(pci_dev->dev.addr, 0x10);␊
221␊
222␉verbose("EHCI controller [%04x:%04x] at %02x:%2x.%x DMA @%x\n", ␊
223␉␉pci_dev->vendor_id, pci_dev->device_id,␊
224␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
225␉␉base);␊
226␊
227␉if (*((unsigned char*)base) < 0xc)␊
228␉{␊
229␉␉DBG("Config space too small: no legacy implementation\n");␊
230␉␉return 1;␊
231␉}␊
232␉eecp = *((unsigned char*)(base + 9));␊
233␉if (!eecp) {␊
234␉␉DBG("No extended capabilities: no legacy implementation\n");␊
235␉␉return 1;␊
236␉}␊
237␊
238␉DBG("eecp=%x\n",eecp);␊
239␊
240␉// bad way to do it␊
241␉// pci_conf_write(pci_dev->dev.addr, eecp, 4, 0x01000001);␊
242␉for (j = 0; j < 8; j++) {␊
243␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
244␉␉DBG("%02x ", legacy[j]);␊
245␉}␊
246␉DBG("\n");␊
247␊
248␉//Real Job: based on orByte's AppleUSBEHCI.cpp␊
249␉//We try soft reset first - some systems hang on reboot with hard reset␊
250␉// Definitely needed during reboot on 10.4.6␊
251␊
252␉isOwnershipConflict = ((legacy[3] & 1 != 0) && (legacy[2] & 1 != 0));␊
253␉if (!alwaysHardBIOSReset && isOwnershipConflict) {␊
254␉␉DBG("EHCI - Ownership conflict - attempting soft reset ...\n");␊
255␉␉DBG("EHCI - toggle OS Ownership to 0\n");␊
256␉␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 0);␊
257␉␉for (k = 0; k < 25; k++) {␊
258␉␉␉for (j = 0; j < 8; j++) {␊
259␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
260␉␉␉}␊
261␉␉␉if (legacy[3] == 0) {␊
262␉␉␉␉break;␊
263␉␉␉}␊
264␉␉␉delay(10);␊
265␉␉}␊
266␉}␉␊
267␊
268␉DBG("Found USBLEGSUP_ID - value %x:%x - writing OSOwned\n", legacy[3],legacy[2]);␊
269␉pci_config_write8(pci_dev->dev.addr, eecp + 3, 1);␊
270␊
271␉// wait for kEHCI_USBLEGSUP_BIOSOwned bit to clear␊
272␉for (k = 0; k < 25; k++) {␊
273␉␉for (j = 0;j < 8; j++) {␊
274␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
275␉␉}␊
276␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
277␉␉if (legacy[2] == 0) {␊
278␉␉␉break;␊
279␉␉}␊
280␉␉delay(10);␊
281␉}␊
282␊
283␉for (j = 0;j < 8; j++) {␊
284␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
285␉}␊
286␉isOwnershipConflict = ((legacy[2]) != 0);␊
287␉if (isOwnershipConflict) {␊
288␉␉// Soft reset has failed. Assume SMI being ignored␊
289␉␉// Hard reset␊
290␉␉// Force Clear BIOS BIT␊
291␉␉DBG("EHCI - Ownership conflict - attempting hard reset ...\n");␉␉␉␊
292␉␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
293␉␉DBG("EHCI - Force BIOS Ownership to 0\n");␊
294␊
295␉␉pci_config_write8(pci_dev->dev.addr, eecp + 2, 0);␊
296␉␉for (k = 0; k < 25; k++) {␊
297␉␉␉for (j = 0; j < 8; j++) {␊
298␉␉␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
299␉␉␉}␊
300␉␉␉DBG ("%x:%x,",legacy[3],legacy[2]);␊
301␊
302␉␉␉if ((legacy[2]) == 0) {␊
303␉␉␉␉break;␊
304␉␉␉}␊
305␉␉␉delay(10);␉␊
306␉␉}␉␉␊
307␉␉// Disable further SMI events␊
308␉␉for (j = 4; j < 8; j++) {␊
309␉␉␉pci_config_write8(pci_dev->dev.addr, eecp + j, 0);␊
310␉␉}␊
311␉}␊
312␊
313␉for (j = 0; j < 8; j++) {␊
314␉␉legacy[j] = pci_config_read8(pci_dev->dev.addr, eecp + j);␊
315␉}␊
316␊
317␉DBG ("%x:%x\n",legacy[3],legacy[2]);␊
318␊
319␉// Final Ownership Resolution Check...␊
320␉if (legacy[2] & 1) {␉␉␉␉␉␊
321␉␉DBG("EHCI controller unable to take control from BIOS\n");␊
322␉␉return 0;␊
323␉}␊
324␊
325␉DBG("EHCI Acquire OS Ownership done\n");␉␊
326␉return 1;␊
327}␊
328␊
329int uhci_reset (pci_dt_t *pci_dev)␊
330{␊
331␉uint32_t base, port_base;␊
332␉␊
333␉base = pci_config_read32(pci_dev->dev.addr, 0x20);␊
334␉port_base = (base >> 5) & 0x07ff;␊
335␊
336␉verbose("UHCI controller [%04x:%04x] at %02x:%2x.%x base %x(%x)\n", ␊
337␉␉pci_dev->vendor_id, pci_dev->device_id,␊
338␉␉pci_dev->dev.bits.bus, pci_dev->dev.bits.dev, pci_dev->dev.bits.func, ␊
339␉␉port_base, base);␊
340␉␊
341␉pci_config_write16(pci_dev->dev.addr, 0xc0, 0x8f00);␊
342␊
343␉outw (port_base, 0x0002);␊
344␉delay(10);␊
345␉outw (port_base+4,0);␊
346␉delay(10);␊
347␉outw (port_base,0);␊
348␉return 1;␊
349}␊
350

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