1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "smbios_getters.h"␊ |
9 | ␊ |
10 | #ifndef DEBUG_SMBIOS␊ |
11 | #define DEBUG_SMBIOS 0␊ |
12 | #endif␊ |
13 | ␊ |
14 | #if DEBUG_SMBIOS␊ |
15 | #define DBG(x...)␉printf(x)␊ |
16 | #else␊ |
17 | #define DBG(x...)␊ |
18 | #endif␊ |
19 | ␊ |
20 | ␊ |
21 | bool getProcessorInformationExternalClock(returnType *value)␊ |
22 | {␊ |
23 | ␉value->word = Platform.CPU.FSBFrequency/1000000;␊ |
24 | ␉return true;␊ |
25 | }␊ |
26 | ␊ |
27 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
28 | {␊ |
29 | ␉value->word = Platform.CPU.CPUFrequency/1000000;␊ |
30 | ␉return true;␊ |
31 | }␊ |
32 | ␊ |
33 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
34 | {␊ |
35 | ␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊ |
36 | ␉{␉␉␊ |
37 | ␉␉switch (Platform.CPU.Family) ␊ |
38 | ␉␉{␊ |
39 | ␉␉␉case 0x06:␊ |
40 | ␉␉␉{␊ |
41 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
42 | ␉␉␉␉{␊ |
43 | ␉␉␉␉␉case 0x0D:␉␉␉␉␉// ?␊ |
44 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊ |
45 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊ |
46 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊ |
47 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊ |
48 | ␉␉␉␉␉␉value->word = 0;␉␉// TODO: populate bus speed for these processors␊ |
49 | ␉␉␉␉␉␉␊ |
50 | //␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊ |
51 | //␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
52 | //␉␉␉␉␉␉␉return 2500;␉␉// Core i5␊ |
53 | //␉␉␉␉␉␉return 4800;␉␉␉// Core i7␊ |
54 | ␉␉␉␉␉␉␊ |
55 | //␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊ |
56 | //␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊ |
57 | //␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊ |
58 | //␉␉␉␉␉␉return 4800;␉␉␉// GT/s / 1000␊ |
59 | //␉␉␉␉␉␉␊ |
60 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
61 | ␉␉␉␉␉␉value->word = 0;␉␉// TODO: populate bus speed for these processors␊ |
62 | ␉␉␉␉␉␉␊ |
63 | //␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
64 | //␉␉␉␉␉␉return 2500;␉␉␉// why? Intel spec says 2.5GT/s ␊ |
65 | ␊ |
66 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
67 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊ |
68 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊ |
69 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊ |
70 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊ |
71 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊ |
72 | ␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
73 | ␉␉␉␉␉{␊ |
74 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
75 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
76 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
77 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
78 | ␉␉␉␉␉␉int i;␊ |
79 | ␉␉␉␉␉␉␊ |
80 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
81 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
82 | ␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊ |
83 | ␉␉␉␉␉␉{␊ |
84 | ␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊ |
85 | ␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊ |
86 | ␉␉␉␉␉␉␉vid &= 0xFFFF;␊ |
87 | ␉␉␉␉␉␉␉did &= 0xFF00;␊ |
88 | ␉␉␉␉␉␉␉␊ |
89 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
90 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊ |
91 | ␉␉␉␉␉␉}␊ |
92 | ␉␉␉␉␉␉␊ |
93 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊ |
94 | ␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊ |
95 | ␉␉␉␉␉␉qpimult &= 0x7F;␊ |
96 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
97 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊ |
98 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
99 | ␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊ |
100 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
101 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
102 | ␉␉␉␉␉}␊ |
103 | ␉␉␉␉}␊ |
104 | ␉␉␉}␊ |
105 | ␉␉}␊ |
106 | ␉}␊ |
107 | ␉value->word = 0;␊ |
108 | ␉return true;␊ |
109 | }␊ |
110 | ␊ |
111 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
112 | {␊ |
113 | ␉if (Platform.CPU.NoCores >= 4) ␊ |
114 | ␉{␊ |
115 | ␉␉return 0x0501;␉// Quad-Core Xeon␊ |
116 | ␉}␊ |
117 | ␉else if (Platform.CPU.NoCores == 1) ␊ |
118 | ␉{␊ |
119 | ␉␉return 0x0201;␉// Core Solo␊ |
120 | ␉};␊ |
121 | ␉␊ |
122 | ␉return 0x0301;␉␉// Core 2 Duo␊ |
123 | }␊ |
124 | ␊ |
125 | bool getSMBOemProcessorType(returnType *value)␊ |
126 | {␊ |
127 | ␉static bool done = false;␉␉␊ |
128 | ␉␉␊ |
129 | ␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊ |
130 | ␉{␊ |
131 | ␉␉if (!done) {␊ |
132 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊ |
133 | ␉␉␉done = true;␊ |
134 | ␉␉}␊ |
135 | ␉␉␊ |
136 | ␉␉switch (Platform.CPU.Family) ␊ |
137 | ␉␉{␊ |
138 | ␉␉␉case 0x06:␊ |
139 | ␉␉␉{␊ |
140 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
141 | ␉␉␉␉{␊ |
142 | ␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ?␊ |
143 | ␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Yonah␊ |
144 | ␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Merom␊ |
145 | ␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Penryn␊ |
146 | ␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊ |
147 | ␉␉␉␉␉␉value->word = simpleGetSMBOemProcessorType();␊ |
148 | ␉␉␉␉␉␉break;␊ |
149 | ␊ |
150 | ␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊ |
151 | ␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
152 | ␉␉␉␉␉␉break;␊ |
153 | ␊ |
154 | ␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊ |
155 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
156 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
157 | ␉␉␉␉␉␉else␊ |
158 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊ |
159 | ␉␉␉␉␉␉break;␊ |
160 | ␊ |
161 | ␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
162 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
163 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊ |
164 | ␉␉␉␉␉␉else␊ |
165 | ␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊ |
166 | ␉␉␉␉␉␉break;␊ |
167 | ␊ |
168 | ␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
169 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊ |
170 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊ |
171 | ␉␉␉␉␉␉else␊ |
172 | ␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊ |
173 | ␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊ |
174 | ␉␉␉␉␉␉␉else␊ |
175 | ␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊ |
176 | ␉␉␉␉␉␉break;␊ |
177 | ␊ |
178 | ␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊ |
179 | ␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊ |
180 | ␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊ |
181 | ␉␉␉␉␉␉break;␊ |
182 | ␊ |
183 | ␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
184 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
185 | ␉␉␉␉␉␉break;␊ |
186 | ␉␉␉␉}␊ |
187 | ␉␉␉}␊ |
188 | ␉␉}␊ |
189 | ␉}␊ |
190 | ␉␊ |
191 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
192 | ␉return true;␊ |
193 | }␊ |
194 | ␊ |
195 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
196 | {␊ |
197 | ␉static int idx = -1;␊ |
198 | ␉int␉map;␊ |
199 | ␊ |
200 | ␉idx++;␊ |
201 | ␉if (idx < MAX_RAM_SLOTS)␊ |
202 | ␉{␊ |
203 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
204 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
205 | ␉␉{␊ |
206 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
207 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
208 | ␉␉␉return true;␊ |
209 | ␉␉}␊ |
210 | ␉}␊ |
211 | ␉␊ |
212 | ␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
213 | ␉return true;␊ |
214 | }␊ |
215 | ␊ |
216 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
217 | {␊ |
218 | ␉static int idx = -1;␊ |
219 | ␉int␉map;␊ |
220 | ␊ |
221 | ␉idx++;␊ |
222 | ␉if (idx < MAX_RAM_SLOTS)␊ |
223 | ␉{␊ |
224 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
225 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
226 | ␉␉{␊ |
227 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
228 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
229 | ␉␉␉return true;␊ |
230 | ␉␉}␊ |
231 | ␉}␊ |
232 | ␊ |
233 | ␉value->dword = 800;␊ |
234 | ␉return true;␊ |
235 | }␊ |
236 | ␊ |
237 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
238 | {␊ |
239 | ␉static int idx = -1;␊ |
240 | ␉int␉map;␊ |
241 | ␊ |
242 | ␉idx++;␊ |
243 | ␉if (idx < MAX_RAM_SLOTS)␊ |
244 | ␉{␊ |
245 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
246 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
247 | ␉␉{␊ |
248 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
249 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
250 | ␉␉␉return true;␊ |
251 | ␉␉}␊ |
252 | ␉}␊ |
253 | ␉value->string = "N/A";␊ |
254 | ␉return true;␊ |
255 | }␊ |
256 | ␉␊ |
257 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
258 | {␊ |
259 | ␉static int idx = -1;␊ |
260 | ␉int␉map;␊ |
261 | ␊ |
262 | ␉idx++;␊ |
263 | ␉if (idx < MAX_RAM_SLOTS)␊ |
264 | ␉{␊ |
265 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
266 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
267 | ␉␉{␊ |
268 | ␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊ |
269 | ␉␉␉␉map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
270 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
271 | ␉␉␉return true;␊ |
272 | ␉␉}␊ |
273 | ␉}␊ |
274 | ␉value->string = "N/A";␊ |
275 | ␉return true;␊ |
276 | }␊ |
277 | ␊ |
278 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
279 | {␊ |
280 | ␉static int idx = -1;␊ |
281 | ␉int␉map;␊ |
282 | ␊ |
283 | ␉idx++;␊ |
284 | ␉if (idx < MAX_RAM_SLOTS)␊ |
285 | ␉{␊ |
286 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
287 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
288 | ␉␉{␊ |
289 | ␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform.RAM.DIMM[map].PartNo);␊ |
290 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
291 | ␉␉␉return true;␊ |
292 | ␉␉}␊ |
293 | ␉}␊ |
294 | ␉value->string = "N/A";␊ |
295 | ␉return true;␊ |
296 | }␊ |
297 | ␊ |
298 | ␊ |
299 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
300 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
301 | static const char * const SMTAG = "_SM_";␊ |
302 | static const char* const DMITAG = "_DMI_";␊ |
303 | ␊ |
304 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
305 | {␊ |
306 | ␉SMBEntryPoint␉*smbios;␊ |
307 | ␉/* ␊ |
308 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
309 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
310 | ␉ */␊ |
311 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
312 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊ |
313 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊ |
314 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
315 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
316 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
317 | ␉ {␊ |
318 | ␉␉␉return smbios;␊ |
319 | ␉ }␊ |
320 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
321 | ␉}␊ |
322 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
323 | ␉pause();␊ |
324 | ␉return NULL;␊ |
325 | }␊ |
326 | ␊ |
327 | |