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1/*␊
2 * Add (c) here␊
3 *␊
4 * Copyright .... All rights reserved.␊
5 *␊
6 */␊
7␊
8#include "smbios_getters.h"␊
9␊
10#ifndef DEBUG_SMBIOS␊
11#define DEBUG_SMBIOS 0␊
12#endif␊
13␊
14#if DEBUG_SMBIOS␊
15#define DBG(x...)␉printf(x)␊
16#else␊
17#define DBG(x...)␊
18#endif␊
19␊
20␊
21bool getProcessorInformationExternalClock(returnType *value)␊
22{␊
23␉value->word = Platform.CPU.FSBFrequency/1000000;␊
24␉return true;␊
25}␊
26␊
27bool getProcessorInformationMaximumClock(returnType *value)␊
28{␊
29␉value->word = Platform.CPU.CPUFrequency/1000000;␊
30␉return true;␊
31}␊
32␊
33bool getSMBOemProcessorBusSpeed(returnType *value)␊
34{␊
35␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
36␉{␉␉␊
37␉␉switch (Platform.CPU.Family) ␊
38␉␉{␊
39␉␉␉case 0x06:␊
40␉␉␉{␊
41␉␉␉␉switch (Platform.CPU.Model)␊
42␉␉␉␉{␊
43␉␉␉␉␉case 0x0D:␉␉␉␉␉// ?␊
44␉␉␉␉␉case CPU_MODEL_YONAH:␉␉// Yonah␉␉0x0E␊
45␉␉␉␉␉case CPU_MODEL_MEROM:␉␉// Merom␉␉0x0F␊
46␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉// Penryn␉␉0x17␊
47␉␉␉␉␉case CPU_MODEL_ATOM:␉␉// Atom 45nm␉0x1C␊
48␉␉␉␉␉␉value->word = 0;␉␉// TODO: populate bus speed for these processors␊
49␉␉␉␉␉␉␊
50//␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
51//␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
52//␉␉␉␉␉␉␉return 2500;␉␉// Core i5␊
53//␉␉␉␉␉␉return 4800;␉␉␉// Core i7␊
54␉␉␉␉␉␉␊
55//␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
56//␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
57//␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
58//␉␉␉␉␉␉return 4800;␉␉␉// GT/s / 1000␊
59//␉␉␉␉␉␉␊
60␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
61␉␉␉␉␉␉value->word = 0;␉␉// TODO: populate bus speed for these processors␊
62␉␉␉␉␉␉␊
63//␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
64//␉␉␉␉␉␉return 2500;␉␉␉// why? Intel spec says 2.5GT/s ␊
65␊
66␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
67␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7 LGA1366 (45nm)␊
68␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7 LGA1156 (45nm)␊
69␉␉␉␉␉case CPU_MODEL_DALES:␉␉// Intel Core i5, i7 LGA1156 (45nm) ???␊
70␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5, i7 LGA1156 (32nm)␊
71␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7 LGA1366 (32nm) 6 Core␊
72␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
73␉␉␉␉␉{␊
74␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊
75␉␉␉␉␉␉int nhm_bus = 0x3F;␊
76␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊
77␉␉␉␉␉␉unsigned long did, vid;␊
78␉␉␉␉␉␉int i;␊
79␉␉␉␉␉␉␊
80␉␉␉␉␉␉// Nehalem supports Scrubbing␊
81␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊
82␉␉␉␉␉␉for(i = 0; i < sizeof(possible_nhm_bus); i++)␊
83␉␉␉␉␉␉{␊
84␉␉␉␉␉␉␉vid = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00);␊
85␉␉␉␉␉␉␉did = pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02);␊
86␉␉␉␉␉␉␉vid &= 0xFFFF;␊
87␉␉␉␉␉␉␉did &= 0xFF00;␊
88␉␉␉␉␉␉␉␊
89␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊
90␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
91␉␉␉␉␉␉}␊
92␉␉␉␉␉␉␊
93␉␉␉␉␉␉unsigned long qpimult, qpibusspeed;␊
94␉␉␉␉␉␉qpimult = pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50);␊
95␉␉␉␉␉␉qpimult &= 0x7F;␊
96␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊
97␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000));␊
98␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊
99␉␉␉␉␉␉if (qpibusspeed%100 != 0)qpibusspeed = ((qpibusspeed+50)/100)*100;␊
100␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊
101␉␉␉␉␉␉value->word = qpibusspeed;␊
102␉␉␉␉␉}␊
103␉␉␉␉}␊
104␉␉␉}␊
105␉␉}␊
106␉}␊
107␉value->word = 0;␊
108␉return true;␊
109}␊
110␊
111uint16_t simpleGetSMBOemProcessorType(void)␊
112{␊
113␉if (Platform.CPU.NoCores >= 4) ␊
114␉{␊
115␉␉return 0x0501;␉// Quad-Core Xeon␊
116␉}␊
117␉else if (Platform.CPU.NoCores == 1) ␊
118␉{␊
119␉␉return 0x0201;␉// Core Solo␊
120␉};␊
121␉␊
122␉return 0x0301;␉␉// Core 2 Duo␊
123}␊
124␊
125bool getSMBOemProcessorType(returnType *value)␊
126{␊
127␉static bool done = false;␉␉␊
128␉␉␊
129␉value->word = simpleGetSMBOemProcessorType();␊
130␊
131␉if (Platform.CPU.Vendor == 0x756E6547) // Intel␊
132␉{␊
133␉␉if (!done)␊
134␉␉{␊
135␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, Platform.CPU.Family, Platform.CPU.Model);␊
136␉␉␉done = true;␊
137␉␉}␊
138␉␉␊
139␉␉switch (Platform.CPU.Family) ␊
140␉␉{␊
141␉␉␉case 0x06:␊
142␉␉␉{␊
143␉␉␉␉switch (Platform.CPU.Model)␊
144␉␉␉␉{␊
145␉␉␉␉␉case 0x0D:␉␉␉␉␉␉␉// ?␊
146␉␉␉␉␉case CPU_MODEL_YONAH:␉␉␉␉// Yonah␊
147␉␉␉␉␉case CPU_MODEL_MEROM:␉␉␉␉// Merom␊
148␉␉␉␉␉case CPU_MODEL_PENRYN:␉␉␉␉// Penryn␊
149␉␉␉␉␉case CPU_MODEL_ATOM:␉␉␉␉// Intel Atom (45nm)␊
150␉␉␉␉␉␉return true;␊
151␊
152␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7 LGA1366 (45nm)␊
153␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
154␉␉␉␉␉␉return true;␊
155␊
156␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉␉// Lynnfield, Clarksfield, Jasper␊
157␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
158␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
159␉␉␉␉␉␉else␊
160␉␉␉␉␉␉␉value->word = 0x701;␉␉// Core i7␊
161␉␉␉␉␉␉return true;␊
162␊
163␉␉␉␉␉case CPU_MODEL_DALES:␉␉␉␉// Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊
164␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
165␉␉␉␉␉␉␉value->word = 0x601;␉␉// Core i5␊
166␉␉␉␉␉␉else␊
167␉␉␉␉␉␉␉value->word = 0x0701;␉␉// Core i7␊
168␉␉␉␉␉␉return true;␊
169␊
170␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5, i7 LGA1156 (32nm) (Clarkdale, Arrandale)␊
171␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
172␉␉␉␉␉␉␉value->word = 0x901;␉␉// Core i3␊
173␉␉␉␉␉␉else␊
174␉␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i5"))␊
175␉␉␉␉␉␉␉␉value->word = 0x601;␉// Core i5␊
176␉␉␉␉␉␉␉else␊
177␉␉␉␉␉␉␉␉value->word = 0x0701;␉// Core i7␊
178␉␉␉␉␉␉return true;␊
179␊
180␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7 LGA1366 (32nm) 6 Core (Gulftown, Westmere-EP, Westmere-WS)␊
181␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Core i7 LGA1366 (45nm) 6 Core ???␊
182␉␉␉␉␉␉value->word = 0x0701;␉␉␉// Core i7␊
183␉␉␉␉␉␉return true;␊
184␊
185␉␉␉␉␉case 0x19:␉␉␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊
186␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊
187␉␉␉␉␉␉return true;␊
188␉␉␉␉}␊
189␉␉␉}␊
190␉␉}␊
191␉}␊
192␉␊
193␉return false;␊
194}␊
195␊
196bool getSMBMemoryDeviceMemoryType(returnType *value)␊
197{␊
198␉static int idx = -1;␊
199␉int␉map;␊
200␊
201␉idx++;␊
202␉if (idx < MAX_RAM_SLOTS)␊
203␉{␊
204␉␉map = Platform.DMI.DIMM[idx];␊
205␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊
206␉␉{␊
207␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊
208␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊
209␉␉␉return true;␊
210␉␉}␊
211␉}␊
212␉␊
213␉return false;␊
214//␉value->byte = SMB_MEM_TYPE_DDR2;␊
215//␉return true;␊
216}␊
217␊
218bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
219{␊
220␉static int idx = -1;␊
221␉int␉map;␊
222␊
223␉idx++;␊
224␉if (idx < MAX_RAM_SLOTS)␊
225␉{␊
226␉␉map = Platform.DMI.DIMM[idx];␊
227␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊
228␉␉{␊
229␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊
230␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊
231␉␉␉return true;␊
232␉␉}␊
233␉}␊
234␊
235␉return false;␊
236//␉value->dword = 800;␊
237//␉return true;␊
238}␊
239␊
240bool getSMBMemoryDeviceManufacturer(returnType *value)␊
241{␊
242␉static int idx = -1;␊
243␉int␉map;␊
244␊
245␉idx++;␊
246␉if (idx < MAX_RAM_SLOTS)␊
247␉{␊
248␉␉map = Platform.DMI.DIMM[idx];␊
249␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊
250␉␉{␊
251␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊
252␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊
253␉␉␉return true;␊
254␉␉}␊
255␉}␊
256␊
257␉return false;␊
258//␉value->string = "N/A";␊
259//␉return true;␊
260}␊
261␉␊
262bool getSMBMemoryDeviceSerialNumber(returnType *value)␊
263{␊
264␉static int idx = -1;␊
265␉int␉map;␊
266␊
267␉idx++;␊
268␉if (idx < MAX_RAM_SLOTS)␊
269␉{␊
270␉␉map = Platform.DMI.DIMM[idx];␊
271␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊
272␉␉{␊
273␉␉␉DBG("name = %s, map=%d, RAM Detected SerialNo[%d]='%s'\n", name ? name : "", ␊
274␉␉␉␉map, idx, Platform.RAM.DIMM[map].SerialNo);␊
275␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊
276␉␉␉return true;␊
277␉␉}␊
278␉}␊
279␊
280␉return false;␊
281//␉value->string = "N/A";␊
282//␉return true;␊
283}␊
284␊
285bool getSMBMemoryDevicePartNumber(returnType *value)␊
286{␊
287␉static int idx = -1;␊
288␉int␉map;␊
289␊
290␉idx++;␊
291␉if (idx < MAX_RAM_SLOTS)␊
292␉{␊
293␉␉map = Platform.DMI.DIMM[idx];␊
294␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊
295␉␉{␊
296␉␉␉DBG("Ram Detected PartNo[%d]='%s'\n", idx, Platform.RAM.DIMM[map].PartNo);␊
297␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊
298␉␉␉return true;␊
299␉␉}␊
300␉}␊
301␊
302␉return false;␊
303//␉value->string = "N/A";␊
304//␉return true;␊
305}␊
306␊
307␊
308// getting smbios addr with fast compare ops, late checksum testing ...␊
309#define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊
310static const char * const SMTAG = "_SM_";␊
311static const char* const DMITAG = "_DMI_";␊
312␊
313SMBEntryPoint *getAddressOfSmbiosTable(void)␊
314{␊
315␉SMBEntryPoint␉*smbios;␊
316␉/* ␊
317␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊
318␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊
319␉ */␊
320␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊
321␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END) {␊
322␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) && ␊
323␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊
324␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊
325␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊
326␉ {␊
327␉␉␉return smbios;␊
328␉ }␊
329␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊
330␉}␊
331␉printf("ERROR: Unable to find SMBIOS!\n");␊
332␉pause();␊
333␉return NULL;␊
334}␊
335␊
336

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