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1/*␊
2 * spd.c - serial presence detect memory information␊
3 *␊
4 * Originally restored from pcefi10.5␊
5 * Dynamic mem detection original impl. by Rekursor␊
6 * System profiler fix and other fixes by Mozodojo.␊
7 */␊
8␊
9#include "libsaio.h"␊
10#include "pci.h"␊
11#include "platform.h"␊
12#include "spd.h"␊
13#include "cpu.h"␊
14#include "saio_internal.h"␊
15#include "bootstruct.h"␊
16#include "memvendors.h"␊
17␊
18#ifndef DEBUG_SPD␊
19#define DEBUG_SPD 0␊
20#endif␊
21␊
22#if DEBUG_SPD␊
23#define DBG(x...)␉printf(x)␊
24#else␊
25#define DBG(x...)␉msglog(x)␊
26#endif␊
27␊
28static const char *spd_memory_types[] =␊
29{␊
30␉"RAM", /* 00h Undefined */␊
31␉"FPM", /* 01h FPM */␊
32␉"EDO", /* 02h EDO */␊
33␉"",␉␉␉␉/* 03h PIPELINE NIBBLE */␊
34␉"SDRAM", /* 04h SDRAM */␊
35␉"",␉␉␉␉/* 05h MULTIPLEXED ROM */␊
36␉"DDR SGRAM",␉/* 06h SGRAM DDR */␊
37␉"DDR SDRAM",␉/* 07h SDRAM DDR */␊
38␉"DDR2 SDRAM", /* 08h SDRAM DDR 2 */␊
39␉"",␉␉␉␉/* 09h Undefined */␊
40␉"",␉␉␉␉/* 0Ah Undefined */␊
41␉"DDR3 SDRAM" /* 0Bh SDRAM DDR 3 */␊
42};␊
43␊
44#define UNKNOWN_MEM_TYPE 2␊
45static uint8_t spd_mem_to_smbios[] =␊
46{␊
47␉UNKNOWN_MEM_TYPE, /* 00h Undefined */␊
48␉UNKNOWN_MEM_TYPE, /* 01h FPM */␊
49␉UNKNOWN_MEM_TYPE, /* 02h EDO */␊
50␉UNKNOWN_MEM_TYPE,␉ /* 03h PIPELINE NIBBLE */␊
51␉SMB_MEM_TYPE_SDRAM, /* 04h SDRAM */␊
52␉SMB_MEM_TYPE_ROM,␉ /* 05h MULTIPLEXED ROM */␊
53␉SMB_MEM_TYPE_SGRAM, /* 06h SGRAM DDR */␊
54␉SMB_MEM_TYPE_DDR, /* 07h SDRAM DDR */␊
55␉SMB_MEM_TYPE_DDR2, /* 08h SDRAM DDR 2 */␊
56␉UNKNOWN_MEM_TYPE, ␉ /* 09h Undefined */␊
57␉UNKNOWN_MEM_TYPE,␉ /* 0Ah Undefined */␊
58␉SMB_MEM_TYPE_DDR3 /* 0Bh SDRAM DDR 3 */␊
59};␊
60#define SPD_TO_SMBIOS_SIZE (sizeof(spd_mem_to_smbios)/sizeof(uint8_t))␊
61␊
62#define rdtsc(low,high) \␊
63__asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))␊
64␊
65#define SMBHSTSTS 0␊
66#define SMBHSTCNT 2␊
67#define SMBHSTCMD 3␊
68#define SMBHSTADD 4␊
69#define SMBHSTDAT 5␊
70#define SBMBLKDAT 7␊
71␊
72/** Read one byte from the intel i2c, used for reading SPD on intel chipsets only. */␊
73unsigned char smb_read_byte_intel(uint32_t base, uint8_t adr, uint8_t cmd)␊
74{␊
75 int l1, h1, l2, h2;␊
76 unsigned long long t;␊
77␉␊
78 outb(base + SMBHSTSTS, 0x1f);␉␉␉␉␉// reset SMBus Controller␊
79 outb(base + SMBHSTDAT, 0xff);␊
80␉␊
81 while( inb(base + SMBHSTSTS) & 0x01);␉␉␉// wait until ready␊
82␉␊
83 outb(base + SMBHSTCMD, cmd);␊
84 outb(base + SMBHSTADD, (adr << 1) | 0x01 );␊
85 outb(base + SMBHSTCNT, 0x48 );␊
86␉␊
87 rdtsc(l1, h1);␊
88␉␊
89 ␉while (!( inb(base + SMBHSTSTS) & 0x02))␉␉// wait til command finished␊
90␉{␉␊
91␉␉rdtsc(l2, h2);␊
92␉␉t = ((h2 - h1) * 0xffffffff + (l2 - l1)) / (Platform.CPU.TSCFrequency / 100);␊
93␉␉if (t > 5)␊
94␉␉␉break;␉␉␉␉␉␉␉␉␉// break after 5ms␊
95 }␊
96 return inb(base + SMBHSTDAT);␊
97}␊
98␊
99/* SPD i2c read optimization: prefetch only what we need, read non prefetcheable bytes on the fly */␊
100#define READ_SPD(spd, base, slot, x) spd[x] = smb_read_byte_intel(base, 0x50 + slot, x)␊
101␊
102int spd_indexes[] = {␊
103␉SPD_MEMORY_TYPE,␊
104␉SPD_DDR3_MEMORY_BANK,␊
105␉SPD_DDR3_MEMORY_CODE,␊
106␉SPD_NUM_ROWS,␊
107␉SPD_NUM_COLUMNS,␊
108␉SPD_NUM_DIMM_BANKS,␊
109␉SPD_NUM_BANKS_PER_SDRAM,␊
110␉4,7,8,9,12,64, /* TODO: give names to these values */␊
111␉95,96,97,98, 122,123,124,125 /* UIS */␊
112};␊
113#define SPD_INDEXES_SIZE (sizeof(spd_indexes) / sizeof(int))␊
114␊
115/** Read from spd *used* values only*/␊
116static void init_spd(char * spd, uint32_t base, int slot)␊
117{␊
118␉int i;␊
119␉for (i=0; i< SPD_INDEXES_SIZE; i++) {␊
120␉␉READ_SPD(spd, base, slot, spd_indexes[i]);␊
121␉}␊
122}␊
123␊
124/** Get Vendor Name from spd, 2 cases handled DDR3 and DDR2, ␊
125 have different formats, always return a valid ptr.*/␊
126const char * getVendorName(RamSlotInfo_t* slot, uint32_t base, int slot_num)␊
127{␊
128 uint8_t bank = 0;␊
129 uint8_t code = 0;␊
130 int i = 0;␊
131 uint8_t * spd = (uint8_t *) slot->spd;␊
132␊
133 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { // DDR3␊
134 bank = (spd[SPD_DDR3_MEMORY_BANK] & 0x07f); // constructors like Patriot use b7=1␊
135 code = spd[SPD_DDR3_MEMORY_CODE];␊
136 for (i=0; i < VEN_MAP_SIZE; i++)␊
137 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
138 return vendorMap[i].name;␊
139 }␊
140 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
141 if(spd[64]==0x7f) {␊
142 for (i=64; i<72 && spd[i]==0x7f;i++) {␊
143␉␉␉ bank++;␊
144␉␉␉ READ_SPD(spd, base, slot_num,i+1); // prefetch next spd byte to read for next loop␊
145␉␉␉}␊
146␉␉␉READ_SPD(spd, base, slot_num,i);␊
147 code = spd[i];␊
148 } else {␊
149 code = spd[64]; ␊
150 bank = 0;␊
151 }␊
152 for (i=0; i < VEN_MAP_SIZE; i++)␊
153 if (bank==vendorMap[i].bank && code==vendorMap[i].code)␊
154 return vendorMap[i].name;␊
155 }␊
156 /* OK there is no vendor id here lets try to match the partnum if it exists */␊
157 if (strstr(slot->PartNo,"GU332") == slot->PartNo) // Unifosa fingerprint␊
158 return "Unifosa";␊
159 return "NoName";␊
160}␊
161␊
162/** Get Default Memory Module Speed (no overclocking handled) */␊
163int getDDRspeedMhz(const char * spd)␊
164{␊
165 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) { ␊
166 switch(spd[12]) {␊
167 case 0x0f:␊
168 return 1066;␊
169 case 0x0c:␊
170 return 1333;␊
171 case 0x0a:␊
172 return 1600;␊
173 case 0x14:␊
174 default:␊
175 return 800;␊
176 }␊
177 } ␊
178 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
179 switch(spd[9]) {␊
180 case 0x50:␊
181 return 400;␊
182 case 0x3d:␊
183 return 533;␊
184 case 0x30:␊
185 return 667;␊
186 case 0x25:␊
187 default:␊
188 return 800;␊
189 }␊
190 }␊
191 return 800; // default freq for unknown types␊
192}␊
193␊
194#define SMST(a) ((uint8_t)((spd[a] & 0xf0) >> 4))␊
195#define SLST(a) ((uint8_t)(spd[a] & 0x0f))␊
196␊
197/** Get DDR3 or DDR2 serial number, 0 most of the times, always return a valid ptr */␊
198const char *getDDRSerial(const char* spd)␊
199{␊
200 static char asciiSerial[16];␊
201 ␊
202 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) // DDR3␊
203 {␊
204␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(122) /*& 0x7*/, SLST(122), SMST(123), SLST(123), SMST(124), SLST(124), SMST(125), SLST(125));␊
205 }␊
206 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) // DDR2 or DDR␊
207 { ␊
208␉sprintf(asciiSerial, "%X%X%X%X%X%X%X%X", SMST(95) /*& 0x7*/, SLST(95), SMST(96), SLST(96), SMST(97), SLST(97), SMST(98), SLST(98));␊
209 }␊
210␊
211 return strdup(asciiSerial);␊
212}␊
213␊
214/** Get DDR3 or DDR2 Part Number, always return a valid ptr */␊
215const char * getDDRPartNum(char* spd, uint32_t base, int slot)␊
216{␊
217␉static char asciiPartNo[32];␊
218␉int i, start=0, index = 0;␊
219␊
220 if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR3) {␊
221␉␉start = 128;␊
222␉}␊
223 else if (spd[SPD_MEMORY_TYPE]==SPD_MEMORY_TYPE_SDRAM_DDR2) {␊
224␉␉start = 73;␊
225␉}␊
226␉␊
227 // Check that the spd part name is zero terminated and that it is ascii:␊
228 bzero(asciiPartNo, sizeof(asciiPartNo));␊
229␉char c;␊
230␉for (i=start; i < start + sizeof(asciiPartNo); i++) {␊
231␉␉READ_SPD(spd, base, slot, i); // only read once the corresponding model part (ddr3 or ddr2)␊
232␉␉c = spd[i];␊
233␉␉if (isalpha(c) || isdigit(c) || ispunct(c)) // It seems that System Profiler likes only letters and digits...␊
234␉␉␉asciiPartNo[index++] = c;␊
235␉␉else if (!isascii(c))␊
236␉␉␉break;␊
237␉}␊
238␉␊
239␉return strdup(asciiPartNo);␊
240 return NULL;␊
241}␊
242␊
243int mapping []= {0,2,1,3,4,6,5,7,8,10,9,11};␊
244␊
245␊
246/** Read from smbus the SPD content and interpret it for detecting memory attributes */␊
247static void read_smb_intel(pci_dt_t *smbus_dev)␊
248{ ␊
249 int i, speed;␊
250 uint8_t spd_size, spd_type;␊
251 uint32_t base;␊
252 bool dump = false;␊
253 RamSlotInfo_t* slot;␊
254␊
255 base = pci_config_read16(smbus_dev->dev.addr, 0x20) & 0xFFFE;␊
256 DBG("Scanning smbus_dev <%04x, %04x> ...\n",smbus_dev->vendor_id, smbus_dev->device_id);␊
257␊
258 getBoolForKey("DumpSPD", &dump, &bootInfo->bootConfig);␊
259 bool fullBanks = // needed at least for laptops␊
260 Platform.DMI.MemoryModules == Platform.DMI.MaxMemorySlots;␊
261 // Search MAX_RAM_SLOTS slots␊
262␉char spdbuf[256];␊
263␊
264 for (i = 0; i < MAX_RAM_SLOTS; i++){␊
265 slot = &Platform.RAM.DIMM[i];␊
266 spd_size = smb_read_byte_intel(base, 0x50 + i, 0);␊
267 // Check spd is present␊
268 if (spd_size && (spd_size != 0xff))␊
269 {␊
270␊
271␉␉␉slot->spd = spdbuf;␊
272 slot->InUse = true;␊
273␊
274 bzero(slot->spd, spd_size);␊
275 ␊
276 // Copy spd data into buffer␊
277 ␊
278␉␉␉//for (x = 0; x < spd_size; x++) slot->spd[x] = smb_read_byte_intel(base, 0x50 + i, x);␊
279 init_spd(slot->spd, base, i);␊
280␉␉␊
281 switch (slot->spd[SPD_MEMORY_TYPE]) {␊
282 case SPD_MEMORY_TYPE_SDRAM_DDR2:␊
283 ␊
284 slot->ModuleSize = ((1 << (slot->spd[SPD_NUM_ROWS] & 0x0f) + (slot->spd[SPD_NUM_COLUMNS] & 0x0f) - 17) * ␊
285 ((slot->spd[SPD_NUM_DIMM_BANKS] & 0x7) + 1) * slot->spd[SPD_NUM_BANKS_PER_SDRAM]);␊
286 break;␊
287 ␊
288 case SPD_MEMORY_TYPE_SDRAM_DDR3:␊
289 ␊
290 slot->ModuleSize = ((slot->spd[4] & 0x0f) + 28 ) + ((slot->spd[8] & 0x7) + 3 );␊
291 slot->ModuleSize -= (slot->spd[7] & 0x7) + 25;␊
292 slot->ModuleSize = ((1 << slot->ModuleSize) * (((slot->spd[7] >> 3) & 0x1f) + 1));␊
293 ␊
294 break;␊
295 }␊
296 ␊
297 spd_type = (slot->spd[SPD_MEMORY_TYPE] < ((char) 12) ? slot->spd[SPD_MEMORY_TYPE] : 0);␊
298 slot->Type = spd_mem_to_smbios[spd_type];␊
299 slot->PartNo = getDDRPartNum(slot->spd, base, i);␊
300 slot->Vendor = getVendorName(slot, base, i);␊
301 slot->SerialNo = getDDRSerial(slot->spd);␊
302␊
303 // determine spd speed␊
304 speed = getDDRspeedMhz(slot->spd);␊
305 if (slot->Frequency<speed) slot->Frequency = speed;␊
306␉␉␉␊
307␉␉␉// pci memory controller if available, is more reliable␊
308␉␉␉if (Platform.RAM.Frequency > 0) {␊
309␉␉␉␉uint32_t freq = (uint32_t)Platform.RAM.Frequency / 500000;␊
310␉␉␉␉// now round off special cases␊
311␉␉␉␉uint32_t fmod100 = freq %100;␊
312␉␉␉␉switch(fmod100) {␊
313␉␉␉␉␉case 1:␉freq--;␉break;␊
314␉␉␉␉␉case 32:␉freq++;␉break;␊
315␉␉␉␉␉case 65:␉freq++; break;␊
316␉␉␉␉␉case 98:␉freq+=2;break;␊
317␉␉␉␉␉case 99:␉freq++; break;␊
318␉␉␉␉}␊
319␉␉␉␉slot->Frequency = freq;␊
320␉␉␉}␊
321␊
322␉␉␉verbose("Slot: %d Type %d %dMB (%s) %dMHz Vendor=%s\n PartNo=%s SerialNo=%s\n", ␊
323 i, ␊
324 (int)slot->Type,␊
325 slot->ModuleSize, ␊
326 spd_memory_types[spd_type],␊
327 slot->Frequency,␊
328 slot->Vendor,␊
329 slot->PartNo,␊
330 slot->SerialNo); ␊
331␊
332#if DEBUG_SPD␊
333 dumpPhysAddr("spd content: ", slot->spd, spd_size);␊
334 getc();␊
335#endif␊
336 }␊
337␊
338 // laptops sometimes show slot 0 and 2 with slot 1 empty when only 2 slots are presents so:␊
339 Platform.DMI.DIMM[i]= ␊
340 i>0 && Platform.RAM.DIMM[1].InUse==false && fullBanks && Platform.DMI.MaxMemorySlots == 2 ? ␊
341 mapping[i] : i; // for laptops case, mapping setup would need to be more generic than this␊
342 ␊
343␉␉slot->spd = NULL;␊
344␊
345 } // for␊
346}␊
347␊
348static struct smbus_controllers_t smbus_controllers[] = {␊
349␊
350␉{0x8086, 0x269B, "ESB2", read_smb_intel },␊
351␉{0x8086, 0x25A4, "6300ESB", read_smb_intel },␊
352␉{0x8086, 0x24C3, "ICH4", read_smb_intel },␊
353␉{0x8086, 0x24D3, "ICH5", read_smb_intel },␊
354␉{0x8086, 0x266A, "ICH6", read_smb_intel },␊
355␉{0x8086, 0x27DA, "ICH7", read_smb_intel },␊
356␉{0x8086, 0x283E, "ICH8", read_smb_intel },␊
357␉{0x8086, 0x2930, "ICH9", read_smb_intel },␉␊
358␉{0x8086, 0x3A30, "ICH10R", read_smb_intel },␊
359␉{0x8086, 0x3A60, "ICH10B", read_smb_intel },␊
360␉{0x8086, 0x3B30, "P55", read_smb_intel },␊
361␉{0x8086, 0x5032, "EP80579", read_smb_intel }␊
362␊
363};␊
364␊
365// initial call : pci_dt = root_pci_dev;␊
366// find_and_read_smbus_controller(root_pci_dev);␊
367bool find_and_read_smbus_controller(pci_dt_t* pci_dt)␊
368{␊
369 pci_dt_t␉*current = pci_dt;␊
370 int i;␊
371␊
372 while (current) {␊
373#if 0␊
374 printf("%02x:%02x.%x [%04x] [%04x:%04x] :: %s\n", ␊
375 current->dev.bits.bus, current->dev.bits.dev, current->dev.bits.func, ␊
376 current->class_id, current->vendor_id, current->device_id, ␊
377 get_pci_dev_path(current));␊
378#endif␊
379␉for ( i = 0; i < sizeof(smbus_controllers) / sizeof(smbus_controllers[0]); i++ )␊
380 {␊
381 if (current->vendor_id == smbus_controllers[i].vendor &&␊
382 current->device_id == smbus_controllers[i].device)␊
383 {␊
384 smbus_controllers[i].read_smb(current); // read smb␊
385 return true;␊
386 } ␊
387 }␊
388 find_and_read_smbus_controller(current->children);␊
389 current = current->next;␊
390 }␊
391 return false; // not found␊
392}␊
393␊
394void scan_spd(PlatformInfo_t *p)␊
395{␊
396 find_and_read_smbus_controller(root_pci_dev);␊
397}␊
398

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