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1/*␊
2 * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊
3 * AsereBLN: 2009: cleanup and bugfix␊
4 */␊
5␊
6#include "libsaio.h"␊
7#include "platform.h"␊
8#include "cpu.h"␊
9␊
10#ifndef DEBUG_CPU␊
11#define DEBUG_CPU 0␊
12#endif␊
13␊
14#if DEBUG_CPU␊
15#define DBG(x...)␉␉printf(x)␊
16#else␊
17#define DBG(x...)␉␉msglog(x)␊
18#endif␊
19␊
20/*␊
21 * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊
22 */␊
23static uint64_t measure_tsc_frequency(void)␊
24{␊
25 uint64_t tscStart;␊
26 uint64_t tscEnd;␊
27 uint64_t tscDelta = 0xffffffffffffffffULL;␊
28 unsigned long pollCount;␊
29 uint64_t retval = 0;␊
30 int i;␊
31␊
32 /* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊
33 * counter 2. We run this loop 3 times to make sure the cache␊
34 * is hot and we take the minimum delta from all of the runs.␊
35 * That is to say that we're biased towards measuring the minimum␊
36 * number of TSC ticks that occur while waiting for the timer to␊
37 * expire. That theoretically helps avoid inconsistencies when␊
38 * running under a VM if the TSC is not virtualized and the host␊
39 * steals time. The TSC is normally virtualized for VMware.␊
40 */␊
41 for(i = 0; i < 10; ++i)␊
42 {␊
43 enable_PIT2();␊
44 set_PIT2_mode0(CALIBRATE_LATCH);␊
45 tscStart = rdtsc64();␊
46 pollCount = poll_PIT2_gate();␊
47 tscEnd = rdtsc64();␊
48 /* The poll loop must have run at least a few times for accuracy */␊
49 if(pollCount <= 1)␊
50 continue;␊
51 /* The TSC must increment at LEAST once every millisecond. We␊
52 * should have waited exactly 30 msec so the TSC delta should␊
53 * be >= 30. Anything less and the processor is way too slow.␊
54 */␊
55 if((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC)␊
56 continue;␊
57 // tscDelta = min(tscDelta, (tscEnd - tscStart))␊
58 if( (tscEnd - tscStart) < tscDelta )␊
59 tscDelta = tscEnd - tscStart;␊
60 }␊
61 /* tscDelta is now the least number of TSC ticks the processor made in␊
62 * a timespan of 0.03 s (e.g. 30 milliseconds)␊
63 * Linux thus divides by 30 which gives the answer in kiloHertz because␊
64 * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊
65 * Hz so we need to convert our milliseconds to seconds. Since we're␊
66 * dividing by the milliseconds, we simply multiply by 1000.␊
67 */␊
68␊
69 /* Unlike linux, we're not limited to 32-bit, but we do need to take care␊
70 * that we're going to multiply by 1000 first so we do need at least some␊
71 * arithmetic headroom. For now, 32-bit should be enough.␊
72 * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊
73 */␊
74 if(tscDelta > (1ULL<<32))␊
75 retval = 0;␊
76 else␊
77 {␊
78 retval = tscDelta * 1000 / 30;␊
79 }␊
80 disable_PIT2();␊
81 return retval;␊
82}␊
83␊
84/*␊
85 * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊
86 * - multi. is read from a specific MSR. In the case of Intel, there is:␊
87 * a max multi. (used to calculate the FSB freq.),␊
88 * and a current multi. (used to calculate the CPU freq.)␊
89 * - fsbFrequency = tscFrequency / multi␊
90 * - cpuFrequency = fsbFrequency * multi␊
91 */␊
92␊
93void scan_cpu(PlatformInfo_t *p)␊
94{␊
95␉uint64_t␉tscFrequency, fsbFrequency, cpuFrequency;␊
96␉uint64_t␉msr, flex_ratio;␊
97␉uint8_t␉␉maxcoef, maxdiv, currcoef, currdiv;␊
98␉␊
99␉maxcoef = maxdiv = currcoef = currdiv = 0;␊
100␊
101␉/* get cpuid values */␊
102␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]);␊
103␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]);␊
104␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]);␊
105␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]);␊
106␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊
107␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊
108␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1) {␊
109␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊
110␉}␊
111␊
112#if DEBUG_CPU␊
113␉{␊
114␉␉int␉␉i;␊
115␉␉printf("CPUID Raw Values:\n");␊
116␉␉for (i=0; i<CPUID_MAX; i++) {␊
117␉␉␉printf("%02d: %08x-%08x-%08x-%08x\n", i,␊
118␉␉␉␉p->CPU.CPUID[i][0], p->CPU.CPUID[i][1],␊
119␉␉␉␉p->CPU.CPUID[i][2], p->CPU.CPUID[i][3]);␊
120␉␉}␊
121␉}␊
122#endif␊
123␉p->CPU.Vendor␉␉= p->CPU.CPUID[CPUID_0][1];␊
124␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊
125␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊
126␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊
127␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊
128␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊
129␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊
130␉␊
131␉p->CPU.Model += (p->CPU.ExtModel << 4);␊
132␊
133␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && (p->CPU.Family == 0x06) && (p->CPU.Model >= 0x1a)){␊
134␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
135␉␉␉p->CPU.NoCores␉␉= bitfield((uint32_t)msr, 31, 16);␉␉␉␉␉// Using undocumented MSR to get actual values␊
136␉␉␉p->CPU.NoThreads␉= bitfield((uint32_t)msr, 15, 0);␉␉␉␉␉// Using undocumented MSR to get actual values␊
137␉} else {␊
138␉␉␉p->CPU.NoThreads␉= bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␉␉// Use previous method for Cores and Threads␊
139␉␉␉p->CPU.NoCores␉␉= bitfield(p->CPU.CPUID[CPUID_4][0], 31, 26) + 1;␊
140␉}␊
141␉␉␉␉␉␉␉␉␉␉␉␉␉ ␉␉␊
142␉/* get brand string (if supported) */␊
143␉/* Copyright: from Apple's XNU cpuid.c */␊
144␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004) {␊
145␉␉uint32_t␉reg[4];␊
146 char str[128], *s;␊
147␉␉/*␊
148␉␉ * The brand string 48 bytes (max), guaranteed to␊
149␉␉ * be NUL terminated.␊
150␉␉ */␊
151␉␉do_cpuid(0x80000002, reg);␊
152␉␉bcopy((char *)reg, &str[0], 16);␊
153␉␉do_cpuid(0x80000003, reg);␊
154␉␉bcopy((char *)reg, &str[16], 16);␊
155␉␉do_cpuid(0x80000004, reg);␊
156␉␉bcopy((char *)reg, &str[32], 16);␊
157␉␉for (s = str; *s != '\0'; s++) {␊
158␉␉␉if (*s != ' ') break;␊
159␉␉}␊
160␉␉␊
161␉␉strlcpy(p->CPU.BrandString,␉s, sizeof(p->CPU.BrandString));␊
162␉␉␊
163␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, min(sizeof(p->CPU.BrandString), strlen(CPU_STRING_UNKNOWN) + 1))) {␊
164␉␉␉ /*␊
165␉␉␉ * This string means we have a firmware-programmable brand string,␊
166␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊
167␉␉␉ */␊
168␉␉␉ p->CPU.BrandString[0] = '\0';␊
169␉␉ }␊
170␉}␊
171␊
172␉/* setup features */␊
173␉p->CPU.Features |= (CPU_FEATURE_MMX | CPU_FEATURE_SSE | CPU_FEATURE_SSE2 | CPU_FEATURE_MSR | CPU_FEATURE_APIC | CPU_FEATURE_TM1 | CPU_FEATURE_ACPI) & p->CPU.CPUID[CPUID_1][3];␊
174␉p->CPU.Features |= (CPU_FEATURE_SSE3 | CPU_FEATURE_SSE41 | CPU_FEATURE_SSE42 | CPU_FEATURE_EST | CPU_FEATURE_TM2 | CPU_FEATURE_SSSE3 | CPU_FEATURE_xAPIC) & p->CPU.CPUID[CPUID_1][2];␊
175␉p->CPU.Features |= (CPU_FEATURE_EM64T | CPU_FEATURE_XD) & p->CPU.CPUID[CPUID_81][3];␊
176␉p->CPU.Features |= (CPU_FEATURE_LAHF) & p->CPU.CPUID[CPUID_81][2];␊
177␉if (p->CPU.NoThreads > p->CPU.NoCores) {␊
178␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊
179␉}␊
180␊
181␉tscFrequency = measure_tsc_frequency();␊
182␉fsbFrequency = 0;␊
183␉cpuFrequency = 0;␊
184␊
185␉if ((p->CPU.Vendor == 0x756E6547 /* Intel */) && ((p->CPU.Family == 0x06) || (p->CPU.Family == 0x0f))) {␊
186␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)) {␊
187␉␉␉/* Nehalem CPU model */␊
188␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM || p->CPU.Model == CPU_MODEL_FIELDS ␊
189␉␉␉ || p->CPU.Model == CPU_MODEL_DALES || p->CPU.Model == CPU_MODEL_DALES_32NM || p->CPU.Model == CPU_MODEL_SANDY_BRIDGE ␊
190␉␉␉ || p->CPU.Model == CPU_MODEL_WESTMERE || p->CPU.Model == CPU_MODEL_NEHALEM_EX)) {␊
191␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
192␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, msr & 0xffffffff);␊
193␉␉␉␉currcoef = (msr >> 8) & 0xff;␊
194␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
195␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, msr & 0xffffffff);␊
196␉␉␉␉if ((msr >> 16) & 0x01) {␊
197␉␉␉␉␉flex_ratio = (msr >> 8) & 0xff;␊
198␉␉␉␉␉if (currcoef > flex_ratio) {␊
199␉␉␉␉␉␉currcoef = flex_ratio;␊
200␉␉␉␉␉}␊
201␉␉␉␉}␊
202␊
203␉␉␉␉if (currcoef) {␊
204␉␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
205␉␉␉␉}␊
206␉␉␉␉cpuFrequency = tscFrequency;␊
207␉␉␉} else {␊
208␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊
209␉␉␉␉DBG("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, msr & 0xffffffff);␊
210␉␉␉␉currcoef = (msr >> 8) & 0x1f;␊
211␉␉␉␉/* Non-integer bus ratio for the max-multi*/␊
212␉␉␉␉maxdiv = (msr >> 46) & 0x01;␊
213␉␉␉␉/* Non-integer bus ratio for the current-multi (undocumented)*/␊
214␉␉␉␉currdiv = (msr >> 14) & 0x01;␊
215␊
216␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f)) // This will always be model >= 3␊
217␉␉␉␉{␊
218␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊
219␉␉␉␉␉maxcoef = (msr >> 40) & 0x1f;␊
220␉␉␉␉} else {␊
221␉␉␉␉␉/* On lower models, currcoef defines TSC freq */␊
222␉␉␉␉␉/* XXX */␊
223␉␉␉␉␉maxcoef = currcoef;␊
224␉␉␉␉}␊
225␊
226␉␉␉␉if (maxcoef) {␊
227␉␉␉␉␉if (maxdiv) {␊
228␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊
229␉␉␉␉␉} else {␊
230␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊
231␉␉␉␉␉}␊
232␉␉␉␉␉if (currdiv) {␊
233␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊
234␉␉␉␉␉} else {␊
235␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊
236␉␉␉␉␉}␊
237␉␉␉␉␉DBG("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊
238␉␉␉␉}␊
239␉␉␉}␊
240␉␉}␊
241␉␉/* Mobile CPU */␊
242␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28)) { ␊
243␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊
244␉␉}␊
245␉}␊
246#if 0␊
247␉else if((p->CPU.Vendor == 0x68747541 /* AMD */) && (p->CPU.Family == 0x0f)) {␊
248␉␉if(p->CPU.ExtFamily == 0x00 /* K8 */) {␊
249␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊
250␉␉␉currcoef = (msr & 0x3f) / 2 + 4;␊
251␉␉␉currdiv = (msr & 0x01) * 2;␊
252␉␉} else if(p->CPU.ExtFamily >= 0x01 /* K10+ */) {␊
253␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊
254␉␉␉if(p->CPU.ExtFamily == 0x01 /* K10 */)␊
255␉␉␉␉currcoef = (msr & 0x3f) + 0x10;␊
256␉␉␉else /* K11+ */␊
257␉␉␉␉currcoef = (msr & 0x3f) + 0x08;␊
258␉␉␉currdiv = (2 << ((msr >> 6) & 0x07));␊
259␉␉}␊
260␊
261␉␉if (currcoef) {␊
262␉␉␉if (currdiv) {␊
263␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊
264␉␉␉␉DBG("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊
265␉␉␉} else {␊
266␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
267␉␉␉␉DBG("%d\n", currcoef);␊
268␉␉␉}␊
269␉␉␉fsbFrequency = (tscFrequency / currcoef);␊
270␉␉␉cpuFrequency = tscFrequency;␊
271␉␉}␊
272␉}␊
273␊
274␉if (!fsbFrequency) {␊
275␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊
276␉␉cpuFrequency = tscFrequency;␊
277␉␉DBG("0 ! using the default value for FSB !\n");␊
278␉}␊
279#endif␊
280␊
281␉p->CPU.MaxCoef = maxcoef;␊
282␉p->CPU.MaxDiv = maxdiv;␊
283␉p->CPU.CurrCoef = currcoef;␊
284␉p->CPU.CurrDiv = currdiv;␊
285␉p->CPU.TSCFrequency = tscFrequency;␊
286␉p->CPU.FSBFrequency = fsbFrequency;␊
287␉p->CPU.CPUFrequency = cpuFrequency;␊
288␊
289␉DBG("CPU: Brand String: %s\n",␉␉␉␉p->CPU.BrandString);␊
290␉DBG("CPU: Vendor/Family/ExtFamily: 0x%x/0x%x/0x%x\n",␉p->CPU.Vendor, p->CPU.Family, p->CPU.ExtFamily);␊
291␉DBG("CPU: Model/ExtModel/Stepping: 0x%x/0x%x/0x%x\n",␉p->CPU.Model, p->CPU.ExtModel, p->CPU.Stepping);␊
292␉DBG("CPU: MaxCoef/CurrCoef: 0x%x/0x%x\n",␉␉p->CPU.MaxCoef, p->CPU.CurrCoef);␊
293␉DBG("CPU: MaxDiv/CurrDiv: 0x%x/0x%x\n",␉␉p->CPU.MaxDiv, p->CPU.CurrDiv);␊
294␉DBG("CPU: TSCFreq: %dMHz\n",␉␉␉p->CPU.TSCFrequency / 1000000);␊
295␉DBG("CPU: FSBFreq: %dMHz\n",␉␉␉p->CPU.FSBFrequency / 1000000);␊
296␉DBG("CPU: CPUFreq: %dMHz\n",␉␉␉p->CPU.CPUFrequency / 1000000);␊
297␉DBG("CPU: NoCores/NoThreads: %d/%d\n",␉␉␉p->CPU.NoCores, p->CPU.NoThreads);␊
298␉DBG("CPU: Features: 0x%08x\n",␉␉␉p->CPU.Features);␊
299#if DEBUG_CPU␊
300␉pause();␊
301#endif␊
302}␊
303

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