1 | /*␊ |
2 | *␉NVidia injector␊ |
3 | *␊ |
4 | *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊ |
5 | *␊ |
6 | *␉NVidia injector is free software: you can redistribute it and/or modify␊ |
7 | *␉it under the terms of the GNU General Public License as published by␊ |
8 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
9 | *␉(at your option) any later version.␊ |
10 | *␊ |
11 | *␉NVidia driver and injector is distributed in the hope that it will be useful,␊ |
12 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
13 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
14 | *␉GNU General Public License for more details.␊ |
15 | *␊ |
16 | *␉You should have received a copy of the GNU General Public License␊ |
17 | *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊ |
18 | */ ␊ |
19 | /*␊ |
20 | * Alternatively you can choose to comply with APSL␊ |
21 | */␊ |
22 | ␊ |
23 | ␊ |
24 | /*␊ |
25 | * DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊ |
26 | *␊ |
27 | *␊ |
28 | * Copyright 2005-2006 Erik Waling␊ |
29 | * Copyright 2006 Stephane Marchesin␊ |
30 | * Copyright 2007-2009 Stuart Bennett␊ |
31 | *␊ |
32 | * Permission is hereby granted, free of charge, to any person obtaining a␊ |
33 | * copy of this software and associated documentation files (the "Software"),␊ |
34 | * to deal in the Software without restriction, including without limitation␊ |
35 | * the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
36 | * and/or sell copies of the Software, and to permit persons to whom the␊ |
37 | * Software is furnished to do so, subject to the following conditions:␊ |
38 | *␊ |
39 | * The above copyright notice and this permission notice shall be included in␊ |
40 | * all copies or substantial portions of the Software.␊ |
41 | *␊ |
42 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊ |
43 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊ |
44 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊ |
45 | * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊ |
46 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊ |
47 | * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊ |
48 | * SOFTWARE.␊ |
49 | */␊ |
50 | ␊ |
51 | #include "libsa.h"␊ |
52 | #include "saio_internal.h"␊ |
53 | #include "bootstruct.h"␊ |
54 | #include "pci.h"␊ |
55 | #include "platform.h"␊ |
56 | #include "device_inject.h"␊ |
57 | #include "nvidia.h"␊ |
58 | ␊ |
59 | #ifndef DEBUG_NVIDIA␊ |
60 | #define DEBUG_NVIDIA 0␊ |
61 | #endif␊ |
62 | ␊ |
63 | #if DEBUG_NVIDIA␊ |
64 | #define DBG(x...)␉printf(x)␊ |
65 | #else␊ |
66 | #define DBG(x...)␊ |
67 | #endif␊ |
68 | ␊ |
69 | #define kUseNvidiaROM␉␉␉␉"UseNvidiaROM"␊ |
70 | #define kVBIOS␉␉␉␉␉␉"VBIOS"␊ |
71 | ␊ |
72 | #define NVIDIA_ROM_SIZE␉␉␉␉0x10000␊ |
73 | #define PATCH_ROM_SUCCESS␉␉␉1␊ |
74 | #define PATCH_ROM_SUCCESS_HAS_LVDS␉2␊ |
75 | #define PATCH_ROM_FAILED␉␉␉0␊ |
76 | #define MAX_NUM_DCB_ENTRIES␉␉␉16␊ |
77 | #define TYPE_GROUPED␉␉␉␉0xff␊ |
78 | ␊ |
79 | extern uint32_t devices_number;␊ |
80 | ␊ |
81 | const char *nvidia_compatible_0[]␉=␉{ "@0,compatible",␉"NVDA,NVMac"␉ };␊ |
82 | const char *nvidia_compatible_1[]␉=␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊ |
83 | const char *nvidia_device_type_0[]␉=␉{ "@0,device_type", "display"␉␉ };␊ |
84 | const char *nvidia_device_type_1[]␉=␉{ "@1,device_type", "display"␉␉ };␊ |
85 | const char *nvidia_device_type[]␉=␉{ "device_type",␉"NVDA,Parent"␉ };␊ |
86 | const char *nvidia_name_0[]␉␉␉=␉{ "@0,name",␉␉"NVDA,Display-A" };␊ |
87 | const char *nvidia_name_1[]␉␉␉=␉{ "@1,name",␉␉"NVDA,Display-B" };␊ |
88 | const char *nvidia_slot_name[]␉␉=␉{ "AAPL,slot-name", "Slot-1"␉␉ };␊ |
89 | ␊ |
90 | static uint8_t default_NVCAP[]= {␊ |
91 | ␉0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,␊ |
92 | ␉0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,␊ |
93 | ␉0x00, 0x00, 0x00, 0x00␊ |
94 | };␊ |
95 | ␊ |
96 | #define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )␊ |
97 | ␊ |
98 | static struct nv_chipsets_t NVKnownChipsets[] = {␊ |
99 | ␉{ 0x00000000, "Unknown" },␊ |
100 | ␉// 0040 - 004F␉␊ |
101 | ␉{ 0x10DE0040, "GeForce 6800 Ultra" },␊ |
102 | ␉{ 0x10DE0041, "GeForce 6800" },␊ |
103 | ␉{ 0x10DE0042, "GeForce 6800 LE" },␊ |
104 | ␉{ 0x10DE0043, "GeForce 6800 XE" },␊ |
105 | ␉{ 0x10DE0044, "GeForce 6800 XT" },␊ |
106 | ␉{ 0x10DE0045, "GeForce 6800 GT" },␊ |
107 | ␉{ 0x10DE0046, "GeForce 6800 GT" },␊ |
108 | ␉{ 0x10DE0047, "GeForce 6800 GS" },␊ |
109 | ␉{ 0x10DE0048, "GeForce 6800 XT" },␊ |
110 | ␉{ 0x10DE004D, "Quadro FX 3400" },␊ |
111 | ␉{ 0x10DE004E, "Quadro FX 4000" },␊ |
112 | ␉// 0050 - 005F␊ |
113 | ␉// 0060 - 006F␉␊ |
114 | ␉// 0070 - 007F␉␊ |
115 | ␉// 0080 - 008F␉␊ |
116 | ␉// 0090 - 009F␉␊ |
117 | ␉{ 0x10DE0090, "GeForce 7800 GTX" },␊ |
118 | ␉{ 0x10DE0091, "GeForce 7800 GTX" },␊ |
119 | ␉{ 0x10DE0092, "GeForce 7800 GT" },␊ |
120 | ␉{ 0x10DE0093, "GeForce 7800 GS" },␊ |
121 | ␉{ 0x10DE0095, "GeForce 7800 SLI" },␊ |
122 | ␉{ 0x10DE0098, "GeForce Go 7800" },␊ |
123 | ␉{ 0x10DE0099, "GeForce Go 7800 GTX" },␊ |
124 | ␉{ 0x10DE009D, "Quadro FX 4500" },␊ |
125 | ␉// 00A0 - 00AF␉␊ |
126 | ␉// 00B0 - 00BF␉␊ |
127 | ␉// 00C0 - 00CF␉␊ |
128 | ␉{ 0x10DE00C0, "GeForce 6800 GS" },␊ |
129 | ␉{ 0x10DE00C1, "GeForce 6800" },␊ |
130 | ␉{ 0x10DE00C2, "GeForce 6800 LE" },␊ |
131 | ␉{ 0x10DE00C3, "GeForce 6800 XT" },␊ |
132 | ␉{ 0x10DE00C8, "GeForce Go 6800" },␊ |
133 | ␉{ 0x10DE00C9, "GeForce Go 6800 Ultra" },␊ |
134 | ␉{ 0x10DE00CC, "Quadro FX Go1400" },␊ |
135 | ␉{ 0x10DE00CD, "Quadro FX 3450/4000 SDI" },␊ |
136 | ␉{ 0x10DE00CE, "Quadro FX 1400" },␊ |
137 | ␉// 00D0 - 00DF␉␊ |
138 | ␉// 00E0 - 00EF␉␊ |
139 | ␉// 00F0 - 00FF␉␊ |
140 | ␉{ 0x10DE00F1, "GeForce 6600 GT" },␊ |
141 | ␉{ 0x10DE00F2, "GeForce 6600" },␊ |
142 | ␉{ 0x10DE00F3, "GeForce 6200" },␊ |
143 | ␉{ 0x10DE00F4, "GeForce 6600 LE" },␊ |
144 | ␉{ 0x10DE00F5, "GeForce 7800 GS" },␊ |
145 | ␉{ 0x10DE00F6, "GeForce 6800 GS/XT" },␊ |
146 | ␉{ 0x10DE00F8, "Quadro FX 3400/4400" },␊ |
147 | ␉{ 0x10DE00F9, "GeForce 6800 Series GPU" },␊ |
148 | ␉// 0100 - 010F␉␊ |
149 | ␉// 0110 - 011F␉␊ |
150 | ␉// 0120 - 012F␉␊ |
151 | ␉// 0130 - 013F␉␊ |
152 | ␉// 0140 - 014F␉␊ |
153 | ␉{ 0x10DE0140, "GeForce 6600 GT" },␊ |
154 | ␉{ 0x10DE0141, "GeForce 6600" },␊ |
155 | ␉{ 0x10DE0142, "GeForce 6600 LE" },␊ |
156 | ␉{ 0x10DE0143, "GeForce 6600 VE" },␊ |
157 | ␉{ 0x10DE0144, "GeForce Go 6600" },␊ |
158 | ␉{ 0x10DE0145, "GeForce 6610 XL" },␊ |
159 | ␉{ 0x10DE0146, "GeForce Go 6600 TE/6200 TE" },␊ |
160 | ␉{ 0x10DE0147, "GeForce 6700 XL" },␊ |
161 | ␉{ 0x10DE0148, "GeForce Go 6600" },␊ |
162 | ␉{ 0x10DE0149, "GeForce Go 6600 GT" },␊ |
163 | ␉{ 0x10DE014A, "Quadro NVS 440" },␊ |
164 | ␉{ 0x10DE014C, "Quadro FX 550" },␊ |
165 | ␉{ 0x10DE014D, "Quadro FX 550" },␊ |
166 | ␉{ 0x10DE014E, "Quadro FX 540" },␊ |
167 | ␉{ 0x10DE014F, "GeForce 6200" },␊ |
168 | ␉// 0150 - 015F␉␊ |
169 | ␉// 0160 - 016F␉␊ |
170 | ␉{ 0x10DE0160, "GeForce 6500" },␊ |
171 | ␉{ 0x10DE0161, "GeForce 6200 TurboCache(TM)" },␊ |
172 | ␉{ 0x10DE0162, "GeForce 6200SE TurboCache(TM)" },␊ |
173 | ␉{ 0x10DE0163, "GeForce 6200 LE" },␊ |
174 | ␉{ 0x10DE0164, "GeForce Go 6200" },␊ |
175 | ␉{ 0x10DE0165, "Quadro NVS 285" },␊ |
176 | ␉{ 0x10DE0166, "GeForce Go 6400" },␊ |
177 | ␉{ 0x10DE0167, "GeForce Go 6200" },␊ |
178 | ␉{ 0x10DE0168, "GeForce Go 6400" },␊ |
179 | ␉{ 0x10DE0169, "GeForce 6250" },␊ |
180 | ␉{ 0x10DE016A, "GeForce 7100 GS" },␊ |
181 | ␉// 0170 - 017F␉␊ |
182 | ␉// 0180 - 018F␉␊ |
183 | ␉// 0190 - 019F␉␉␊ |
184 | ␉{ 0x10DE0191, "GeForce 8800 GTX" },␊ |
185 | ␉{ 0x10DE0193, "GeForce 8800 GTS" },␊ |
186 | ␉{ 0x10DE0194, "GeForce 8800 Ultra" },␊ |
187 | ␉{ 0x10DE0197, "Tesla C870" },␊ |
188 | ␉{ 0x10DE019D, "Quadro FX 5600" },␊ |
189 | ␉{ 0x10DE019E, "Quadro FX 4600" },␊ |
190 | ␉// 01A0 - 01AF␉␊ |
191 | ␉// 01B0 - 01BF␉␊ |
192 | ␉// 01C0 - 01CF␉␊ |
193 | ␉// 01D0 - 01DF␉␉␊ |
194 | ␉{ 0x10DE01D0, "GeForce 7350 LE" },␊ |
195 | ␉{ 0x10DE01D1, "GeForce 7300 LE" },␊ |
196 | ␉{ 0x10DE01D2, "GeForce 7550 LE" },␊ |
197 | ␉{ 0x10DE01D3, "GeForce 7300 SE/7200 GS" },␊ |
198 | ␉{ 0x10DE01D6, "GeForce Go 7200" },␊ |
199 | ␉{ 0x10DE01D7, "GeForce Go 7300" },␊ |
200 | ␉{ 0x10DE01D8, "GeForce Go 7400" },␊ |
201 | ␉{ 0x10DE01D9, "GeForce Go 7400 GS" },␊ |
202 | ␉{ 0x10DE01DA, "Quadro NVS 110M" },␊ |
203 | ␉{ 0x10DE01DB, "Quadro NVS 120M" },␊ |
204 | ␉{ 0x10DE01DC, "Quadro FX 350M" },␊ |
205 | ␉{ 0x10DE01DD, "GeForce 7500 LE" },␊ |
206 | ␉{ 0x10DE01DE, "Quadro FX 350" },␊ |
207 | ␉{ 0x10DE01DF, "GeForce 7300 GS" },␊ |
208 | ␉// 01E0 - 01EF␉␊ |
209 | ␉// 01F0 - 01FF␊ |
210 | ␉// 0200 - 020F␉␊ |
211 | ␉// 0210 - 021F␉␊ |
212 | ␉{ 0x10DE0211, "GeForce 6800" },␊ |
213 | ␉{ 0x10DE0212, "GeForce 6800 LE" },␊ |
214 | ␉{ 0x10DE0215, "GeForce 6800 GT" },␊ |
215 | ␉{ 0x10DE0218, "GeForce 6800 XT" },␊ |
216 | ␉// 0220 - 022F␉␊ |
217 | ␉{ 0x10DE0221, "GeForce 6200" },␊ |
218 | ␉{ 0x10DE0222, "GeForce 6200 A-LE" },␊ |
219 | ␉// 0230 - 023F␉␊ |
220 | ␉// 0240 - 024F␉␊ |
221 | ␉{ 0x10DE0240, "GeForce 6150" },␊ |
222 | ␉{ 0x10DE0241, "GeForce 6150 LE" },␊ |
223 | ␉{ 0x10DE0242, "GeForce 6100" },␊ |
224 | ␉{ 0x10DE0244, "GeForce Go 6150" },␊ |
225 | ␉{ 0x10DE0245, "Quadro NVS 210S / GeForce 6150LE" },␊ |
226 | ␉{ 0x10DE0247, "GeForce Go 6100" },␊ |
227 | ␉// 0250 - 025F␉␊ |
228 | ␉// 0260 - 026F␉␊ |
229 | ␉// 0270 - 027F␉␊ |
230 | ␉// 0280 - 028F␉␉␊ |
231 | ␉// 0290 - 029F␉␊ |
232 | ␉{ 0x10DE0290, "GeForce 7900 GTX" },␊ |
233 | ␉{ 0x10DE0291, "GeForce 7900 GT/GTO" },␊ |
234 | ␉{ 0x10DE0292, "GeForce 7900 GS" },␊ |
235 | ␉{ 0x10DE0293, "GeForce 7950 GX2" },␊ |
236 | ␉{ 0x10DE0294, "GeForce 7950 GX2" },␊ |
237 | ␉{ 0x10DE0295, "GeForce 7950 GT" },␊ |
238 | ␉{ 0x10DE0298, "GeForce Go 7900 GS" },␊ |
239 | ␉{ 0x10DE0299, "GeForce Go 7900 GTX" },␊ |
240 | ␉{ 0x10DE029A, "Quadro FX 2500M" },␊ |
241 | ␉{ 0x10DE029B, "Quadro FX 1500M" },␊ |
242 | ␉{ 0x10DE029C, "Quadro FX 5500" },␊ |
243 | ␉{ 0x10DE029D, "Quadro FX 3500" },␊ |
244 | ␉{ 0x10DE029E, "Quadro FX 1500" },␊ |
245 | ␉{ 0x10DE029F, "Quadro FX 4500 X2" },␊ |
246 | ␉// 02A0 - 02AF␉␊ |
247 | ␉// 02B0 - 02BF␉␊ |
248 | ␉// 02C0 - 02CF␉␊ |
249 | ␉// 02D0 - 02DF␉␉␊ |
250 | ␉// 02E0 - 02EF␉␉␊ |
251 | ␉{ 0x10DE02E0, "GeForce 7600 GT" },␊ |
252 | ␉{ 0x10DE02E1, "GeForce 7600 GS" },␊ |
253 | ␉{ 0x10DE02E2, "GeForce 7300 GT" },␊ |
254 | ␉{ 0x10DE02E3, "GeForce 7900 GS" },␊ |
255 | ␉{ 0x10DE02E4, "GeForce 7950 GT" },␊ |
256 | ␉// 02F0 - 02FF␉␉␊ |
257 | ␉// 0300 - 030F␉␉␊ |
258 | ␉{ 0x10DE0301, "GeForce FX 5800 Ultra" },␊ |
259 | ␉{ 0x10DE0302, "GeForce FX 5800" },␊ |
260 | ␉{ 0x10DE0308, "Quadro FX 2000" },␊ |
261 | ␉{ 0x10DE0309, "Quadro FX 1000" },␊ |
262 | ␉// 0310 - 031F␉␉␊ |
263 | ␉{ 0x10DE0311, "GeForce FX 5600 Ultra" },␊ |
264 | ␉{ 0x10DE0312, "GeForce FX 5600" },␊ |
265 | ␉{ 0x10DE0314, "GeForce FX 5600XT" },␊ |
266 | ␉{ 0x10DE031A, "GeForce FX Go5600" },␊ |
267 | ␉{ 0x10DE031B, "GeForce FX Go5650" },␊ |
268 | ␉{ 0x10DE031C, "Quadro FX Go700" },␊ |
269 | ␉// 0320 - 032F␉␉␊ |
270 | ␉{ 0x10DE0324, "GeForce FX Go5200" },␊ |
271 | ␉{ 0x10DE0325, "GeForce FX Go5250" },␊ |
272 | ␉{ 0x10DE0326, "GeForce FX 5500" },␊ |
273 | ␉{ 0x10DE0328, "GeForce FX Go5200 32M/64M" },␊ |
274 | ␉{ 0x10DE032A, "Quadro NVS 55/280 PCI" },␊ |
275 | ␉{ 0x10DE032B, "Quadro FX 500/600 PCI" },␊ |
276 | ␉{ 0x10DE032C, "GeForce FX Go53xx Series" },␊ |
277 | ␉{ 0x10DE032D, "GeForce FX Go5100" },␊ |
278 | ␉// 0330 - 033F␊ |
279 | ␉{ 0x10DE0330, "GeForce FX 5900 Ultra" },␊ |
280 | ␉{ 0x10DE0331, "GeForce FX 5900" },␊ |
281 | ␉{ 0x10DE0332, "GeForce FX 5900XT" },␊ |
282 | ␉{ 0x10DE0333, "GeForce FX 5950 Ultra" },␊ |
283 | ␉{ 0x10DE0334, "GeForce FX 5900ZT" },␊ |
284 | ␉{ 0x10DE0338, "Quadro FX 3000" },␊ |
285 | ␉{ 0x10DE033F, "Quadro FX 700" },␊ |
286 | ␉// 0340 - 034F␊ |
287 | ␉{ 0x10DE0341, "GeForce FX 5700 Ultra" },␊ |
288 | ␉{ 0x10DE0342, "GeForce FX 5700" },␊ |
289 | ␉{ 0x10DE0343, "GeForce FX 5700LE" },␊ |
290 | ␉{ 0x10DE0344, "GeForce FX 5700VE" },␊ |
291 | ␉{ 0x10DE0347, "GeForce FX Go5700" },␊ |
292 | ␉{ 0x10DE0348, "GeForce FX Go5700" },␊ |
293 | ␉{ 0x10DE034C, "Quadro FX Go1000" },␊ |
294 | ␉{ 0x10DE034E, "Quadro FX 1100" },␊ |
295 | ␉// 0350 - 035F␉␊ |
296 | ␉// 0360 - 036F␉␊ |
297 | ␉// 0370 - 037F␉␊ |
298 | ␉// 0380 - 038F␉␉␉␊ |
299 | ␉{ 0x10DE038B, "GeForce 7650 GS" },␊ |
300 | ␉// 0390 - 039F␊ |
301 | ␉{ 0x10DE0390, "GeForce 7650 GS" },␊ |
302 | ␉{ 0x10DE0391, "GeForce 7600 GT" },␊ |
303 | ␉{ 0x10DE0392, "GeForce 7600 GS" },␊ |
304 | ␉{ 0x10DE0393, "GeForce 7300 GT" },␊ |
305 | ␉{ 0x10DE0394, "GeForce 7600 LE" },␊ |
306 | ␉{ 0x10DE0395, "GeForce 7300 GT" },␊ |
307 | ␉{ 0x10DE0397, "GeForce Go 7700" },␊ |
308 | ␉{ 0x10DE0398, "GeForce Go 7600" },␊ |
309 | ␉{ 0x10DE0399, "GeForce Go 7600 GT"},␊ |
310 | ␉{ 0x10DE039A, "Quadro NVS 300M" },␊ |
311 | ␉{ 0x10DE039B, "GeForce Go 7900 SE" },␊ |
312 | ␉{ 0x10DE039C, "Quadro FX 550M" },␊ |
313 | ␉{ 0x10DE039E, "Quadro FX 560" },␊ |
314 | ␉// 03A0 - 03AF␉␊ |
315 | ␉// 03B0 - 03BF␉␊ |
316 | ␉// 03C0 - 03CF␉␊ |
317 | ␉// 03D0 - 03DF␉␉␉␊ |
318 | ␉{ 0x10DE03D0, "GeForce 6150SE nForce 430" },␊ |
319 | ␉{ 0x10DE03D1, "GeForce 6100 nForce 405" },␊ |
320 | ␉{ 0x10DE03D2, "GeForce 6100 nForce 400" },␊ |
321 | ␉{ 0x10DE03D5, "GeForce 6100 nForce 420" },␊ |
322 | ␉{ 0x10DE03D6, "GeForce 7025 / nForce 630a" },␊ |
323 | ␉// 03E0 - 03EF␊ |
324 | ␉// 03F0 - 03FF␊ |
325 | ␉// 0400 - 040F␉␉␊ |
326 | ␉{ 0x10DE0400, "GeForce 8600 GTS" },␊ |
327 | ␉{ 0x10DE0401, "GeForce 8600 GT" },␊ |
328 | ␉{ 0x10DE0402, "GeForce 8600 GT" },␊ |
329 | ␉{ 0x10DE0403, "GeForce 8600 GS" },␊ |
330 | ␉{ 0x10DE0404, "GeForce 8400 GS" },␊ |
331 | ␉{ 0x10DE0405, "GeForce 9500M GS" },␊ |
332 | ␉{ 0x10DE0406, "GeForce 8300 GS" },␊ |
333 | ␉{ 0x10DE0407, "GeForce 8600M GT" },␊ |
334 | ␉{ 0x10DE0408, "GeForce 9650M GS" },␊ |
335 | ␉{ 0x10DE0409, "GeForce 8700M GT" },␊ |
336 | ␉{ 0x10DE040A, "Quadro FX 370" },␊ |
337 | ␉{ 0x10DE040B, "Quadro NVS 320M" },␊ |
338 | ␉{ 0x10DE040C, "Quadro FX 570M" },␊ |
339 | ␉{ 0x10DE040D, "Quadro FX 1600M" },␊ |
340 | ␉{ 0x10DE040E, "Quadro FX 570" },␊ |
341 | ␉{ 0x10DE040F, "Quadro FX 1700" },␊ |
342 | ␉// 0410 - 041F␉␊ |
343 | ␉{ 0x10DE0410, "GeForce GT 330" },␊ |
344 | ␉// 0420 - 042F␉␊ |
345 | ␉{ 0x10DE0420, "GeForce 8400 SE" },␊ |
346 | ␉{ 0x10DE0421, "GeForce 8500 GT" },␊ |
347 | ␉{ 0x10DE0422, "GeForce 8400 GS" },␊ |
348 | ␉{ 0x10DE0423, "GeForce 8300 GS" },␊ |
349 | ␉{ 0x10DE0424, "GeForce 8400 GS" },␊ |
350 | ␉{ 0x10DE0425, "GeForce 8600M GS" },␊ |
351 | ␉{ 0x10DE0426, "GeForce 8400M GT" },␊ |
352 | ␉{ 0x10DE0427, "GeForce 8400M GS" },␊ |
353 | ␉{ 0x10DE0428, "GeForce 8400M G" },␊ |
354 | ␉{ 0x10DE0429, "Quadro NVS 140M" },␊ |
355 | ␉{ 0x10DE042A, "Quadro NVS 130M" },␊ |
356 | ␉{ 0x10DE042B, "Quadro NVS 135M" },␊ |
357 | ␉{ 0x10DE042C, "GeForce 9400 GT" },␊ |
358 | ␉{ 0x10DE042D, "Quadro FX 360M" },␊ |
359 | ␉{ 0x10DE042E, "GeForce 9300M G" },␊ |
360 | ␉{ 0x10DE042F, "Quadro NVS 290" },␊ |
361 | ␉// 0430 - 043F␊ |
362 | ␉// 0440 - 044F␊ |
363 | ␉// 0450 - 045F␊ |
364 | ␉// 0460 - 046F␊ |
365 | ␉// 0470 - 047F␊ |
366 | ␉// 0480 - 048F␊ |
367 | ␉// 0490 - 049F␊ |
368 | ␉// 04A0 - 04AF␊ |
369 | ␉// 04B0 - 04BF␊ |
370 | ␉// 04C0 - 04CF␊ |
371 | ␉// 04D0 - 04DF␊ |
372 | ␉// 04E0 - 04EF␊ |
373 | ␉// 04F0 - 04FF␊ |
374 | ␉// 0500 - 050F␉␊ |
375 | ␉// 0510 - 051F␉␊ |
376 | ␉// 0520 - 052F␉␊ |
377 | ␉// 0530 - 053F␉␊ |
378 | ␉{ 0x10DE053A, "GeForce 7050 PV / nForce 630a" },␊ |
379 | ␉{ 0x10DE053B, "GeForce 7050 PV / nForce 630a" },␊ |
380 | ␉{ 0x10DE053E, "GeForce 7025 / nForce 630a" },␊ |
381 | ␉// 0540 - 054F␊ |
382 | ␉// 0550 - 055F␊ |
383 | ␉// 0560 - 056F␊ |
384 | ␉// 0570 - 057F␊ |
385 | ␉// 0580 - 058F␊ |
386 | ␉// 0590 - 059F␊ |
387 | ␉// 05A0 - 05AF␊ |
388 | ␉// 05B0 - 05BF␊ |
389 | ␉// 05C0 - 05CF␊ |
390 | ␉// 05D0 - 05DF␊ |
391 | ␉// 05E0 - 05EF␉␊ |
392 | ␉{ 0x10DE05E0, "GeForce GTX 295" },␊ |
393 | ␉{ 0x10DE05E1, "GeForce GTX 280" },␊ |
394 | ␉{ 0x10DE05E2, "GeForce GTX 260" },␊ |
395 | ␉{ 0x10DE05E3, "GeForce GTX 285" },␊ |
396 | ␉{ 0x10DE05E6, "GeForce GTX 275" },␊ |
397 | ␉{ 0x10DE05EA, "GeForce GTX 260" },␊ |
398 | ␉{ 0x10DE05EB, "GeForce GTX 295" },␊ |
399 | ␉{ 0x10DE05ED, "Quadroplex 2200 D2" },␊ |
400 | ␉// 05F0 - 05FF␉␉␊ |
401 | ␉{ 0x10DE05F8, "Quadroplex 2200 S4" },␊ |
402 | ␉{ 0x10DE05F9, "Quadro CX" },␊ |
403 | ␉{ 0x10DE05FD, "Quadro FX 5800" },␊ |
404 | ␉{ 0x10DE05FE, "Quadro FX 4800" },␊ |
405 | ␉{ 0x10DE05FF, "Quadro FX 3800" },␊ |
406 | ␉// 0600 - 060F␉␊ |
407 | ␉{ 0x10DE0600, "GeForce 8800 GTS 512" },␊ |
408 | ␉{ 0x10DE0601, "GeForce 9800 GT" },␊ |
409 | ␉{ 0x10DE0602, "GeForce 8800 GT" },␊ |
410 | ␉{ 0x10DE0603, "GeForce GT 230" },␊ |
411 | ␉{ 0x10DE0604, "GeForce 9800 GX2" },␊ |
412 | ␉{ 0x10DE0605, "GeForce 9800 GT" },␊ |
413 | ␉{ 0x10DE0606, "GeForce 8800 GS" },␊ |
414 | ␉{ 0x10DE0607, "GeForce GTS 240" },␊ |
415 | ␉{ 0x10DE0608, "GeForce 9800M GTX" },␊ |
416 | ␉{ 0x10DE0609, "GeForce 8800M GTS" },␊ |
417 | ␉{ 0x10DE060A, "GeForce GTX 280M" },␊ |
418 | ␉{ 0x10DE060B, "GeForce 9800M GT" },␊ |
419 | ␉{ 0x10DE060C, "GeForce 8800M GTX" },␊ |
420 | ␉{ 0x10DE060D, "GeForce 8800 GS" },␊ |
421 | ␉{ 0x10DE060F, "GeForce GTX 285M" },␊ |
422 | ␉// 0610 - 061F␉␊ |
423 | ␉{ 0x10DE0610, "GeForce 9600 GSO" },␊ |
424 | ␉{ 0x10DE0611, "GeForce 8800 GT" },␊ |
425 | ␉{ 0x10DE0612, "GeForce 9800 GTX" },␊ |
426 | ␉{ 0x10DE0613, "GeForce 9800 GTX+" },␊ |
427 | ␉{ 0x10DE0614, "GeForce 9800 GT" },␊ |
428 | ␉{ 0x10DE0615, "GeForce GTS 250" },␊ |
429 | ␉{ 0x10DE0617, "GeForce 9800M GTX" },␊ |
430 | ␉{ 0x10DE0618, "GeForce GTX 260M" },␊ |
431 | ␉{ 0x10DE0619, "Quadro FX 4700 X2" },␊ |
432 | ␉{ 0x10DE061A, "Quadro FX 3700" },␊ |
433 | ␉{ 0x10DE061B, "Quadro VX 200" },␊ |
434 | ␉{ 0x10DE061C, "Quadro FX 3600M" },␊ |
435 | ␉{ 0x10DE061D, "Quadro FX 2800M" },␊ |
436 | ␉{ 0x10DE061F, "Quadro FX 3800M" },␊ |
437 | ␉// 0620 - 062F␉␊ |
438 | ␉{ 0x10DE0622, "GeForce 9600 GT" },␊ |
439 | ␉{ 0x10DE0623, "GeForce 9600 GS" },␊ |
440 | ␉{ 0x10DE0625, "GeForce 9600 GSO 512"},␊ |
441 | ␉{ 0x10DE0626, "GeForce GT 130" },␊ |
442 | ␉{ 0x10DE0627, "GeForce GT 140" },␊ |
443 | ␉{ 0x10DE0628, "GeForce 9800M GTS" },␊ |
444 | ␉{ 0x10DE062A, "GeForce 9700M GTS" },␊ |
445 | ␉{ 0x10DE062C, "GeForce 9800M GTS" },␊ |
446 | ␉{ 0x10DE062D, "GeForce 9600 GT" },␊ |
447 | ␉{ 0x10DE062E, "GeForce 9600 GT" },␊ |
448 | ␉// 0630 - 063F␉␊ |
449 | ␉{ 0x10DE0631, "GeForce GTS 160M" },␊ |
450 | ␉{ 0x10DE0632, "GeForce GTS 150M" },␊ |
451 | ␉{ 0x10DE0635, "GeForce 9600 GSO" },␊ |
452 | ␉{ 0x10DE0637, "GeForce 9600 GT" },␊ |
453 | ␉{ 0x10DE0638, "Quadro FX 1800" },␊ |
454 | ␉{ 0x10DE063A, "Quadro FX 2700M" },␊ |
455 | ␉// 0640 - 064F␉␊ |
456 | ␉{ 0x10DE0640, "GeForce 9500 GT" },␊ |
457 | ␉{ 0x10DE0641, "GeForce 9400 GT" },␊ |
458 | ␉{ 0x10DE0642, "GeForce 8400 GS" },␊ |
459 | ␉{ 0x10DE0643, "GeForce 9500 GT" },␊ |
460 | ␉{ 0x10DE0644, "GeForce 9500 GS" },␊ |
461 | ␉{ 0x10DE0645, "GeForce 9500 GS" },␊ |
462 | ␉{ 0x10DE0646, "GeForce GT 120" },␊ |
463 | ␉{ 0x10DE0647, "GeForce 9600M GT" },␊ |
464 | ␉{ 0x10DE0648, "GeForce 9600M GS" },␊ |
465 | ␉{ 0x10DE0649, "GeForce 9600M GT" },␊ |
466 | ␉{ 0x10DE064A, "GeForce 9700M GT" },␊ |
467 | ␉{ 0x10DE064B, "GeForce 9500M G" },␊ |
468 | ␉{ 0x10DE064C, "GeForce 9650M GT" },␊ |
469 | ␉// 0650 - 065F␉␉␊ |
470 | ␉{ 0x10DE0651, "GeForce G 110M" },␊ |
471 | ␉{ 0x10DE0652, "GeForce GT 130M" },␊ |
472 | ␉{ 0x10DE0653, "GeForce GT 120M" },␊ |
473 | ␉{ 0x10DE0654, "GeForce GT 220M" },␊ |
474 | ␉{ 0x10DE0656, "GeForce 9650 S" },␊ |
475 | ␉{ 0x10DE0658, "Quadro FX 380" },␊ |
476 | ␉{ 0x10DE0659, "Quadro FX 580" },␊ |
477 | ␉{ 0x10DE065A, "Quadro FX 1700M" },␊ |
478 | ␉{ 0x10DE065B, "GeForce 9400 GT" },␊ |
479 | ␉{ 0x10DE065C, "Quadro FX 770M" },␊ |
480 | ␉{ 0x10DE065F, "GeForce G210" },␊ |
481 | ␉// 0660 - 066F␊ |
482 | ␉// 0670 - 067F␊ |
483 | ␉// 0680 - 068F␊ |
484 | ␉// 0690 - 069F␊ |
485 | ␉// 06A0 - 06AF␊ |
486 | ␉// 06B0 - 06BF␊ |
487 | ␉// 06C0 - 06CF␊ |
488 | ␉{ 0x10DE06C0, "GeForce GTX 480" },␊ |
489 | ␉{ 0x10DE06C3, "GeForce GTX D12U" },␊ |
490 | ␉{ 0x10DE06C4, "GeForce GTX 465" },␊ |
491 | ␉{ 0x10DE06CA, "GeForce GTX 480M" },␊ |
492 | ␉{ 0x10DE06CD, "GeForce GTX 470" },␊ |
493 | ␉// 06D0 - 06DF␊ |
494 | ␉{ 0x10DE06D1, "Tesla C2050" },␉// TODO: sub-device id: 0x0771␊ |
495 | ␉{ 0x10DE06D1, "Tesla C2070" },␉// TODO: sub-device id: 0x0772␊ |
496 | ␉{ 0x10DE06D2, "Tesla M2070" },␊ |
497 | ␉{ 0x10DE06D8, "Quadro 6000" },␊ |
498 | ␉{ 0x10DE06D9, "Quadro 5000" },␊ |
499 | ␉{ 0x10DE06DA, "Quadro 5000M" },␊ |
500 | ␉{ 0x10DE06DC, "Quadro 6000" },␊ |
501 | ␉{ 0x10DE06DD, "Quadro 4000" },␊ |
502 | ␉{ 0x10DE06DE, "Tesla M2050" },␉// TODO: sub-device id: 0x0846␊ |
503 | ␉{ 0x10DE06DE, "Tesla M2070" },␉// TODO: sub-device id: ?␉␊ |
504 | ␉// 0x10DE06DE also applies to misc S2050, X2070, M2050, M2070␊ |
505 | ␉// 06E0 - 06EF␉␊ |
506 | ␉{ 0x10DE06E0, "GeForce 9300 GE" },␊ |
507 | ␉{ 0x10DE06E1, "GeForce 9300 GS" },␊ |
508 | ␉{ 0x10DE06E2, "GeForce 8400" },␊ |
509 | ␉{ 0x10DE06E3, "GeForce 8400 SE" },␊ |
510 | ␉{ 0x10DE06E4, "GeForce 8400 GS" },␊ |
511 | ␉{ 0x10DE06E5, "GeForce 9300M GS" },␊ |
512 | ␉{ 0x10DE06E6, "GeForce G100" },␊ |
513 | ␉{ 0x10DE06E7, "GeForce 9300 SE" },␊ |
514 | ␉{ 0x10DE06E8, "GeForce 9200M GS" },␊ |
515 | ␉{ 0x10DE06E9, "GeForce 9300M GS" },␊ |
516 | ␉{ 0x10DE06EA, "Quadro NVS 150M" },␊ |
517 | ␉{ 0x10DE06EB, "Quadro NVS 160M" },␊ |
518 | ␉{ 0x10DE06EC, "GeForce G 105M" },␊ |
519 | ␉{ 0x10DE06EF, "GeForce G 103M" },␊ |
520 | ␉// 06F0 - 06FF␉␊ |
521 | ␉{ 0x10DE06F8, "Quadro NVS 420" },␊ |
522 | ␉{ 0x10DE06F9, "Quadro FX 370 LP" },␊ |
523 | ␉{ 0x10DE06FA, "Quadro NVS 450" },␊ |
524 | ␉{ 0x10DE06FB, "Quadro FX 370M" },␊ |
525 | ␉{ 0x10DE06FD, "Quadro NVS 295" },␊ |
526 | ␉// 0700 - 070F␊ |
527 | ␉// 0710 - 071F␊ |
528 | ␉// 0720 - 072F␊ |
529 | ␉// 0730 - 073F␊ |
530 | ␉// 0740 - 074F␊ |
531 | ␉// 0750 - 075F␊ |
532 | ␉// 0760 - 076F␊ |
533 | ␉// 0770 - 077F␊ |
534 | ␉// 0780 - 078F␊ |
535 | ␉// 0790 - 079F␊ |
536 | ␉// 07A0 - 07AF␊ |
537 | ␉// 07B0 - 07BF␊ |
538 | ␉// 07C0 - 07CF␊ |
539 | ␉// 07D0 - 07DF␉␊ |
540 | ␉// 07E0 - 07EF␉␉␊ |
541 | ␉{ 0x10DE07E0, "GeForce 7150 / nForce 630i" },␊ |
542 | ␉{ 0x10DE07E1, "GeForce 7100 / nForce 630i" },␊ |
543 | ␉{ 0x10DE07E2, "GeForce 7050 / nForce 630i" },␊ |
544 | ␉{ 0x10DE07E3, "GeForce 7050 / nForce 610i" },␊ |
545 | ␉{ 0x10DE07E5, "GeForce 7050 / nForce 620i" },␊ |
546 | ␉// 07F0 - 07FF␉␊ |
547 | ␉// 0800 - 080F␊ |
548 | ␉// 0810 - 081F␊ |
549 | ␉// 0820 - 082F␊ |
550 | ␉// 0830 - 083F␊ |
551 | ␉// 0840 - 084F␊ |
552 | ␉{ 0x10DE0844, "GeForce 9100M G" },␊ |
553 | ␉{ 0x10DE0845, "GeForce 8200M G" },␊ |
554 | ␉{ 0x10DE0846, "GeForce 9200" },␊ |
555 | ␉{ 0x10DE0847, "GeForce 9100" },␊ |
556 | ␉{ 0x10DE0848, "GeForce 8300" },␊ |
557 | ␉{ 0x10DE0849, "GeForce 8200" },␊ |
558 | ␉{ 0x10DE084A, "nForce 730a" },␊ |
559 | ␉{ 0x10DE084B, "GeForce 9200" },␊ |
560 | ␉{ 0x10DE084C, "nForce 980a/780a SLI" },␊ |
561 | ␉{ 0x10DE084D, "nForce 750a SLI" },␊ |
562 | ␉{ 0x10DE084F, "GeForce 8100 / nForce 720a" },␊ |
563 | ␉// 0850 - 085F␊ |
564 | ␉// 0860 - 086F␉␊ |
565 | ␉{ 0x10DE0860, "GeForce 9400" },␊ |
566 | ␉{ 0x10DE0861, "GeForce 9400" },␊ |
567 | ␉{ 0x10DE0862, "GeForce 9400M G" },␊ |
568 | ␉{ 0x10DE0863, "GeForce 9400M" },␊ |
569 | ␉{ 0x10DE0864, "GeForce 9300" },␊ |
570 | ␉{ 0x10DE0865, "ION" },␊ |
571 | ␉{ 0x10DE0866, "GeForce 9400M G" },␊ |
572 | ␉{ 0x10DE0867, "GeForce 9400" },␊ |
573 | ␉{ 0x10DE0868, "nForce 760i SLI" },␊ |
574 | ␉{ 0x10DE086A, "GeForce 9400" },␊ |
575 | ␉{ 0x10DE086C, "GeForce 9300 / nForce 730i" },␊ |
576 | ␉{ 0x10DE086D, "GeForce 9200" },␊ |
577 | ␉{ 0x10DE086E, "GeForce 9100M G" },␊ |
578 | ␉{ 0x10DE086F, "GeForce 8200M G" },␊ |
579 | ␉// 0870 - 087F␉␊ |
580 | ␉{ 0x10DE0870, "GeForce 9400M" },␊ |
581 | ␉{ 0x10DE0871, "GeForce 9200" },␊ |
582 | ␉{ 0x10DE0872, "GeForce G102M" },␊ |
583 | ␉{ 0x10DE0873, "GeForce G102M" },␊ |
584 | ␉{ 0x10DE0874, "ION 9300M" },␉␊ |
585 | ␉{ 0x10DE0876, "ION" },␊ |
586 | ␉{ 0x10DE087A, "GeForce 9400" },␊ |
587 | ␉{ 0x10DE087D, "ION 9400M" },␊ |
588 | ␉{ 0x10DE087E, "ION LE" },␊ |
589 | ␉{ 0x10DE087F, "ION LE" },␊ |
590 | ␉// 0880 - 088F␊ |
591 | ␉// 0890 - 089F␊ |
592 | ␉// 08A0 - 08AF␊ |
593 | ␉// 08B0 - 08BF␊ |
594 | ␉// 08C0 - 08CF␊ |
595 | ␉// 08D0 - 08DF␉␊ |
596 | ␉// 08E0 - 08EF␉␉␉␊ |
597 | ␉// 08F0 - 08FF␊ |
598 | ␉// 0900 - 090F␊ |
599 | ␉// 0910 - 091F␊ |
600 | ␉// 0920 - 092F␊ |
601 | ␉// 0930 - 093F␊ |
602 | ␉// 0940 - 094F␊ |
603 | ␉// 0950 - 095F␊ |
604 | ␉// 0960 - 096F␊ |
605 | ␉// 0970 - 097F␊ |
606 | ␉// 0980 - 098F␊ |
607 | ␉// 0990 - 099F␊ |
608 | ␉// 09A0 - 09AF␊ |
609 | ␉// 09B0 - 09BF␊ |
610 | ␉// 09C0 - 09CF␊ |
611 | ␉// 09D0 - 09DF␉␊ |
612 | ␉// 09E0 - 09EF␊ |
613 | ␉// 09F0 - 09FF␊ |
614 | ␉// 0A00 - 0A0F␊ |
615 | ␉// 0A10 - 0A1F␊ |
616 | ␉// 0A20 - 0A2F␊ |
617 | ␉{ 0x10DE0A20, "GeForce GT220" },␊ |
618 | ␉{ 0x10DE0A22, "GeForce 315" },␊ |
619 | ␉{ 0x10DE0A23, "GeForce 210" },␊ |
620 | ␉{ 0x10DE0A28, "GeForce GT 230M" },␊ |
621 | ␉{ 0x10DE0A29, "GeForce GT 330M" },␊ |
622 | ␉{ 0x10DE0A2A, "GeForce GT 230M" },␊ |
623 | ␉{ 0x10DE0A2B, "GeForce GT 330M" },␊ |
624 | ␉{ 0x10DE0A2C, "NVS 5100M" },␊ |
625 | ␉{ 0x10DE0A2D, "GeForce GT 320M" },␉␊ |
626 | ␉// 0A30 - 0A3F␉␊ |
627 | ␉{ 0x10DE0A34, "GeForce GT 240M" },␊ |
628 | ␉{ 0x10DE0A35, "GeForce GT 325M" },␊ |
629 | ␉{ 0x10DE0A3C, "Quadro FX 880M" },␊ |
630 | ␉// 0A40 - 0A4F␊ |
631 | ␉// 0A50 - 0A5F␊ |
632 | ␉// 0A60 - 0A6F␊ |
633 | ␉{ 0x10DE0A60, "GeForce G210" },␊ |
634 | ␉{ 0x10DE0A62, "GeForce 205" },␊ |
635 | ␉{ 0x10DE0A63, "GeForce 310" },␊ |
636 | ␉{ 0x10DE0A64, "ION" },␊ |
637 | ␉{ 0x10DE0A65, "GeForce 210" },␊ |
638 | ␉{ 0x10DE0A66, "GeForce 310" },␊ |
639 | ␉{ 0x10DE0A67, "GeForce 315" },␊ |
640 | ␉{ 0x10DE0A68, "GeForce G105M" },␊ |
641 | ␉{ 0x10DE0A69, "GeForce G105M" },␊ |
642 | ␉{ 0x10DE0A6A, "NVS 2100M" },␊ |
643 | ␉{ 0x10DE0A6C, "NVS 3100M" },␊ |
644 | ␉{ 0x10DE0A6E, "GeForce 305M" },␊ |
645 | ␉{ 0x10DE0A6F, "ION" },␉␊ |
646 | ␉// 0A70 - 0A7F␊ |
647 | ␉{ 0x10DE0A70, "GeForce 310M" },␊ |
648 | ␉{ 0x10DE0A71, "GeForce 305M" },␊ |
649 | ␉{ 0x10DE0A72, "GeForce 310M" },␊ |
650 | ␉{ 0x10DE0A73, "GeForce 305M" },␊ |
651 | ␉{ 0x10DE0A74, "GeForce G210M" },␊ |
652 | ␉{ 0x10DE0A75, "GeForce G310M" },␊ |
653 | ␉{ 0x10DE0A78, "Quadro FX 380 LP" },␊ |
654 | ␉{ 0x10DE0A7C, "Quadro FX 380M" },␊ |
655 | ␉// 0A80 - 0A8F␊ |
656 | ␉// 0A90 - 0A9F␊ |
657 | ␉// 0AA0 - 0AAF␊ |
658 | ␉// 0AB0 - 0ABF␊ |
659 | ␉// 0AC0 - 0ACF␊ |
660 | ␉// 0AD0 - 0ADF␉␊ |
661 | ␉// 0AE0 - 0AEF␊ |
662 | ␉// 0AF0 - 0AFF␊ |
663 | ␉// 0B00 - 0B0F␊ |
664 | ␉// 0B10 - 0B1F␊ |
665 | ␉// 0B20 - 0B2F␊ |
666 | ␉// 0B30 - 0B3F␊ |
667 | ␉// 0B40 - 0B4F␊ |
668 | ␉// 0B50 - 0B5F␊ |
669 | ␉// 0B60 - 0B6F␊ |
670 | ␉// 0B70 - 0B7F␊ |
671 | ␉// 0B80 - 0B8F␊ |
672 | ␉// 0B90 - 0B9F␊ |
673 | ␉// 0BA0 - 0BAF␊ |
674 | ␉// 0BB0 - 0BBF␊ |
675 | ␉// 0BC0 - 0BCF␊ |
676 | ␉// 0BD0 - 0BDF␉␊ |
677 | ␉// 0BE0 - 0BEF␊ |
678 | ␉// 0BF0 - 0BFF␊ |
679 | ␉// 0C00 - 0C0F␊ |
680 | ␉// 0C10 - 0C1F␊ |
681 | ␉// 0C20 - 0C2F␊ |
682 | ␉// 0C30 - 0C3F␊ |
683 | ␉// 0C40 - 0C4F␊ |
684 | ␉// 0C50 - 0C5F␊ |
685 | ␉// 0C60 - 0C6F␊ |
686 | ␉// 0C70 - 0C7F␊ |
687 | ␉// 0C80 - 0C8F␊ |
688 | ␉// 0C90 - 0C9F␊ |
689 | ␉// 0CA0 - 0CAF␊ |
690 | ␉{ 0x10DE0CA0, "GeForce GT 330 " },␊ |
691 | ␉{ 0x10DE0CA2, "GeForce GT 320" },␊ |
692 | ␉{ 0x10DE0CA3, "GeForce GT 240" },␊ |
693 | ␉{ 0x10DE0CA4, "GeForce GT 340" },␊ |
694 | ␉{ 0x10DE0CA7, "GeForce GT 330" },␊ |
695 | ␉{ 0x10DE0CA8, "GeForce GTS 260M" },␊ |
696 | ␉{ 0x10DE0CA9, "GeForce GTS 250M" },␊ |
697 | ␉{ 0x10DE0CAC, "GeForce 315" },␊ |
698 | ␉{ 0x10DE0CAF, "GeForce GT 335M" },␊ |
699 | ␉// 0CB0 - 0CBF␉␊ |
700 | ␉{ 0x10DE0CB0, "GeForce GTS 350M" },␊ |
701 | ␉{ 0x10DE0CB1, "GeForce GTS 360M" },␊ |
702 | ␉{ 0x10DE0CBC, "Quadro FX 1800M" },␊ |
703 | ␉// 0CC0 - 0CCF␊ |
704 | ␉// 0CD0 - 0CDF␉␊ |
705 | ␉// 0CE0 - 0CEF␊ |
706 | ␉// 0CF0 - 0CFF␊ |
707 | ␉// 0D00 - 0D0F␊ |
708 | ␉// 0D10 - 0D1F␊ |
709 | ␉// 0D20 - 0D2F␊ |
710 | ␉// 0D30 - 0D3F␊ |
711 | ␉// 0D40 - 0D4F␊ |
712 | ␉// 0D50 - 0D5F␊ |
713 | ␉// 0D60 - 0D6F␊ |
714 | ␉// 0D70 - 0D7F␊ |
715 | ␉// 0D80 - 0D8F␊ |
716 | ␉// 0D90 - 0D9F␊ |
717 | ␉// 0DA0 - 0DAF␉␊ |
718 | ␉// 0DB0 - 0DBF␊ |
719 | ␉// 0DC0 - 0DCF␊ |
720 | ␉{ 0x10DE0DC0, "GeForce GT 440" },␊ |
721 | ␉{ 0x10DE0DC1, "D12-P1-35" },␊ |
722 | ␉{ 0x10DE0DC2, "D12-P1-35" },␊ |
723 | ␉{ 0x10DE0DC4, "GeForce GTS 450" },␊ |
724 | ␉{ 0x10DE0DC5, "GeForce GTS 450" },␊ |
725 | ␉{ 0x10DE0DC6, "GeForce GTS 450" },␊ |
726 | ␉{ 0x10DE0DCA, "GF10x" },␊ |
727 | ␉// 0DD0 - 0DDF␉␊ |
728 | ␉{ 0x10DE0DD1, "GeForce GTX 460M" },␊ |
729 | ␉{ 0x10DE0DD2, "GeForce GT 445M" },␊ |
730 | ␉{ 0x10DE0DD3, "GeForce GT 435M" },␊ |
731 | ␉{ 0x10DE0DD8, "Quadro 2000" },␊ |
732 | ␉{ 0x10DE0DDE, "GF106-ES" },␊ |
733 | ␉{ 0x10DE0DDF, "GF106-INT" },␊ |
734 | ␉// 0DE0 - 0DEF␉␊ |
735 | ␉{ 0x10DE0DE0, "GeForce GT 440" },␊ |
736 | ␉{ 0x10DE0DE1, "GeForce GT 430" },␊ |
737 | ␉{ 0x10DE0DE2, "GeForce GT 420" },␊ |
738 | ␉{ 0x10DE0DE5, "GeForce GT 530" },␊ |
739 | ␉{ 0x10DE0DEB, "GeForce GT 555M" },␊ |
740 | ␉{ 0x10DE0DEE, "GeForce GT 415M" },␊ |
741 | ␉// 0DF0 - 0DFF␉␊ |
742 | ␉{ 0x10DE0DF0, "GeForce GT 425M" },␊ |
743 | ␉{ 0x10DE0DF1, "GeForce GT 420M" },␊ |
744 | ␉{ 0x10DE0DF2, "GeForce GT 435M" },␊ |
745 | ␉{ 0x10DE0DF3, "GeForce GT 420M" },␊ |
746 | ␉{ 0x10DE0DF8, "Quadro 600" },␊ |
747 | ␉{ 0x10DE0DFE, "GF108 ES" },␊ |
748 | ␉{ 0x10DE0DFF, "GF108 INT" },␊ |
749 | ␉// 0E00 - 0E0F␊ |
750 | ␉// 0E10 - 0E1F␊ |
751 | ␉// 0E20 - 0E2F␊ |
752 | ␉{ 0x10DE0E21, "D12U-25" },␊ |
753 | ␉{ 0x10DE0E22, "GeForce GTX 460" },␊ |
754 | ␉{ 0x10DE0E23, "GeForce GTX 460 SE" },␊ |
755 | ␉{ 0x10DE0E24, "GeForce GTX 460" },␊ |
756 | ␉{ 0x10DE0E25, "D12U-50" },␊ |
757 | ␉// 0E30 - 0E3F␉␊ |
758 | ␉{ 0x10DE0E30, "GeForce GTX 470M" },␊ |
759 | ␉{ 0x10DE0E38, "GF104GL" },␊ |
760 | ␉{ 0x10DE0E3E, "GF104-ES" },␊ |
761 | ␉{ 0x10DE0E3F, "GF104-INT" },␊ |
762 | ␉// 0E40 - 0E4F␉␊ |
763 | ␉// 0E50 - 0E5F␊ |
764 | ␉// 0E60 - 0E6F␊ |
765 | ␉// 0E70 - 0E7F␊ |
766 | ␉// 0E80 - 0E8F␊ |
767 | ␉// 0E90 - 0E9F␊ |
768 | ␉// 0EA0 - 0EAF␊ |
769 | ␉// 0EB0 - 0EBF␊ |
770 | ␉// 0EC0 - 0ECF␊ |
771 | ␉// 0ED0 - 0EDF␉␊ |
772 | ␉// 0EE0 - 0EEF␊ |
773 | ␉// 0EF0 - 0EFF␊ |
774 | ␉// 0F00 - 0F0F␊ |
775 | ␉// 0F10 - 0F1F␊ |
776 | ␉// 0F20 - 0F2F␊ |
777 | ␉// 0F30 - 0F3F␊ |
778 | ␉// 0F40 - 0F4F␊ |
779 | ␉// 0F50 - 0F5F␊ |
780 | ␉// 0F60 - 0F6F␊ |
781 | ␉// 0F70 - 0F7F␊ |
782 | ␉// 0F80 - 0F8F␊ |
783 | ␉// 0F90 - 0F9F␊ |
784 | ␉// 0FA0 - 0FAF␊ |
785 | ␉// 0FB0 - 0FBF␊ |
786 | ␉// 0FC0 - 0FCF␊ |
787 | ␉// 0FD0 - 0FDF␊ |
788 | ␉// 0FE0 - 0FEF␊ |
789 | ␉// 0FF0 - 0FFF␊ |
790 | ␉// 1000 - 100F␊ |
791 | ␉// 1010 - 101F␊ |
792 | ␉// 1020 - 102F␊ |
793 | ␉// 1030 - 103F␊ |
794 | ␉// 1040 - 104F␊ |
795 | ␉{ 0x10DE1040, "GeForce GT 520" },␉␊ |
796 | ␉// 1050 - 105F␊ |
797 | ␉{ 0x10DE1050, "GeForce GT 520M" },␊ |
798 | ␉// 1060 - 106F␊ |
799 | ␉// 1070 - 107F␊ |
800 | ␉// 1080 - 108F␊ |
801 | ␉{ 0x10DE1080, "GeForce GTX 580" },␊ |
802 | ␉{ 0x10DE1081, "GeForce GTX 570" },␊ |
803 | ␉{ 0x10DE1082, "GeForce GTX 560 Ti" },␊ |
804 | ␉{ 0x10DE1083, "D13U" },␊ |
805 | ␉{ 0x10DE1088, "GeForce GTX 590" },␊ |
806 | ␉// 1090 - 109F␉␊ |
807 | ␉{ 0x10DE1098, "D13U" },␊ |
808 | ␉{ 0x10DE109A, "N12E-Q5" },␊ |
809 | ␉// 10A0 - 10AF␊ |
810 | ␉// 10B0 - 10BF␊ |
811 | ␉// 10C0 - 10CF␊ |
812 | ␉{ 0x10DE10C3, "GeForce 8400 GS" },␊ |
813 | ␉// 1200 - ␊ |
814 | ␉{ 0x10DE1200, "GeForce GTX 560 Ti" },␊ |
815 | ␉{ 0x10DE1244, "GeForce GTX 550 Ti" },␊ |
816 | ␉{ 0x10DE1245, "GeForce GTS 450" },␉␊ |
817 | };␊ |
818 | ␊ |
819 | static uint16_t swap16(uint16_t x)␊ |
820 | {␊ |
821 | ␉return (((x & 0x00FF) << 8) | ((x & 0xFF00) >> 8));␊ |
822 | }␊ |
823 | ␊ |
824 | static uint16_t read16(uint8_t *ptr, uint16_t offset)␊ |
825 | {␊ |
826 | ␉uint8_t ret[2];␊ |
827 | ␉␊ |
828 | ␉ret[0] = ptr[offset+1];␊ |
829 | ␉ret[1] = ptr[offset];␊ |
830 | ␉␊ |
831 | ␉return *((uint16_t*)&ret);␊ |
832 | }␊ |
833 | ␊ |
834 | #if 0␊ |
835 | static uint32_t swap32(uint32_t x)␊ |
836 | {␊ |
837 | ␉return ((x & 0x000000FF) << 24) | ((x & 0x0000FF00) << 8 ) | ((x & 0x00FF0000) >> 8 ) | ((x & 0xFF000000) >> 24);␊ |
838 | }␊ |
839 | ␊ |
840 | static uint8_t␉read8(uint8_t *ptr, uint16_t offset)␊ |
841 | { ␊ |
842 | ␉return ptr[offset];␊ |
843 | }␊ |
844 | ␊ |
845 | static uint32_t read32(uint8_t *ptr, uint16_t offset)␊ |
846 | {␊ |
847 | ␉uint8_t ret[4];␊ |
848 | ␉␊ |
849 | ␉ret[0] = ptr[offset+3];␊ |
850 | ␉ret[1] = ptr[offset+2];␊ |
851 | ␉ret[2] = ptr[offset+1];␊ |
852 | ␉ret[3] = ptr[offset];␊ |
853 | ␉␊ |
854 | ␉return *((uint32_t*)&ret);␊ |
855 | }␊ |
856 | #endif␊ |
857 | ␊ |
858 | static int patch_nvidia_rom(uint8_t *rom)␊ |
859 | {␊ |
860 | ␉if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {␊ |
861 | ␉␉printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);␊ |
862 | ␉␉return PATCH_ROM_FAILED;␊ |
863 | ␉}␊ |
864 | ␉␊ |
865 | ␉uint16_t dcbptr = swap16(read16(rom, 0x36));␊ |
866 | ␉␊ |
867 | ␉if (!dcbptr) {␊ |
868 | ␉␉printf("no dcb table found\n");␊ |
869 | ␉␉return PATCH_ROM_FAILED;␊ |
870 | ␉}␊ |
871 | //␉else␊ |
872 | //␉␉printf("dcb table at offset 0x%04x\n", dcbptr);␊ |
873 | ␉ ␊ |
874 | ␉uint8_t *dcbtable␉␉ = &rom[dcbptr];␊ |
875 | ␉uint8_t dcbtable_version = dcbtable[0];␊ |
876 | ␉uint8_t headerlength␉ = 0;␊ |
877 | ␉uint8_t recordlength␉ = 0;␊ |
878 | ␉uint8_t numentries␉␉ = 0;␊ |
879 | ␉␊ |
880 | ␉if (dcbtable_version >= 0x20)␊ |
881 | ␉{␊ |
882 | ␉␉uint32_t sig;␊ |
883 | ␉␉␊ |
884 | ␉␉if (dcbtable_version >= 0x30)␊ |
885 | ␉␉{␊ |
886 | ␉␉␉headerlength = dcbtable[1];␊ |
887 | ␉␉␉numentries␉ = dcbtable[2];␊ |
888 | ␉␉␉recordlength = dcbtable[3];␊ |
889 | ␉␉␉␊ |
890 | ␉␉␉sig = *(uint32_t *)&dcbtable[6];␊ |
891 | ␉␉}␊ |
892 | ␉␉else␊ |
893 | ␉␉{␊ |
894 | ␉␉␉sig = *(uint32_t *)&dcbtable[4];␊ |
895 | ␉␉␉headerlength = 8;␊ |
896 | ␉␉}␊ |
897 | ␉␉␊ |
898 | ␉␉if (sig != 0x4edcbdcb)␊ |
899 | ␉␉{␊ |
900 | ␉␉␉printf("bad display config block signature (0x%8x)\n", sig);␊ |
901 | ␉␉␉return PATCH_ROM_FAILED;␊ |
902 | ␉␉}␊ |
903 | ␉}␊ |
904 | ␉else if (dcbtable_version >= 0x14) /* some NV15/16, and NV11+ */␊ |
905 | ␉{␊ |
906 | ␉␉char sig[8] = { 0 };␊ |
907 | ␉␉␊ |
908 | ␉␉strncpy(sig, (char *)&dcbtable[-7], 7);␊ |
909 | ␉␉recordlength = 10;␊ |
910 | ␉␉␊ |
911 | ␉␉if (strcmp(sig, "DEV_REC"))␊ |
912 | ␉␉{␊ |
913 | ␉␉␉printf("Bad Display Configuration Block signature (%s)\n", sig);␊ |
914 | ␉␉␉return PATCH_ROM_FAILED;␊ |
915 | ␉␉}␊ |
916 | ␉}␊ |
917 | ␉else␊ |
918 | ␉{␊ |
919 | ␉␉printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);␊ |
920 | ␉␉return PATCH_ROM_FAILED;␊ |
921 | ␉}␊ |
922 | ␉␊ |
923 | ␉if (numentries >= MAX_NUM_DCB_ENTRIES)␊ |
924 | ␉␉numentries = MAX_NUM_DCB_ENTRIES;␊ |
925 | ␉␊ |
926 | ␉uint8_t num_outputs = 0, i = 0;␊ |
927 | ␉␊ |
928 | ␉struct dcbentry␊ |
929 | ␉{␊ |
930 | ␉␉uint8_t type;␊ |
931 | ␉␉uint8_t index;␊ |
932 | ␉␉uint8_t *heads;␊ |
933 | ␉} entries[numentries];␊ |
934 | ␉␊ |
935 | ␉for (i = 0; i < numentries; i++)␊ |
936 | ␉{␊ |
937 | ␉␉uint32_t connection;␊ |
938 | ␉␉connection = *(uint32_t *)&dcbtable[headerlength + recordlength * i];␊ |
939 | ␉␉␊ |
940 | ␉␉/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */␊ |
941 | ␉␉if ((connection & 0x0000000f) == 0x0000000f) /* end of records */ ␊ |
942 | ␉␉␉continue;␊ |
943 | ␉␉if (connection == 0x00000000) /* seen on an NV11 with DCB v1.5 */ ␊ |
944 | ␉␉␉continue;␊ |
945 | ␉␉if ((connection & 0xf) == 0x6) /* we skip type 6 as it doesnt appear on macbook nvcaps */␊ |
946 | ␉␉␉continue;␊ |
947 | ␉␉␊ |
948 | ␉␉entries[num_outputs].type = connection & 0xf;␊ |
949 | ␉␉entries[num_outputs].index = num_outputs;␊ |
950 | ␉␉entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);␊ |
951 | ␉}␊ |
952 | ␉␊ |
953 | ␉int has_lvds = false;␊ |
954 | ␉uint8_t channel1 = 0, channel2 = 0;␊ |
955 | ␉␊ |
956 | ␉for (i = 0; i < num_outputs; i++)␊ |
957 | ␉{␊ |
958 | ␉␉if (entries[i].type == 3)␊ |
959 | ␉␉{␊ |
960 | ␉␉␉has_lvds = true;␊ |
961 | ␉␉␉//printf("found LVDS\n");␊ |
962 | ␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
963 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
964 | ␉␉}␊ |
965 | ␉}␊ |
966 | ␉␊ |
967 | ␉// if we have a LVDS output, we group the rest to the second channel␊ |
968 | ␉if (has_lvds)␊ |
969 | ␉{␊ |
970 | ␉␉for (i = 0; i < num_outputs; i++)␊ |
971 | ␉␉{␊ |
972 | ␉␉␉if (entries[i].type == TYPE_GROUPED)␊ |
973 | ␉␉␉␉continue;␊ |
974 | ␉␉␉␊ |
975 | ␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
976 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
977 | ␉␉}␊ |
978 | ␉}␊ |
979 | ␉else␊ |
980 | ␉{␊ |
981 | ␉␉int x;␊ |
982 | ␉␉// we loop twice as we need to generate two channels␊ |
983 | ␉␉for (x = 0; x <= 1; x++)␊ |
984 | ␉␉{␊ |
985 | ␉␉␉for (i=0; i<num_outputs; i++)␊ |
986 | ␉␉␉{␊ |
987 | ␉␉␉␉if (entries[i].type == TYPE_GROUPED)␊ |
988 | ␉␉␉␉␉continue;␊ |
989 | ␉␉␉␉// if type is TMDS, the prior output is ANALOG␊ |
990 | ␉␉␉␉// we always group ANALOG and TMDS␊ |
991 | ␉␉␉␉// if there is a TV output after TMDS, we group it to that channel as well␊ |
992 | ␉␉␉␉if (i && entries[i].type == 0x2)␊ |
993 | ␉␉␉␉{␊ |
994 | ␉␉␉␉␉switch (x)␊ |
995 | ␉␉␉␉␉{␊ |
996 | ␉␉␉␉␉␉case 0:␊ |
997 | ␉␉␉␉␉␉␉//printf("group channel 1\n");␊ |
998 | ␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i].index);␊ |
999 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1000 | ␉␉␉␉␉␉␉␊ |
1001 | ␉␉␉␉␉␉␉if ((entries[i-1].type == 0x0))␊ |
1002 | ␉␉␉␉␉␉␉{␊ |
1003 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i-1].index);␊ |
1004 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
1005 | ␉␉␉␉␉␉␉}␊ |
1006 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
1007 | ␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊ |
1008 | ␉␉␉␉␉␉␉{␊ |
1009 | ␉␉␉␉␉␉␉␉//␉printf("group tv1\n");␊ |
1010 | ␉␉␉␉␉␉␉␉channel1 |= ( 0x1 << entries[i+1].index);␊ |
1011 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
1012 | ␉␉␉␉␉␉␉}␊ |
1013 | ␉␉␉␉␉␉␉break;␊ |
1014 | ␉␉␉␉␉␉␊ |
1015 | ␉␉␉␉␉␉case 1:␊ |
1016 | ␉␉␉␉␉␉␉//printf("group channel 2 : %d\n", i);␊ |
1017 | ␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i].index);␊ |
1018 | ␉␉␉␉␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1019 | ␉␉␉␉␉␉␉␊ |
1020 | ␉␉␉␉␉␉␉if ((entries[i - 1].type == 0x0))␊ |
1021 | ␉␉␉␉␉␉␉{␊ |
1022 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i-1].index);␊ |
1023 | ␉␉␉␉␉␉␉␉entries[i-1].type = TYPE_GROUPED;␊ |
1024 | ␉␉␉␉␉␉␉}␊ |
1025 | ␉␉␉␉␉␉␉// group TV as well if there is one␊ |
1026 | ␉␉␉␉␉␉␉if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) )␊ |
1027 | ␉␉␉␉␉␉␉{␊ |
1028 | ␉␉␉␉␉␉␉␉//␉printf("group tv2\n");␊ |
1029 | ␉␉␉␉␉␉␉␉channel2 |= ( 0x1 << entries[i+1].index);␊ |
1030 | ␉␉␉␉␉␉␉␉entries[i+1].type = TYPE_GROUPED;␊ |
1031 | ␉␉␉␉␉␉␉}␊ |
1032 | ␉␉␉␉␉␉␉break;␊ |
1033 | ␉␉␉␉␉}␊ |
1034 | ␉␉␉␉␉break;␊ |
1035 | ␉␉␉␉}␊ |
1036 | ␉␉␉}␊ |
1037 | ␉␉}␊ |
1038 | ␉}␊ |
1039 | ␉␊ |
1040 | ␉// if we have left ungrouped outputs merge them to the empty channel␊ |
1041 | ␉uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);␊ |
1042 | ␉togroup = &channel2;␊ |
1043 | ␉␊ |
1044 | ␉for (i = 0; i < num_outputs; i++)␊ |
1045 | ␉{␊ |
1046 | ␉␉if (entries[i].type != TYPE_GROUPED)␊ |
1047 | ␉␉{␊ |
1048 | ␉␉␉//printf("%d not grouped\n", i);␊ |
1049 | ␉␉␉if (togroup)␊ |
1050 | ␉␉␉{␊ |
1051 | ␉␉␉␉*togroup |= ( 0x1 << entries[i].index);␊ |
1052 | ␉␉␉}␊ |
1053 | ␉␉␉entries[i].type = TYPE_GROUPED;␊ |
1054 | ␉␉}␊ |
1055 | ␉}␊ |
1056 | ␉␊ |
1057 | ␉if (channel1 > channel2)␊ |
1058 | ␉{␊ |
1059 | ␉␉uint8_t buff = channel1;␊ |
1060 | ␉␉channel1 = channel2;␊ |
1061 | ␉␉channel2 = buff;␊ |
1062 | ␉}␊ |
1063 | ␉␊ |
1064 | ␉default_NVCAP[6] = channel1;␊ |
1065 | ␉default_NVCAP[8] = channel2;␊ |
1066 | ␉␊ |
1067 | ␉// patching HEADS␊ |
1068 | ␉for (i = 0; i < num_outputs; i++)␊ |
1069 | ␉{␊ |
1070 | ␉␉if (channel1 & (1 << i))␊ |
1071 | ␉␉{␊ |
1072 | ␉␉␉*entries[i].heads = 1;␊ |
1073 | ␉␉}␊ |
1074 | ␉␉else if(channel2 & (1 << i))␊ |
1075 | ␉␉{␊ |
1076 | ␉␉␉*entries[i].heads = 2;␊ |
1077 | ␉␉}␊ |
1078 | ␉}␊ |
1079 | ␉return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);␊ |
1080 | }␊ |
1081 | ␊ |
1082 | static char *get_nvidia_model(uint32_t id)␊ |
1083 | {␊ |
1084 | ␉int i;␊ |
1085 | ␉␊ |
1086 | ␉for (i = 1; i < (sizeof(NVKnownChipsets) / sizeof(NVKnownChipsets[0])); i++) {␊ |
1087 | ␉␉if (NVKnownChipsets[i].device == id)␊ |
1088 | ␉␉{␊ |
1089 | ␉␉␉return NVKnownChipsets[i].name;␊ |
1090 | ␉␉}␊ |
1091 | ␉}␊ |
1092 | ␉return NVKnownChipsets[0].name;␊ |
1093 | }␊ |
1094 | ␊ |
1095 | static uint32_t load_nvidia_bios_file(const char *filename, uint8_t *buf, int bufsize)␊ |
1096 | {␊ |
1097 | ␉int fd;␊ |
1098 | ␉int size;␊ |
1099 | ␉␊ |
1100 | ␉if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0)␊ |
1101 | ␉{␊ |
1102 | ␉␉return 0;␊ |
1103 | ␉}␊ |
1104 | ␉␊ |
1105 | ␉size = file_size(fd);␊ |
1106 | ␉␊ |
1107 | ␉if (size > bufsize)␊ |
1108 | ␉{␊ |
1109 | ␉␉printf("Filesize of %s is bigger than expected! Truncating to 0x%x Bytes!\n",␊ |
1110 | ␉␉␉␉filename, bufsize);␊ |
1111 | ␉␉size = bufsize;␊ |
1112 | ␉}␊ |
1113 | ␉size = read(fd, (char *)buf, size);␊ |
1114 | ␉close(fd);␊ |
1115 | ␉␊ |
1116 | ␉return size > 0 ? size : 0;␊ |
1117 | }␊ |
1118 | ␊ |
1119 | static int devprop_add_nvidia_template(struct DevPropDevice *device)␊ |
1120 | {␊ |
1121 | ␉char tmp[16];␊ |
1122 | ␉␊ |
1123 | ␉if (!device)␊ |
1124 | ␉␉return 0;␊ |
1125 | ␉␊ |
1126 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))␊ |
1127 | ␉␉return 0;␊ |
1128 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))␊ |
1129 | ␉␉return 0;␊ |
1130 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))␊ |
1131 | ␉␉return 0;␊ |
1132 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))␊ |
1133 | ␉␉return 0;␊ |
1134 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))␊ |
1135 | ␉␉return 0;␊ |
1136 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))␊ |
1137 | ␉␉return 0;␊ |
1138 | ␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊ |
1139 | ␉␉return 0;␊ |
1140 | ␉␊ |
1141 | ␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊ |
1142 | ␉// len = sprintf(tmp, "Slot-%x", devices_number);␊ |
1143 | ␉sprintf(tmp, "Slot-%x",devices_number);␊ |
1144 | ␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));␊ |
1145 | ␉devices_number++;␊ |
1146 | ␉␊ |
1147 | ␉return 1;␊ |
1148 | }␊ |
1149 | ␊ |
1150 | int hex2bin(const char *hex, uint8_t *bin, int len)␊ |
1151 | {␊ |
1152 | ␉char␉*p;␊ |
1153 | ␉int␉␉i;␊ |
1154 | ␉char␉buf[3];␊ |
1155 | ␉␊ |
1156 | ␉if (hex == NULL || bin == NULL || len <= 0 || strlen(hex) != len * 2) {␊ |
1157 | ␉␉printf("[ERROR] bin2hex input error\n");␊ |
1158 | ␉␉return -1;␊ |
1159 | ␉}␊ |
1160 | ␉␊ |
1161 | ␉buf[2] = '\0';␊ |
1162 | ␉p = (char *) hex;␊ |
1163 | ␉␊ |
1164 | ␉for (i = 0; i < len; i++)␊ |
1165 | ␉{␊ |
1166 | ␉␉if (p[0] == '\0' || p[1] == '\0' || !isxdigit(p[0]) || !isxdigit(p[1])) {␊ |
1167 | ␉␉␉printf("[ERROR] bin2hex '%s' syntax error\n", hex);␊ |
1168 | ␉␉␉return -2;␊ |
1169 | ␉␉}␊ |
1170 | ␉␉buf[0] = *p++;␊ |
1171 | ␉␉buf[1] = *p++;␊ |
1172 | ␉␉bin[i] = (unsigned char) strtoul(buf, NULL, 16);␊ |
1173 | ␉}␊ |
1174 | ␉return 0;␊ |
1175 | }␊ |
1176 | ␊ |
1177 | unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev)␊ |
1178 | {␊ |
1179 | ␉unsigned long long vram_size = 0;␊ |
1180 | ␉␊ |
1181 | ␉if (nvCardType < NV_ARCH_50)␊ |
1182 | ␉{␊ |
1183 | ␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
1184 | ␉␉vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;␊ |
1185 | ␉}␊ |
1186 | ␉else if (nvCardType < NV_ARCH_C0)␊ |
1187 | ␉{␊ |
1188 | ␉␉vram_size = REG32(NV04_PFB_FIFO_DATA);␊ |
1189 | ␉␉vram_size |= (vram_size & 0xff) << 32;␊ |
1190 | ␉␉vram_size &= 0xffffffff00ll;␊ |
1191 | ␉}␊ |
1192 | ␉else // >= NV_ARCH_C0␊ |
1193 | ␉{␊ |
1194 | ␉␉vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;␊ |
1195 | ␉␉vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);␊ |
1196 | ␉}␊ |
1197 | ␉␊ |
1198 | ␉// Workaround for GT 420/430 & 9600M GT␊ |
1199 | ␉switch (nvda_dev->device_id)␊ |
1200 | ␉{␊ |
1201 | ␉␉case 0x0DE1: vram_size = 1024*1024*1024; break; // GT 430␊ |
1202 | ␉␉case 0x0DE2: vram_size = 1024*1024*1024; break; // GT 420␊ |
1203 | ␉␉case 0x0649: vram_size = 512*1024*1024; break; // 9600M GT␊ |
1204 | ␉␉default: break;␊ |
1205 | ␉}␊ |
1206 | ␉␊ |
1207 | ␉return vram_size;␊ |
1208 | }␊ |
1209 | ␊ |
1210 | bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊ |
1211 | {␊ |
1212 | ␉struct DevPropDevice␉*device;␊ |
1213 | ␉char␉␉␉␉␉*devicepath;␊ |
1214 | ␉option_rom_pci_header_t *rom_pci_header;␊ |
1215 | ␉volatile uint8_t␉␉*regs;␊ |
1216 | ␉uint8_t␉␉␉␉␉*rom;␊ |
1217 | ␉uint8_t␉␉␉␉␉*nvRom;␊ |
1218 | ␉uint8_t␉␉␉␉␉nvCardType;␊ |
1219 | ␉unsigned long long␉␉videoRam;␊ |
1220 | ␉uint32_t␉␉␉␉nvBiosOveride;␊ |
1221 | ␉uint32_t␉␉␉␉bar[7];␊ |
1222 | ␉uint32_t␉␉␉␉boot_display;␊ |
1223 | ␉int␉␉␉␉␉␉nvPatch;␊ |
1224 | ␉int␉␉␉␉␉␉len;␊ |
1225 | ␉char␉␉␉␉␉biosVersion[32];␊ |
1226 | ␉char␉␉␉␉␉nvFilename[32];␊ |
1227 | ␉char␉␉␉␉␉kNVCAP[12];␊ |
1228 | ␉char␉␉␉␉␉*model;␊ |
1229 | ␉const char␉␉␉␉*value;␊ |
1230 | ␉bool␉␉␉␉␉doit;␊ |
1231 | ␉␊ |
1232 | ␉devicepath = get_pci_dev_path(nvda_dev);␊ |
1233 | ␉bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );␊ |
1234 | ␉regs = (uint8_t *) (bar[0] & ~0x0f);␊ |
1235 | ␉␊ |
1236 | ␉// get card type␊ |
1237 | ␉nvCardType = (REG32(0) >> 20) & 0x1ff;␊ |
1238 | ␉␊ |
1239 | ␉// Amount of VRAM in kilobytes␊ |
1240 | ␉videoRam = mem_detect(regs, nvCardType, nvda_dev);␊ |
1241 | ␉model = get_nvidia_model((nvda_dev->vendor_id << 16) | nvda_dev->device_id);␊ |
1242 | ␉␊ |
1243 | ␉verbose("nVidia %s %dMB NV%02x [%04x:%04x] :: %s\n",␊ |
1244 | ␉␉␉model, (uint32_t)(videoRam / 1024 / 1024),␊ |
1245 | ␉␉␉(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,␊ |
1246 | ␉␉␉devicepath);␊ |
1247 | ␉␊ |
1248 | ␉rom = malloc(NVIDIA_ROM_SIZE);␊ |
1249 | ␉sprintf(nvFilename, "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id,␊ |
1250 | ␉␉␉(uint16_t)nvda_dev->device_id);␊ |
1251 | ␉␊ |
1252 | ␉if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->bootConfig) && doit)␊ |
1253 | ␉{␊ |
1254 | ␉␉verbose("Looking for nvidia video bios file %s\n", nvFilename);␊ |
1255 | ␉␉nvBiosOveride = load_nvidia_bios_file(nvFilename, rom, NVIDIA_ROM_SIZE);␊ |
1256 | ␉␉␊ |
1257 | ␉␉if (nvBiosOveride > 0)␊ |
1258 | ␉␉{␊ |
1259 | ␉␉␉verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);␊ |
1260 | ␉␉␉DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);␊ |
1261 | ␉␉}␊ |
1262 | ␉␉else␊ |
1263 | ␉␉{␊ |
1264 | ␉␉␉printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);␊ |
1265 | ␉␉␉return false;␊ |
1266 | ␉␉}␊ |
1267 | ␉}␊ |
1268 | ␉else␊ |
1269 | ␉{␊ |
1270 | ␉␉// Otherwise read bios from card␊ |
1271 | ␉␉nvBiosOveride = 0;␊ |
1272 | ␉␉␊ |
1273 | ␉␉// TODO: we should really check for the signature before copying the rom, i think.␊ |
1274 | ␉␉␊ |
1275 | ␉␉// PRAMIN first␊ |
1276 | ␉␉nvRom = (uint8_t*)®s[NV_PRAMIN_OFFSET];␊ |
1277 | ␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
1278 | ␉␉␊ |
1279 | ␉␉// Valid Signature ?␊ |
1280 | ␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊ |
1281 | ␉␉{␊ |
1282 | ␉␉␉// PROM next␊ |
1283 | ␉␉␉// Enable PROM access␊ |
1284 | ␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊ |
1285 | ␉␉␉␊ |
1286 | ␉␉␉nvRom = (uint8_t*)®s[NV_PROM_OFFSET];␊ |
1287 | ␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊ |
1288 | ␉␉␉␊ |
1289 | ␉␉␉// disable PROM access␊ |
1290 | ␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊ |
1291 | ␉␉␉␊ |
1292 | ␉␉␉// Valid Signature ?␊ |
1293 | ␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊ |
1294 | ␉␉␉{␊ |
1295 | ␉␉␉␉// 0xC0000 last␊ |
1296 | ␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊ |
1297 | ␉␉␉␉␊ |
1298 | ␉␉␉␉// Valid Signature ?␊ |
1299 | ␉␉␉␉if (rom[0] != 0x55 && rom[1] != 0xaa)␊ |
1300 | ␉␉␉␉{␊ |
1301 | ␉␉␉␉␉printf("ERROR: Unable to locate nVidia Video BIOS\n");␊ |
1302 | ␉␉␉␉␉return false;␊ |
1303 | ␉␉␉␉}␊ |
1304 | ␉␉␉␉else␊ |
1305 | ␉␉␉␉{␊ |
1306 | ␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1307 | ␉␉␉␉}␊ |
1308 | ␉␉␉}␊ |
1309 | ␉␉␉else␊ |
1310 | ␉␉␉{␊ |
1311 | ␉␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1312 | ␉␉␉}␊ |
1313 | ␉␉}␊ |
1314 | ␉␉else␊ |
1315 | ␉␉{␊ |
1316 | ␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊ |
1317 | ␉␉}␊ |
1318 | ␉}␊ |
1319 | ␉␊ |
1320 | ␉if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {␊ |
1321 | ␉␉printf("ERROR: nVidia ROM Patching Failed!\n");␊ |
1322 | ␉␉//return false;␊ |
1323 | ␉}␊ |
1324 | ␉␊ |
1325 | ␉rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);␊ |
1326 | ␉␊ |
1327 | ␉// check for 'PCIR' sig␊ |
1328 | ␉if (rom_pci_header->signature == 0x50434952)␊ |
1329 | ␉{␊ |
1330 | ␉␉if (rom_pci_header->device_id != nvda_dev->device_id)␊ |
1331 | ␉␉{␊ |
1332 | ␉␉␉// Get Model from the OpROM␊ |
1333 | ␉␉␉model = get_nvidia_model((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id);␊ |
1334 | ␉␉}␊ |
1335 | ␉␉else␊ |
1336 | ␉␉{␊ |
1337 | ␉␉␉printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);␊ |
1338 | ␉␉}␊ |
1339 | ␉}␊ |
1340 | ␉␊ |
1341 | ␉if (!string) {␊ |
1342 | ␉␉string = devprop_create_string();␊ |
1343 | ␉}␊ |
1344 | ␉device = devprop_add_device(string, devicepath);␊ |
1345 | ␉␊ |
1346 | ␉/* FIXME: for primary graphics card only */␊ |
1347 | ␉boot_display = 1;␊ |
1348 | ␉devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);␊ |
1349 | ␉␊ |
1350 | ␉if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {␊ |
1351 | ␉␉uint8_t built_in = 0x01;␊ |
1352 | ␉␉devprop_add_value(device, "@0,built-in", &built_in, 1);␊ |
1353 | ␉}␊ |
1354 | ␉␊ |
1355 | ␉// get bios version␊ |
1356 | ␉const int MAX_BIOS_VERSION_LENGTH = 32;␊ |
1357 | ␉char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);␊ |
1358 | ␉␊ |
1359 | ␉memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);␊ |
1360 | ␉␊ |
1361 | ␉int i, version_start;␊ |
1362 | ␉int crlf_count = 0;␊ |
1363 | ␉␊ |
1364 | ␉// only search the first 384 bytes␊ |
1365 | ␉for (i = 0; i < 0x180; i++)␊ |
1366 | ␉{␊ |
1367 | ␉␉if (rom[i] == 0x0D && rom[i+1] == 0x0A)␊ |
1368 | ␉␉{␊ |
1369 | ␉␉␉crlf_count++;␊ |
1370 | ␉␉␉// second 0x0D0A was found, extract bios version␊ |
1371 | ␉␉␉if (crlf_count == 2)␊ |
1372 | ␉␉␉{␊ |
1373 | ␉␉␉␉if (rom[i-1] == 0x20) i--; // strip last " "␊ |
1374 | ␉␉␉␉{␊ |
1375 | ␉␉␉␉␉for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--)␊ |
1376 | ␉␉␉␉␉{␊ |
1377 | ␉␉␉␉␉␉// find start␊ |
1378 | ␉␉␉␉␉␉if (rom[version_start] == 0x00)␊ |
1379 | ␉␉␉␉␉␉{␊ |
1380 | ␉␉␉␉␉␉␉version_start++;␊ |
1381 | ␉␉␉␉␉␉␉␊ |
1382 | ␉␉␉␉␉␉␉// strip "Version "␊ |
1383 | ␉␉␉␉␉␉␉if (strncmp((const char*)rom+version_start, "Version ", 8) == 0)␊ |
1384 | ␉␉␉␉␉␉␉{␊ |
1385 | ␉␉␉␉␉␉␉␉version_start += 8;␊ |
1386 | ␉␉␉␉␉␉␉}␊ |
1387 | ␉␉␉␉␉␉␉strncpy(version_str, (const char*)rom+version_start, i-version_start);␊ |
1388 | ␉␉␉␉␉␉␉␊ |
1389 | ␉␉␉␉␉␉␉break;␊ |
1390 | ␉␉␉␉␉␉}␊ |
1391 | ␉␉␉␉␉}␊ |
1392 | ␉␉␉␉}␊ |
1393 | ␉␉␉␉break; //Azi: reminder␊ |
1394 | ␉␉␉}␊ |
1395 | ␉␉}␊ |
1396 | ␉}␊ |
1397 | ␉␊ |
1398 | ␉sprintf(biosVersion, "%s", (nvBiosOveride > 0) ? nvFilename : version_str);␊ |
1399 | ␉sprintf(kNVCAP, "NVCAP_%04x", nvda_dev->device_id);␊ |
1400 | ␉␊ |
1401 | ␉if (getValueForKey(kNVCAP, &value, &len, &bootInfo->bootConfig) && len == NVCAP_LEN * 2)␊ |
1402 | ␉{␊ |
1403 | ␉␉uint8_t new_NVCAP[NVCAP_LEN];␊ |
1404 | ␉␉␊ |
1405 | ␉␉if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0)␊ |
1406 | ␉␉{␊ |
1407 | ␉␉␉verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);␊ |
1408 | ␉␉␉memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);␊ |
1409 | ␉␉}␊ |
1410 | ␉}␊ |
1411 | ␉␊ |
1412 | #if DEBUG_NVCAP␊ |
1413 | ␉printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",␊ |
1414 | ␉default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],␊ |
1415 | ␉default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],␊ |
1416 | ␉default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],␊ |
1417 | ␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊ |
1418 | ␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊ |
1419 | #endif␊ |
1420 | ␉␊ |
1421 | ␉devprop_add_nvidia_template(device);␊ |
1422 | ␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊ |
1423 | ␉devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);␊ |
1424 | ␉devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);␊ |
1425 | ␉devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);␊ |
1426 | ␉␊ |
1427 | ␉if (getBoolForKey(kVBIOS, &doit, &bootInfo->bootConfig) && doit)␊ |
1428 | ␉{␊ |
1429 | ␉␉devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));␊ |
1430 | ␉}␊ |
1431 | ␉␊ |
1432 | ␉stringdata = malloc(sizeof(uint8_t) * string->length);␊ |
1433 | ␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊ |
1434 | ␉stringlength = string->length;␊ |
1435 | ␉␊ |
1436 | ␉return true;␊ |
1437 | }␊ |
1438 | |