1 | /*␊ |
2 | * platform.h␊ |
3 | * AsereBLN: reworked and extended␊ |
4 | *␊ |
5 | */␊ |
6 | ␊ |
7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
8 | #define __LIBSAIO_PLATFORM_H␊ |
9 | ␊ |
10 | ␊ |
11 | //Azi: this was already acting as a mini libsaio.h :P see bootstruct.h.␊ |
12 | //#include "libsaio.h"␊ |
13 | #include "libsa.h"␊ |
14 | #include "saio_types.h"␊ |
15 | #include "saio_internal.h" //Updt - delete these and test!!!␊ |
16 | ␊ |
17 | ␊ |
18 | extern bool platformCPUFeature(uint32_t);␊ |
19 | extern void scan_platform(void);␊ |
20 | //Azi: function is on mem.c which is gone on Kabyl's... ???␊ |
21 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
22 | ␊ |
23 | /* CPUID index into cpuid_raw */␊ |
24 | #define CPUID_0␉␉␉␉␉0␊ |
25 | #define CPUID_1␉␉␉␉␉1␊ |
26 | #define CPUID_2␉␉␉␉␉2␊ |
27 | #define CPUID_3␉␉␉␉␉3␊ |
28 | #define CPUID_4␉␉␉␉␉4␊ |
29 | #define CPUID_80␉␉␉␉5␊ |
30 | #define CPUID_81␉␉␉␉6␊ |
31 | #define CPUID_MAX␉␉␉␉7␊ |
32 | ␊ |
33 | #define CPU_MODEL_YONAH␉␉␉0x0E␊ |
34 | #define CPU_MODEL_MEROM␉␉␉0x0F␊ |
35 | #define CPU_MODEL_PENRYN␉␉0x17␊ |
36 | #define CPU_MODEL_NEHALEM␉␉0x1A␊ |
37 | #define CPU_MODEL_ATOM␉␉␉0x1C␊ |
38 | #define CPU_MODEL_FIELDS␉␉0x1E␉␉␉␉␉// Lynnfield, Clarksfield, Jasper␊ |
39 | #define CPU_MODEL_DALES␉␉␉0x1F␉␉␉␉␉// Havendale, Auburndale␊ |
40 | #define CPU_MODEL_DALES_32NM␉0x25␉␉␉␉␉// Clarkdale, Arrandale␊ |
41 | #define CPU_MODEL_SANDY␉␉␉0x2a␉␉␉␉␉// Sandy bridge␊ |
42 | #define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊ |
43 | #define CPU_MODEL_SANDY_XEON␉0x2D␊ |
44 | #define CPU_MODEL_NEHALEM_EX␉0x2E␊ |
45 | #define CPU_MODEL_WESTMERE_EX␉0x2F␊ |
46 | ␊ |
47 | /* CPU Features */␊ |
48 | #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉␉␉// MMX Instruction Set␊ |
49 | #define CPU_FEATURE_SSE␉␉␉0x00000002␉␉␉␉// SSE Instruction Set␊ |
50 | #define CPU_FEATURE_SSE2␉␉0x00000004␉␉␉␉// SSE2 Instruction Set␊ |
51 | #define CPU_FEATURE_SSE3␉␉0x00000008␉␉␉␉// SSE3 Instruction Set␊ |
52 | #define CPU_FEATURE_SSE41␉␉0x00000010␉␉␉␉// SSE41 Instruction Set␊ |
53 | #define CPU_FEATURE_SSE42␉␉0x00000020␉␉␉␉// SSE42 Instruction Set␊ |
54 | #define CPU_FEATURE_EM64T␉␉0x00000040␉␉␉␉// 64Bit Support␊ |
55 | #define CPU_FEATURE_HTT␉␉␉0x00000080␉␉␉␉// HyperThreading␊ |
56 | #define CPU_FEATURE_MOBILE␉␉0x00000100␉␉␉␉// Mobile CPU␊ |
57 | #define CPU_FEATURE_MSR␉␉␉0x00000200␉␉␉␉// MSR Support␊ |
58 | ␊ |
59 | /* SMBIOS Memory Types */ ␊ |
60 | #define SMB_MEM_TYPE_UNDEFINED␉0␊ |
61 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
62 | #define SMB_MEM_TYPE_UNKNOWN␉2␊ |
63 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
64 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
65 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
66 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
67 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
68 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
69 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
70 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
71 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
72 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
73 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
74 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
75 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
76 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
77 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
78 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
79 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
80 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
81 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
82 | ␊ |
83 | /* Memory Configuration Types */ ␊ |
84 | #define SMB_MEM_CHANNEL_UNKNOWN␉0␊ |
85 | #define SMB_MEM_CHANNEL_SINGLE␉1␊ |
86 | #define SMB_MEM_CHANNEL_DUAL␉2␊ |
87 | #define SMB_MEM_CHANNEL_TRIPLE␉3␊ |
88 | ␊ |
89 | /* Maximum number of ram slots */␊ |
90 | #define MAX_RAM_SLOTS␉␉␉8 //Azi: 8 or 12 ??␊ |
91 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
92 | ␊ |
93 | /* Maximum number of SPD bytes */␊ |
94 | #define MAX_SPD_SIZE␉␉␉256␊ |
95 | ␊ |
96 | /* Size of SMBIOS UUID in bytes */␊ |
97 | #define UUID_LEN␉␉␉␉16␊ |
98 | ␊ |
99 | typedef struct _RamSlotInfo_t␊ |
100 | {␊ |
101 | uint32_t␉␉␉␉␉ModuleSize;␉␉␉␉// Size of Module in MB␊ |
102 | uint32_t␉␉␉␉␉Frequency;␉␉␉␉// in Mhz␊ |
103 | const char*␉␉␉␉␉Vendor;␊ |
104 | const char*␉␉␉␉␉PartNo;␊ |
105 | const char*␉␉␉␉␉SerialNo;␊ |
106 | char*␉␉␉␉␉␉spd;␉␉␉␉␉// SPD Dump␊ |
107 | bool␉␉␉␉␉␉InUse;␊ |
108 | uint8_t␉␉␉␉␉␉Type;␊ |
109 | uint8_t␉␉␉␉␉␉BankConnections;␉␉// table type 6, see (3.3.7)␊ |
110 | uint8_t␉␉␉␉␉␉BankConnCnt;␊ |
111 | } RamSlotInfo_t;␊ |
112 | ␊ |
113 | typedef struct _PlatformInfo_t␊ |
114 | {␊ |
115 | ␉struct CPU␊ |
116 | ␉{␊ |
117 | ␉␉uint32_t␉␉␉␉Features;␉␉␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
118 | ␉␉uint32_t␉␉␉␉Vendor;␉␉␉␉␉// Vendor␊ |
119 | ␉␉uint32_t␉␉␉␉Signature;␉␉␉␉// Signature␊ |
120 | ␉␉uint32_t␉␉␉␉Stepping;␉␉␉␉// Stepping␊ |
121 | ␉␉uint32_t␉␉␉␉Model;␉␉␉␉␉// Model␊ |
122 | ␉␉uint32_t␉␉␉␉ExtModel;␉␉␉␉// Extended Model␊ |
123 | ␉␉uint32_t␉␉␉␉Family;␉␉␉␉␉// Family␊ |
124 | ␉␉uint32_t␉␉␉␉ExtFamily;␉␉␉␉// Extended Family␊ |
125 | ␉␉uint32_t␉␉␉␉NoCores;␉␉␉␉// No Cores per Package␊ |
126 | ␉␉uint32_t␉␉␉␉NoThreads;␉␉␉␉// Threads per Package␊ |
127 | ␉␉uint8_t␉␉␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊ |
128 | ␉␉uint8_t␉␉␉␉␉MaxDiv;␊ |
129 | ␉␉uint8_t␉␉␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊ |
130 | ␉␉uint8_t␉␉␉␉␉CurrDiv;␊ |
131 | ␉␉uint64_t␉␉␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊ |
132 | ␉␉uint64_t␉␉␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊ |
133 | ␉␉uint64_t␉␉␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊ |
134 | ␉␉uint32_t␉␉␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊ |
135 | ␉␉uint32_t␉␉␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊ |
136 | ␉␉char␉␉␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊ |
137 | ␉␉uint32_t␉␉␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
138 | ␉} CPU;␊ |
139 | ␊ |
140 | ␉struct RAM␊ |
141 | ␉{␊ |
142 | ␉␉uint64_t␉␉␉␉Frequency;␉␉␉␉// Ram Frequency␊ |
143 | ␉␉uint32_t␉␉␉␉Divider;␉␉␉␉// Memory divider␊ |
144 | ␉␉uint8_t␉␉␉␉␉CAS;␉␉␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
145 | ␉␉uint8_t␉␉␉␉␉TRC;␉␉␉␉␉␊ |
146 | ␉␉uint8_t␉␉␉␉␉TRP;␊ |
147 | ␉␉uint8_t␉␉␉␉␉RAS;␊ |
148 | ␉␉uint8_t␉␉␉␉␉Channels;␉␉␉␉// Channel Configuration Single,Dual or Triple␊ |
149 | ␉␉uint8_t␉␉␉␉␉NoSlots;␉␉␉␉// Maximum no of slots available␊ |
150 | ␉␉uint8_t␉␉␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
151 | ␉␉RamSlotInfo_t␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊ |
152 | ␉} RAM;␊ |
153 | ␊ |
154 | ␉struct DMI␊ |
155 | ␉{␊ |
156 | ␉␉int␉␉␉␉␉␉MaxMemorySlots;␉␉␉// number of memory slots polulated by SMBIOS␊ |
157 | ␉␉int␉␉␉␉␉␉CntMemorySlots;␉␉␉// number of memory slots counted␊ |
158 | ␉␉int␉␉␉␉␉␉MemoryModules;␉␉␉// number of memory modules installed␊ |
159 | ␉␉int␉␉␉␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
160 | ␉} DMI;␊ |
161 | ␉uint8_t␉␉␉␉␉␉Type;␉␉␉␉␉// System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊ |
162 | ␉uint8_t␉␉␉␉␉␉*UUID;␊ |
163 | } PlatformInfo_t;␊ |
164 | ␊ |
165 | extern PlatformInfo_t Platform;␊ |
166 | ␊ |
167 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
168 | |