1 | /*␊ |
2 | * Copyright (c) 2000-2006 Apple Computer, Inc. All rights reserved.␊ |
3 | *␊ |
4 | * @APPLE_OSREFERENCE_LICENSE_HEADER_START@␊ |
5 | *␊ |
6 | * This file contains Original Code and/or Modifications of Original Code␊ |
7 | * as defined in and that are subject to the Apple Public Source License␊ |
8 | * Version 2.0 (the 'License'). You may not use this file except in␊ |
9 | * compliance with the License. The rights granted to you under the License␊ |
10 | * may not be used to create, or enable the creation or redistribution of,␊ |
11 | * unlawful or unlicensed copies of an Apple operating system, or to␊ |
12 | * circumvent, violate, or enable the circumvention or violation of, any␊ |
13 | * terms of an Apple operating system software license agreement.␊ |
14 | *␊ |
15 | * Please obtain a copy of the License at␊ |
16 | * http://www.opensource.apple.com/apsl/ and read it before using this file.␊ |
17 | *␊ |
18 | * The Original Code and all software distributed under the License are␊ |
19 | * distributed on an 'AS IS' basis, WITHOUT WARRANTY OF ANY KIND, EITHER␊ |
20 | * EXPRESS OR IMPLIED, AND APPLE HEREBY DISCLAIMS ALL SUCH WARRANTIES,␊ |
21 | * INCLUDING WITHOUT LIMITATION, ANY WARRANTIES OF MERCHANTABILITY,␊ |
22 | * FITNESS FOR A PARTICULAR PURPOSE, QUIET ENJOYMENT OR NON-INFRINGEMENT.␊ |
23 | * Please see the License for the specific language governing rights and␊ |
24 | * limitations under the License.␊ |
25 | *␊ |
26 | * @APPLE_OSREFERENCE_LICENSE_HEADER_END@␊ |
27 | */␊ |
28 | /*␊ |
29 | * @OSF_COPYRIGHT@␊ |
30 | */␊ |
31 | /*␊ |
32 | * Copyright 2008 Islam Ahmed Zaid. All rights reserved. <azismed@gmail.com>␊ |
33 | * AsereBLN: 2009: cleanup and bugfix␊ |
34 | */␊ |
35 | ␊ |
36 | #include "libsaio.h"␊ |
37 | #include "platform.h"␊ |
38 | #include "cpu.h"␊ |
39 | #include "bootstruct.h"␊ |
40 | #include "boot.h"␊ |
41 | ␊ |
42 | #ifndef DEBUG_CPU␊ |
43 | #define DEBUG_CPU 0␊ |
44 | #endif␊ |
45 | ␊ |
46 | #if DEBUG_CPU␊ |
47 | #define DBG(x...)␉␉printf(x)␊ |
48 | #else␊ |
49 | #define DBG(x...)␉␉msglog(x)␊ |
50 | #endif␊ |
51 | ␊ |
52 | /*␊ |
53 | * timeRDTSC()␊ |
54 | * This routine sets up PIT counter 2 to count down 1/20 of a second.␊ |
55 | * It pauses until the value is latched in the counter␊ |
56 | * and then reads the time stamp counter to return to the caller.␊ |
57 | */␊ |
58 | uint64_t timeRDTSC(void)␊ |
59 | {␊ |
60 | ␉int␉␉attempts = 0;␊ |
61 | ␉uint64_t latchTime;␊ |
62 | ␉uint64_t␉saveTime,intermediate;␊ |
63 | ␉unsigned int timerValue, lastValue;␊ |
64 | ␉//boolean_t␉int_enabled;␊ |
65 | ␉/*␊ |
66 | ␉ * Table of correction factors to account for␊ |
67 | ␉ *␉ - timer counter quantization errors, and␊ |
68 | ␉ *␉ - undercounts 0..5␊ |
69 | ␉ */␊ |
70 | #define SAMPLE_CLKS_EXACT␉(((double) CLKNUM) / 20.0)␊ |
71 | #define SAMPLE_CLKS_INT␉␉((int) CLKNUM / 20)␊ |
72 | #define SAMPLE_NSECS␉␉(2000000000LL)␊ |
73 | #define SAMPLE_MULTIPLIER␉(((double)SAMPLE_NSECS)*SAMPLE_CLKS_EXACT)␊ |
74 | #define ROUND64(x)␉␉((uint64_t)((x) + 0.5))␊ |
75 | ␉uint64_t␉scale[6] = {␊ |
76 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-0)), ␊ |
77 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-1)), ␊ |
78 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-2)), ␊ |
79 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-3)), ␊ |
80 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-4)), ␊ |
81 | ␉␉ROUND64(SAMPLE_MULTIPLIER/(double)(SAMPLE_CLKS_INT-5))␊ |
82 | ␉};␊ |
83 | ␊ |
84 | ␉//int_enabled = ml_set_interrupts_enabled(FALSE);␊ |
85 | ␊ |
86 | restart:␊ |
87 | ␉if (attempts >= 9) // increase to up to 9 attempts.␊ |
88 | ␉{␊ |
89 | ␉ // This will flash-reboot. TODO: Use tscPanic instead.␊ |
90 | ␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊ |
91 | ␉}␊ |
92 | ␉attempts++;␊ |
93 | ␉enable_PIT2();␉␉// turn on PIT2␊ |
94 | ␉set_PIT2(0);␉␉// reset timer 2 to be zero␊ |
95 | ␉latchTime = rdtsc64();␉// get the time stamp to time ␊ |
96 | ␉latchTime = get_PIT2(&timerValue) - latchTime; // time how long this takes␊ |
97 | ␉set_PIT2(SAMPLE_CLKS_INT);␉// set up the timer for (almost) 1/20th a second␊ |
98 | ␉saveTime = rdtsc64();␉// now time how long a 20th a second is...␊ |
99 | ␉get_PIT2(&lastValue);␊ |
100 | ␉get_PIT2(&lastValue);␉// read twice, first value may be unreliable␊ |
101 | ␉do {␊ |
102 | ␉␉intermediate = get_PIT2(&timerValue);␊ |
103 | ␉␉if (timerValue > lastValue)␊ |
104 | ␉␉{␊ |
105 | ␉␉␉// Timer wrapped␊ |
106 | ␉␉␉set_PIT2(0);␊ |
107 | ␉␉␉disable_PIT2();␊ |
108 | ␉␉␉goto restart;␊ |
109 | ␉␉}␊ |
110 | ␉␉lastValue = timerValue;␊ |
111 | ␉} while (timerValue > 5);␊ |
112 | ␉printf("timerValue␉ %d\n",timerValue);␊ |
113 | ␉printf("intermediate 0x%016llX\n",intermediate);␊ |
114 | ␉printf("saveTime␉ 0x%016llX\n",saveTime);␊ |
115 | ␊ |
116 | ␉intermediate -= saveTime;␉␉// raw count for about 1/20 second␊ |
117 | ␉intermediate *= scale[timerValue];␉// rescale measured time spent␊ |
118 | ␉intermediate /= SAMPLE_NSECS;␉// so its exactly 1/20 a second␊ |
119 | ␉intermediate += latchTime;␉␉// add on our save fudge␊ |
120 | ␊ |
121 | ␉set_PIT2(0);␉␉␉// reset timer 2 to be zero␊ |
122 | ␉disable_PIT2();␉␉␉// turn off PIT 2␊ |
123 | ␊ |
124 | ␉//ml_set_interrupts_enabled(int_enabled);␊ |
125 | ␉return intermediate;␊ |
126 | }␊ |
127 | ␊ |
128 | /*␊ |
129 | * DFE: Measures the TSC frequency in Hz (64-bit) using the ACPI PM timer␊ |
130 | */␊ |
131 | static uint64_t measure_tsc_frequency(void)␊ |
132 | {␊ |
133 | ␉uint64_t tscStart;␊ |
134 | ␉uint64_t tscEnd;␊ |
135 | ␉uint64_t tscDelta = 0xffffffffffffffffULL;␊ |
136 | ␉unsigned long pollCount;␊ |
137 | ␉uint64_t retval = 0;␊ |
138 | ␉int i;␊ |
139 | ␊ |
140 | ␉/* Time how many TSC ticks elapse in 30 msec using the 8254 PIT␊ |
141 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
142 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
143 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
144 | ␉ * number of TSC ticks that occur while waiting for the timer to␊ |
145 | ␉ * expire. That theoretically helps avoid inconsistencies when␊ |
146 | ␉ * running under a VM if the TSC is not virtualized and the host␊ |
147 | ␉ * steals time.␉ The TSC is normally virtualized for VMware.␊ |
148 | ␉ */␊ |
149 | ␉for(i = 0; i < 10; ++i)␊ |
150 | ␉{␊ |
151 | ␉␉enable_PIT2();␊ |
152 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
153 | ␉␉tscStart = rdtsc64();␊ |
154 | ␉␉pollCount = poll_PIT2_gate();␊ |
155 | ␉␉tscEnd = rdtsc64();␊ |
156 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
157 | ␉␉if (pollCount <= 1) {␊ |
158 | ␉␉␉continue;␊ |
159 | ␉␉}␊ |
160 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
161 | ␉␉ * We should have waited exactly 30 msec so the TSC delta should␊ |
162 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
163 | ␉␉ */␊ |
164 | ␉␉if ((tscEnd - tscStart) <= CALIBRATE_TIME_MSEC) {␊ |
165 | ␉␉␉continue;␊ |
166 | ␉␉}␊ |
167 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
168 | ␉␉if ( (tscEnd - tscStart) < tscDelta ) {␊ |
169 | ␉␉␉tscDelta = tscEnd - tscStart;␊ |
170 | ␉␉}␊ |
171 | ␉}␊ |
172 | ␉/* tscDelta is now the least number of TSC ticks the processor made in␊ |
173 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
174 | ␉ * Linux thus divides by 30 which gives the answer in kiloHertz because␊ |
175 | ␉ * 1 / ms = kHz. But we're xnu and most of the rest of the code uses␊ |
176 | ␉ * Hz so we need to convert our milliseconds to seconds. Since we're␊ |
177 | ␉ * dividing by the milliseconds, we simply multiply by 1000.␊ |
178 | ␉ */␊ |
179 | ␊ |
180 | ␉/* Unlike linux, we're not limited to 32-bit, but we do need to take care␊ |
181 | ␉ * that we're going to multiply by 1000 first so we do need at least some␊ |
182 | ␉ * arithmetic headroom. For now, 32-bit should be enough.␊ |
183 | ␉ * Also unlike Linux, our compiler can do 64-bit integer arithmetic.␊ |
184 | ␉ */␊ |
185 | ␉if (tscDelta > (1ULL<<32)) {␊ |
186 | ␉␉retval = 0;␊ |
187 | ␉} else {␊ |
188 | ␉␉retval = tscDelta * 1000 / 30;␊ |
189 | ␉}␊ |
190 | ␉disable_PIT2();␊ |
191 | ␉return retval;␊ |
192 | }␊ |
193 | ␊ |
194 | /*␊ |
195 | * Original comment/code:␊ |
196 | * "DFE: Measures the Max Performance Frequency in Hz (64-bit)"␊ |
197 | *␊ |
198 | * Measures the Actual Performance Frequency in Hz (64-bit)␊ |
199 | * (just a naming change, mperf --> aperf )␊ |
200 | */␊ |
201 | static uint64_t measure_aperf_frequency(void)␊ |
202 | {␊ |
203 | ␉uint64_t aperfStart;␊ |
204 | ␉uint64_t aperfEnd;␊ |
205 | ␉uint64_t aperfDelta = 0xffffffffffffffffULL;␊ |
206 | ␉unsigned long pollCount;␊ |
207 | ␉uint64_t retval = 0;␊ |
208 | ␉int i;␊ |
209 | ␊ |
210 | ␉/* Time how many APERF ticks elapse in 30 msec using the 8254 PIT␊ |
211 | ␉ * counter 2. We run this loop 3 times to make sure the cache␊ |
212 | ␉ * is hot and we take the minimum delta from all of the runs.␊ |
213 | ␉ * That is to say that we're biased towards measuring the minimum␊ |
214 | ␉ * number of APERF ticks that occur while waiting for the timer to␊ |
215 | ␉ * expire.␊ |
216 | ␉ */␊ |
217 | ␉for(i = 0; i < 10; ++i)␊ |
218 | ␉{␊ |
219 | ␉␉enable_PIT2();␊ |
220 | ␉␉set_PIT2_mode0(CALIBRATE_LATCH);␊ |
221 | ␉␉aperfStart = rdmsr64(MSR_AMD_APERF);␊ |
222 | ␉␉pollCount = poll_PIT2_gate();␊ |
223 | ␉␉aperfEnd = rdmsr64(MSR_AMD_APERF);␊ |
224 | ␉␉/* The poll loop must have run at least a few times for accuracy */␊ |
225 | ␉␉if (pollCount <= 1)␊ |
226 | ␉␉{␊ |
227 | ␉␉␉continue;␊ |
228 | ␉␉}␊ |
229 | ␉␉/* The TSC must increment at LEAST once every millisecond.␊ |
230 | ␉␉ * We should have waited exactly 30 msec so the APERF delta should␊ |
231 | ␉␉ * be >= 30. Anything less and the processor is way too slow.␊ |
232 | ␉␉ */␊ |
233 | ␉␉if ((aperfEnd - aperfStart) <= CALIBRATE_TIME_MSEC)␊ |
234 | ␉␉{␊ |
235 | ␉␉␉continue;␊ |
236 | ␉␉}␊ |
237 | ␉␉// tscDelta = MIN(tscDelta, (tscEnd - tscStart))␊ |
238 | ␉␉if ( (aperfEnd - aperfStart) < aperfDelta )␊ |
239 | ␉␉{␊ |
240 | ␉␉␉aperfDelta = aperfEnd - aperfStart;␊ |
241 | ␉␉}␊ |
242 | ␉}␊ |
243 | ␉/* mperfDelta is now the least number of MPERF ticks the processor made in␊ |
244 | ␉ * a timespan of 0.03 s (e.g. 30 milliseconds)␊ |
245 | ␉ */␊ |
246 | ␊ |
247 | ␉if (aperfDelta > (1ULL<<32))␊ |
248 | ␉{␊ |
249 | ␉␉retval = 0;␊ |
250 | ␉}␊ |
251 | ␉else␊ |
252 | ␉{␊ |
253 | ␉␉retval = aperfDelta * 1000 / 30;␊ |
254 | ␉}␊ |
255 | ␉disable_PIT2();␊ |
256 | ␉return retval;␊ |
257 | }␊ |
258 | ␊ |
259 | /*␊ |
260 | * Calculates the FSB and CPU frequencies using specific MSRs for each CPU␊ |
261 | * - multi. is read from a specific MSR. In the case of Intel, there is:␊ |
262 | *␉ a max multi. (used to calculate the FSB freq.),␊ |
263 | *␉ and a current multi. (used to calculate the CPU freq.)␊ |
264 | * - fsbFrequency = tscFrequency / multi␊ |
265 | * - cpuFrequency = fsbFrequency * multi␊ |
266 | */␊ |
267 | void scan_cpu(PlatformInfo_t *p)␊ |
268 | {␊ |
269 | ␉uint64_t␉tscFrequency = 0;␊ |
270 | ␉uint64_t␉fsbFrequency = 0;␊ |
271 | ␉uint64_t␉cpuFrequency = 0;␊ |
272 | ␉uint64_t␉msr = 0;␊ |
273 | ␉uint64_t␉flex_ratio = 0;␊ |
274 | ␊ |
275 | ␉uint32_t␉max_ratio = 0;␊ |
276 | ␉uint32_t␉min_ratio = 0;␊ |
277 | ␉uint32_t␉reg[4];␊ |
278 | ␉uint32_t␉cores_per_package = 0;␊ |
279 | ␉uint32_t␉logical_per_package = 1;␊ |
280 | ␉uint32_t␉threads_per_core = 1;;␊ |
281 | ␊ |
282 | ␉uint8_t␉␉bus_ratio_max = 0;␊ |
283 | ␉uint8_t␉␉bus_ratio_min = 0;␊ |
284 | ␉uint8_t␉␉currdiv = 0;␊ |
285 | ␉uint8_t␉␉currcoef = 0;␊ |
286 | ␉uint8_t␉␉maxdiv = 0;␊ |
287 | ␉uint8_t␉␉maxcoef = 0;␊ |
288 | ␊ |
289 | ␉const char␉*newratio;␊ |
290 | ␉char␉␉str[128];␊ |
291 | ␉char␉␉*s = 0;␊ |
292 | ␊ |
293 | ␉int␉␉len = 0;␊ |
294 | ␉int␉␉myfsb = 0;␊ |
295 | ␉int␉␉i = 0;␊ |
296 | ␊ |
297 | ␉/* get cpuid values */␊ |
298 | ␉do_cpuid(0x00000000, p->CPU.CPUID[CPUID_0]); // MaxFn, Vendor␊ |
299 | ␉p->CPU.Vendor = p->CPU.CPUID[CPUID_0][ebx];␊ |
300 | ␊ |
301 | ␉do_cpuid(0x00000001, p->CPU.CPUID[CPUID_1]); // Signature, stepping, features␊ |
302 | ␊ |
303 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && ((bit(28) & p->CPU.CPUID[CPUID_1][edx]) != 0)) // Intel && HTT/Multicore␊ |
304 | ␉{␊ |
305 | ␉␉logical_per_package = bitfield(p->CPU.CPUID[CPUID_1][ebx], 23, 16);␊ |
306 | ␉}␊ |
307 | ␊ |
308 | ␉do_cpuid(0x00000002, p->CPU.CPUID[CPUID_2]); // TLB/Cache/Prefetch␊ |
309 | ␊ |
310 | ␉do_cpuid(0x00000003, p->CPU.CPUID[CPUID_3]); // S/N␊ |
311 | ␊ |
312 | ␉/* Based on Apple's XNU cpuid.c - Deterministic cache parameters */␊ |
313 | ␉if ((p->CPU.CPUID[CPUID_0][eax] > 3) && (p->CPU.CPUID[CPUID_0][eax] < 0x80000000))␊ |
314 | ␉{␊ |
315 | ␉␉for (i = 0; i < 0xFF; i++) // safe loop␊ |
316 | ␉␉{␊ |
317 | ␉␉␉do_cpuid2(0x00000004, i, reg); // AX=4: Fn, CX=i: cache index␊ |
318 | ␉␉␉if (bitfield(reg[eax], 4, 0) == 0)␊ |
319 | ␉␉␉{␊ |
320 | ␉␉␉␉break;␊ |
321 | ␉␉␉}␊ |
322 | ␉␉␉//cores_per_package = bitfield(reg[eax], 31, 26) + 1;␊ |
323 | ␉␉}␊ |
324 | ␉}␊ |
325 | ␉do_cpuid2(0x00000004, 0, p->CPU.CPUID[CPUID_4]);␊ |
326 | ␉if (i > 0)␊ |
327 | ␉{␊ |
328 | ␉␉cores_per_package = bitfield(p->CPU.CPUID[CPUID_4][eax], 31, 26) + 1; // i = cache index␊ |
329 | ␉␉threads_per_core = bitfield(p->CPU.CPUID[CPUID_4][eax], 25, 14) + 1;␊ |
330 | ␉}␊ |
331 | ␊ |
332 | ␉if (cores_per_package == 0) cores_per_package = 1;␊ |
333 | ␊ |
334 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 0x5) // Monitor/Mwait␊ |
335 | ␉{␊ |
336 | ␉␉do_cpuid(5, p->CPU.CPUID[CPUID_5]);␊ |
337 | ␉}␊ |
338 | ␉if (p->CPU.CPUID[CPUID_0][0] >= 6) // Thermal/Power␊ |
339 | ␉{␊ |
340 | ␉␉do_cpuid(6, p->CPU.CPUID[CPUID_6]);␊ |
341 | ␉}␊ |
342 | ␊ |
343 | ␉do_cpuid(0x80000000, p->CPU.CPUID[CPUID_80]);␊ |
344 | ␉if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 8)␊ |
345 | ␉{␊ |
346 | ␉␉do_cpuid(0x80000008, p->CPU.CPUID[CPUID_88]);␊ |
347 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
348 | ␉}␊ |
349 | ␉else if ((p->CPU.CPUID[CPUID_80][0] & 0x0000000f) >= 1)␊ |
350 | ␉{␊ |
351 | ␉␉do_cpuid(0x80000001, p->CPU.CPUID[CPUID_81]);␊ |
352 | ␉}␊ |
353 | ␊ |
354 | /*␊ |
355 | EAX (Intel):␊ |
356 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
357 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
358 | |########|Extended family |Extmodel|####|type|familyid| model |stepping|␊ |
359 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
360 | ␊ |
361 | EAX (AMD):␊ |
362 | 31 28 27 20 19 16 1514 1312 11 8 7 4 3 0␊ |
363 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
364 | |########|Extended family |Extmodel|####|####|familyid| model |stepping|␊ |
365 | +--------+----------------+--------+----+----+--------+--------+--------+␊ |
366 | */␊ |
367 | ␉p->CPU.Signature␉= p->CPU.CPUID[CPUID_1][0];␊ |
368 | ␉// stepping = cpu_feat_eax & 0xF;␊ |
369 | ␉p->CPU.Stepping␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 3, 0);␊ |
370 | ␉// model = (cpu_feat_eax >> 4) & 0xF;␊ |
371 | ␉p->CPU.Model␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 7, 4);␊ |
372 | ␉// family = (cpu_feat_eax >> 8) & 0xF;␊ |
373 | ␉p->CPU.Family␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 11, 8);␊ |
374 | ␉// type = (cpu_feat_eax >> 12) & 0x3;␊ |
375 | ␉//p->CPU.Type␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 13, 12);␊ |
376 | ␉// ext_model = (cpu_feat_eax >> 16) & 0xF;␊ |
377 | ␉p->CPU.ExtModel␉␉= bitfield(p->CPU.CPUID[CPUID_1][0], 19, 16);␊ |
378 | ␉// ext_family = (cpu_feat_eax >> 20) & 0xFF;␊ |
379 | ␉p->CPU.ExtFamily␉= bitfield(p->CPU.CPUID[CPUID_1][0], 27, 20);␊ |
380 | /*␊ |
381 | ␉if (p->CPU.Family == 0x0f)␊ |
382 | ␉{␊ |
383 | ␉␉p->CPU.Family += p->CPU.ExtFamily;␊ |
384 | ␉}␊ |
385 | ␊ |
386 | ␉if (p->CPU.Family == 0x0f || p->CPU.Family == 0x06)␊ |
387 | */␊ |
388 | ␉p->CPU.Model += (p->CPU.ExtModel << 4);␊ |
389 | ␊ |
390 | ␉/* get BrandString (if supported) */␊ |
391 | ␉/* Copyright: from Apple's XNU cpuid.c */␊ |
392 | ␉if (p->CPU.CPUID[CPUID_80][0] > 0x80000004)␊ |
393 | ␉{␊ |
394 | ␉␉bzero(str, 128);␊ |
395 | ␉␉/*␊ |
396 | ␉␉ * The brand string 48 bytes (max), guaranteed to␊ |
397 | ␉␉ * be NULL terminated.␊ |
398 | ␉␉ */␊ |
399 | ␉␉do_cpuid(0x80000002, reg);␊ |
400 | ␉␉memcpy(&str[0], (char *)reg, 16);␊ |
401 | ␉␉do_cpuid(0x80000003, reg);␊ |
402 | ␉␉memcpy(&str[16], (char *)reg, 16);␊ |
403 | ␉␉do_cpuid(0x80000004, reg);␊ |
404 | ␉␉memcpy(&str[32], (char *)reg, 16);␊ |
405 | ␉␉for (s = str; *s != '\0'; s++)␊ |
406 | ␉␉{␊ |
407 | ␉␉␉if (*s != ' ')␊ |
408 | ␉␉␉{␊ |
409 | ␉␉␉␉break;␊ |
410 | ␉␉␉}␊ |
411 | ␉␉}␊ |
412 | ␉␉strlcpy(p->CPU.BrandString, s, 48);␊ |
413 | ␊ |
414 | ␉␉if (!strncmp(p->CPU.BrandString, CPU_STRING_UNKNOWN, MIN(sizeof(p->CPU.BrandString), (unsigned)strlen(CPU_STRING_UNKNOWN) + 1)))␊ |
415 | ␉␉{␊ |
416 | ␉␉␉/*␊ |
417 | ␉␉␉ * This string means we have a firmware-programmable brand string,␊ |
418 | ␉␉␉ * and the firmware couldn't figure out what sort of CPU we have.␊ |
419 | ␉␉␉ */␊ |
420 | ␉␉␉p->CPU.BrandString[0] = '\0';␊ |
421 | ␉␉}␊ |
422 | ␉␉p->CPU.BrandString[47] = '\0';␊ |
423 | //␉␉verbose("Brandstring = %s\n", p->CPU.BrandString);␊ |
424 | ␉}␊ |
425 | ␊ |
426 | ␉/*␊ |
427 | ␉ * Find the number of enabled cores and threads␊ |
428 | ␉ * (which determines whether SMT/Hyperthreading is active).␊ |
429 | ␉ */␊ |
430 | ␉switch (p->CPU.Vendor)␊ |
431 | ␉{␊ |
432 | ␉␉case CPUID_VENDOR_INTEL:␊ |
433 | ␉␉␉switch (p->CPU.Model)␊ |
434 | ␉␉␉{␊ |
435 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
436 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
437 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
438 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
439 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
440 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
441 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
442 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊ |
443 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
444 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
445 | ␉␉␉␉//case CPUID_MODEL_HASWELL_H:␊ |
446 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
447 | ␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
448 | ␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
449 | ␉␉␉␉␉p->CPU.NoCores␉␉= (uint32_t)bitfield((uint32_t)msr, 31, 16);␊ |
450 | ␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
451 | ␉␉␉␉break;␊ |
452 | ␊ |
453 | ␉␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
454 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
455 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
456 | ␉␉␉␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␊ |
457 | ␉␉␉␉␉p->CPU.NoCores␉= (uint32_t)bitfield((uint32_t)msr, 19, 16);␊ |
458 | ␉␉␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield((uint32_t)msr, 15, 0);␊ |
459 | ␉␉␉␉break;␊ |
460 | ␉␉␉}␊ |
461 | ␊ |
462 | ␉␉␉if (p->CPU.NoCores == 0)␊ |
463 | ␉␉␉{␊ |
464 | ␉␉␉␉p->CPU.NoCores = cores_per_package;␊ |
465 | ␉␉␉␉p->CPU.NoThreads = logical_per_package;␊ |
466 | ␉␉␉}␊ |
467 | break;␊ |
468 | ␊ |
469 | ␉␉case CPUID_VENDOR_AMD:␊ |
470 | ␉␉␉p->CPU.NoCores␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_88][2], 7, 0) + 1;␊ |
471 | ␉␉␉p->CPU.NoThreads␉= (uint32_t)bitfield(p->CPU.CPUID[CPUID_1][1], 23, 16);␊ |
472 | ␉␉␉if (p->CPU.NoCores == 0)␊ |
473 | ␉␉␉␉p->CPU.NoCores = 1;␊ |
474 | ␉␉␉if (p->CPU.NoThreads < p->CPU.NoCores)␊ |
475 | ␉␉␉␉p->CPU.NoThreads = p->CPU.NoCores;␊ |
476 | ␉␉␉break;␊ |
477 | ␊ |
478 | ␉␉default:␊ |
479 | ␉␉␉stop("Unsupported CPU detected! System halted.");␊ |
480 | ␉␉}␊ |
481 | ␊ |
482 | ␉␉//workaround for N270. I don't know why it detected wrong␊ |
483 | ␉␉// MSR is *NOT* available on the Intel Atom CPU␊ |
484 | ␉␉if ((p->CPU.Model == CPUID_MODEL_ATOM) && (strstr(p->CPU.BrandString, "270")))␊ |
485 | ␉␉{␊ |
486 | ␉␉␉p->CPU.NoCores␉␉= 1;␊ |
487 | ␉␉␉p->CPU.NoThreads␉= 2;␊ |
488 | ␉␉}␊ |
489 | ␊ |
490 | ␉/* setup features */␊ |
491 | ␉if ((bit(23) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
492 | ␉{␊ |
493 | ␉␉p->CPU.Features |= CPU_FEATURE_MMX;␊ |
494 | ␉}␊ |
495 | ␊ |
496 | ␉if ((bit(25) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
497 | ␉{␊ |
498 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE;␊ |
499 | ␉}␊ |
500 | ␊ |
501 | ␉if ((bit(26) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
502 | ␉{␊ |
503 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE2;␊ |
504 | ␉}␊ |
505 | ␊ |
506 | ␉if ((bit(0) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
507 | ␉{␊ |
508 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE3;␊ |
509 | ␉}␊ |
510 | ␊ |
511 | ␉if ((bit(19) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
512 | ␉{␊ |
513 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE41;␊ |
514 | ␉}␊ |
515 | ␊ |
516 | ␉if ((bit(20) & p->CPU.CPUID[CPUID_1][2]) != 0)␊ |
517 | ␉{␊ |
518 | ␉␉p->CPU.Features |= CPU_FEATURE_SSE42;␊ |
519 | ␉}␊ |
520 | ␊ |
521 | ␉if ((bit(29) & p->CPU.CPUID[CPUID_81][3]) != 0)␊ |
522 | ␉{␊ |
523 | ␉␉p->CPU.Features |= CPU_FEATURE_EM64T;␊ |
524 | ␉}␊ |
525 | ␊ |
526 | ␉if ((bit(5) & p->CPU.CPUID[CPUID_1][3]) != 0)␊ |
527 | ␉{␊ |
528 | ␉␉p->CPU.Features |= CPU_FEATURE_MSR;␊ |
529 | ␉}␊ |
530 | ␊ |
531 | ␉if ((p->CPU.Vendor == CPUID_VENDOR_INTEL) && (p->CPU.NoThreads > p->CPU.NoCores))␊ |
532 | ␉{␊ |
533 | ␉␉p->CPU.Features |= CPU_FEATURE_HTT;␊ |
534 | ␉}␊ |
535 | ␊ |
536 | ␉tscFrequency = measure_tsc_frequency();␊ |
537 | ␉//verbose("cpu freq classic = 0x%016llx\n", tscFrequency);␊ |
538 | ␊ |
539 | ␉/* if usual method failed */␊ |
540 | ␉if ( tscFrequency < 1000 )␉//TEST␊ |
541 | ␉{␊ |
542 | ␉␉tscFrequency = timeRDTSC() * 20;//measure_tsc_frequency();␊ |
543 | ␉␉//verbose("cpu freq timeRDTSC = 0x%016llx\n", tscFrequency);␊ |
544 | ␉}␊ |
545 | ␉else␊ |
546 | ␉{␊ |
547 | ␉␉// verbose("cpu freq timeRDTSC = 0x%016llxn", timeRDTSC() * 20);␊ |
548 | ␉}␊ |
549 | ␊ |
550 | ␉fsbFrequency = 0;␊ |
551 | ␉cpuFrequency = 0;␊ |
552 | ␊ |
553 | ␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL && ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0c) || (p->CPU.Family == 0x0f && p->CPU.Model >= 0x03)))␊ |
554 | ␉{␊ |
555 | ␉␉int intelCPU = p->CPU.Model;␊ |
556 | ␉␉if (p->CPU.Family == 0x06)␊ |
557 | ␉␉{␊ |
558 | ␉␉␉/* Nehalem CPU model */␊ |
559 | ␉␉␉switch (p->CPU.Model)␊ |
560 | ␉␉␉{␊ |
561 | ␉␉␉␉case CPUID_MODEL_NEHALEM:␊ |
562 | ␉␉␉␉case CPUID_MODEL_FIELDS:␊ |
563 | ␉␉␉␉case CPUID_MODEL_DALES:␊ |
564 | ␉␉␉␉case CPUID_MODEL_DALES_32NM:␊ |
565 | ␉␉␉␉case CPUID_MODEL_WESTMERE:␊ |
566 | ␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␊ |
567 | ␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␊ |
568 | /* --------------------------------------------------------- */␊ |
569 | ␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
570 | ␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
571 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE_EP:␊ |
572 | ␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
573 | ␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
574 | ␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
575 | ␊ |
576 | ␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
577 | ␉␉␉␉case CPUID_MODEL_CRYSTALWELL:␊ |
578 | /* --------------------------------------------------------- */␊ |
579 | ␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊ |
580 | ␉␉␉␉//verbose("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
581 | ␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊ |
582 | ␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊ |
583 | ␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
584 | ␉␉␉␉//verbose("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
585 | ␉␉␉␉if (bitfield(msr, 16, 16))␊ |
586 | ␉␉␉␉{␊ |
587 | ␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊ |
588 | ␊ |
589 | ␉␉␉␉␉// bcc9: at least on the gigabyte h67ma-ud2h,␊ |
590 | ␉␉␉␉␉// where the cpu multipler can't be changed to␊ |
591 | ␉␉␉␉␉// allow overclocking, the flex_ratio msr has unexpected (to OSX)␊ |
592 | ␉␉␉␉␉// contents.␉These contents cause mach_kernel to␊ |
593 | ␉␉␉␉␉// fail to compute the bus ratio correctly, instead␊ |
594 | ␉␉␉␉␉// causing the system to crash since tscGranularity␊ |
595 | ␉␉␉␉␉// is inadvertently set to 0.␊ |
596 | ␉␉␉␉␉if (flex_ratio == 0)␊ |
597 | ␉␉␉␉␉{␊ |
598 | ␉␉␉␉␉␉// Clear bit 16 (evidently the presence bit)␊ |
599 | ␉␉␉␉␉␉wrmsr64(MSR_FLEX_RATIO, (msr & 0xFFFFFFFFFFFEFFFFULL));␊ |
600 | ␉␉␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊ |
601 | ␉␉␉␉␉␉verbose("CPU: Unusable flex ratio detected. Patched MSR now %08x\n", bitfield(msr, 31, 0));␊ |
602 | ␉␉␉␉␉}␊ |
603 | ␉␉␉␉␉else␊ |
604 | ␉␉␉␉␉{␊ |
605 | ␉␉␉␉␉␉if (bus_ratio_max > flex_ratio)␊ |
606 | ␉␉␉␉␉␉{␊ |
607 | ␉␉␉␉␉␉␉bus_ratio_max = flex_ratio;␊ |
608 | ␉␉␉␉␉␉}␊ |
609 | ␉␉␉␉␉}␊ |
610 | ␉␉␉␉}␊ |
611 | ␊ |
612 | ␉␉␉␉if (bus_ratio_max)␊ |
613 | ␉␉␉␉{␊ |
614 | ␉␉␉␉␉fsbFrequency = (tscFrequency / bus_ratio_max);␊ |
615 | ␉␉␉␉}␊ |
616 | ␊ |
617 | ␉␉␉␉//valv: Turbo Ratio Limit␊ |
618 | ␉␉␉␉if ((intelCPU != 0x2e) && (intelCPU != 0x2f))␊ |
619 | ␉␉␉␉{␊ |
620 | ␉␉␉␉␉msr = rdmsr64(MSR_TURBO_RATIO_LIMIT);␊ |
621 | ␊ |
622 | ␉␉␉␉␉cpuFrequency = bus_ratio_max * fsbFrequency;␊ |
623 | ␉␉␉␉␉max_ratio = bus_ratio_max * 10;␊ |
624 | ␉␉␉␉}␊ |
625 | ␉␉␉␉else␊ |
626 | ␉␉␉␉{␊ |
627 | ␉␉␉␉␉cpuFrequency = tscFrequency;␊ |
628 | ␉␉␉␉}␊ |
629 | ␉␉␉␉if ((getValueForKey(kbusratio, &newratio, &len, &bootInfo->chameleonConfig)) && (len <= 4))␊ |
630 | ␉␉␉␉{␊ |
631 | ␉␉␉␉␉max_ratio = atoi(newratio);␊ |
632 | ␉␉␉␉␉max_ratio = (max_ratio * 10);␊ |
633 | ␉␉␉␉␉if (len >= 3)␊ |
634 | ␉␉␉␉␉{␊ |
635 | ␉␉␉␉␉␉max_ratio = (max_ratio + 5);␊ |
636 | ␉␉␉␉␉}␊ |
637 | ␊ |
638 | ␉␉␉␉␉//verbose("Bus-Ratio: min=%d, max=%s\n", bus_ratio_min, newratio);␊ |
639 | ␊ |
640 | ␉␉␉␉␉// extreme overclockers may love 320 ;)␊ |
641 | ␉␉␉␉␉if ((max_ratio >= min_ratio) && (max_ratio <= 320))␊ |
642 | ␉␉␉␉␉{␊ |
643 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * max_ratio) / 10;␊ |
644 | ␉␉␉␉␉␉if (len >= 3)␊ |
645 | ␉␉␉␉␉␉{␊ |
646 | ␉␉␉␉␉␉␉maxdiv = 1;␊ |
647 | ␉␉␉␉␉␉}␊ |
648 | ␉␉␉␉␉␉else␊ |
649 | ␉␉␉␉␉␉{␊ |
650 | ␉␉␉␉␉␉␉maxdiv = 0;␊ |
651 | ␉␉␉␉␉␉}␊ |
652 | ␉␉␉␉␉}␊ |
653 | ␉␉␉␉␉else␊ |
654 | ␉␉␉␉␉{␊ |
655 | ␉␉␉␉␉␉max_ratio = (bus_ratio_max * 10);␊ |
656 | ␉␉␉␉␉}␊ |
657 | ␉␉␉␉}␊ |
658 | ␉␉␉␉//valv: to be uncommented if Remarq.1 didn't stick␊ |
659 | ␉␉␉␉//if (bus_ratio_max > 0) bus_ratio = flex_ratio;␊ |
660 | ␉␉␉␉p->CPU.MaxRatio = max_ratio;␊ |
661 | ␉␉␉␉p->CPU.MinRatio = min_ratio;␊ |
662 | ␊ |
663 | ␉␉␉␉myfsb = fsbFrequency / 1000000;␊ |
664 | ␉␉␉␉//verbose("Sticking with [BCLK: %dMhz, Bus-Ratio: %d]\n", myfsb, max_ratio/10); // Bungo: fixed wrong Bus-Ratio readout␊ |
665 | ␉␉␉␉currcoef = bus_ratio_max;␊ |
666 | ␊ |
667 | ␉␉␉␉break;␊ |
668 | ␊ |
669 | ␉␉␉default:␊ |
670 | ␉␉␉␉msr = rdmsr64(MSR_IA32_PERF_STATUS);␊ |
671 | ␉␉␉␉//verbose("msr(%d): ia32_perf_stat 0x%08x\n", __LINE__, bitfield(msr, 31, 0));␊ |
672 | ␉␉␉␉currcoef = bitfield(msr, 12, 8); // Bungo: reverted to 2263 state because of wrong old CPUs freq. calculating␊ |
673 | ␉␉␉␉// Non-integer bus ratio for the max-multi␊ |
674 | ␉␉␉␉maxdiv = bitfield(msr, 46, 46);␊ |
675 | ␉␉␉␉// Non-integer bus ratio for the current-multi (undocumented)␊ |
676 | ␉␉␉␉currdiv = bitfield(msr, 14, 14);␊ |
677 | ␊ |
678 | ␉␉␉␉// This will always be model >= 3␊ |
679 | ␉␉␉␉if ((p->CPU.Family == 0x06 && p->CPU.Model >= 0x0e) || (p->CPU.Family == 0x0f))␊ |
680 | ␉␉␉␉{␊ |
681 | ␉␉␉␉␉/* On these models, maxcoef defines TSC freq */␊ |
682 | ␉␉␉␉␉maxcoef = bitfield(msr, 44, 40);␊ |
683 | ␉␉␉␉}␊ |
684 | ␉␉␉␉else␊ |
685 | ␉␉␉␉{␊ |
686 | ␉␉␉␉␉// On lower models, currcoef defines TSC freq␊ |
687 | ␉␉␉␉␉// XXX␊ |
688 | ␉␉␉␉␉maxcoef = currcoef;␊ |
689 | ␉␉␉␉}␊ |
690 | ␊ |
691 | ␉␉␉␉if (!currcoef)␊ |
692 | ␉␉␉␉{␊ |
693 | ␉␉␉␉␉currcoef = maxcoef;␊ |
694 | ␉␉␉␉}␊ |
695 | ␊ |
696 | ␉␉␉␉if (maxcoef)␊ |
697 | ␉␉␉␉{␊ |
698 | ␉␉␉␉␉if (maxdiv)␊ |
699 | ␉␉␉␉␉{␊ |
700 | ␉␉␉␉␉␉fsbFrequency = ((tscFrequency * 2) / ((maxcoef * 2) + 1));␊ |
701 | ␉␉␉␉␉}␊ |
702 | ␉␉␉␉␉else␊ |
703 | ␉␉␉␉␉{␊ |
704 | ␉␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
705 | ␉␉␉␉␉}␊ |
706 | ␊ |
707 | ␉␉␉␉␉if (currdiv)␊ |
708 | ␉␉␉␉␉{␊ |
709 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * ((currcoef * 2) + 1) / 2);␊ |
710 | ␉␉␉␉␉}␊ |
711 | ␉␉␉␉␉else␊ |
712 | ␉␉␉␉␉{␊ |
713 | ␉␉␉␉␉␉cpuFrequency = (fsbFrequency * currcoef);␊ |
714 | ␉␉␉␉␉}␊ |
715 | ␉␉␉␉␉//verbose("max: %d%s current: %d%s\n", maxcoef, maxdiv ? ".5" : "",currcoef, currdiv ? ".5" : "");␊ |
716 | ␉␉␉␉}␊ |
717 | ␉␉␉␉break;␊ |
718 | ␉␉␉}␊ |
719 | ␉␉}␊ |
720 | ␉␉// Mobile CPU␊ |
721 | ␉␉if (rdmsr64(MSR_IA32_PLATFORM_ID) & (1<<28))␊ |
722 | ␉␉{␊ |
723 | ␉␉␉p->CPU.Features |= CPU_FEATURE_MOBILE;␊ |
724 | ␉␉}␊ |
725 | ␉}␊ |
726 | ␉else if ((p->CPU.Vendor == CPUID_VENDOR_AMD) && (p->CPU.Family == 0x0f))␊ |
727 | ␉{␊ |
728 | ␉␉switch(p->CPU.ExtFamily)␊ |
729 | ␉␉{␊ |
730 | ␉␉␉case 0x00: //* K8 *//␊ |
731 | ␉␉␉␉msr = rdmsr64(K8_FIDVID_STATUS);␊ |
732 | ␉␉␉␉maxcoef = bitfield(msr, 21, 16) / 2 + 4;␊ |
733 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) / 2 + 4;␊ |
734 | ␉␉␉␉break;␊ |
735 | ␊ |
736 | ␉␉␉case 0x01: //* K10 *//␊ |
737 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
738 | ␉␉␉␉do_cpuid2(0x00000006, 0, p->CPU.CPUID[CPUID_6]);␊ |
739 | ␉␉␉␉// EffFreq: effective frequency interface␊ |
740 | ␉␉␉␉if (bitfield(p->CPU.CPUID[CPUID_6][2], 0, 0) == 1)␊ |
741 | ␉␉␉␉{␊ |
742 | ␉␉␉␉␉//uint64_t mperf = measure_mperf_frequency();␊ |
743 | ␉␉␉␉␉uint64_t aperf = measure_aperf_frequency();␊ |
744 | ␉␉␉␉␉cpuFrequency = aperf;␊ |
745 | ␉␉␉␉}␊ |
746 | ␉␉␉␉// NOTE: tsc runs at the maccoeff (non turbo)␊ |
747 | ␉␉␉␉//␉␉␉*not* at the turbo frequency.␊ |
748 | ␉␉␉␉maxcoef␉ = bitfield(msr, 54, 49) / 2 + 4;␊ |
749 | ␉␉␉␉currcoef = bitfield(msr, 5, 0) + 0x10;␊ |
750 | ␉␉␉␉currdiv = 2 << bitfield(msr, 8, 6);␊ |
751 | ␊ |
752 | ␉␉␉␉break;␊ |
753 | ␊ |
754 | ␉␉␉case 0x05: //* K14 *//␊ |
755 | ␉␉␉␉msr = rdmsr64(K10_COFVID_STATUS);␊ |
756 | ␉␉␉␉currcoef = (bitfield(msr, 54, 49) + 0x10) << 2;␊ |
757 | ␉␉␉␉currdiv = (bitfield(msr, 8, 4) + 1) << 2;␊ |
758 | ␉␉␉␉currdiv += bitfield(msr, 3, 0);␊ |
759 | ␊ |
760 | ␉␉␉␉break;␊ |
761 | ␊ |
762 | ␉␉␉case 0x02: //* K11 *//␊ |
763 | ␉␉␉␉// not implimented␊ |
764 | ␉␉␉␉break;␊ |
765 | ␉␉}␊ |
766 | ␊ |
767 | ␉␉if (maxcoef)␊ |
768 | ␉␉{␊ |
769 | ␉␉␉if (currdiv)␊ |
770 | ␉␉␉{␊ |
771 | ␉␉␉␉if (!currcoef)␊ |
772 | ␉␉␉␉{␊ |
773 | ␉␉␉␉␉currcoef = maxcoef;␊ |
774 | ␉␉␉␉}␊ |
775 | ␊ |
776 | ␉␉␉␉if (!cpuFrequency)␊ |
777 | ␉␉␉␉{␊ |
778 | ␉␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
779 | ␉␉␉␉}␊ |
780 | ␉␉␉␉else␊ |
781 | ␉␉␉␉{␊ |
782 | ␉␉␉␉␉fsbFrequency = ((cpuFrequency * currdiv) / currcoef);␊ |
783 | ␉␉␉␉}␊ |
784 | ␉␉␉␉//verbose("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
785 | ␉␉␉}␊ |
786 | ␉␉␉else␊ |
787 | ␉␉␉{␊ |
788 | ␉␉␉␉if (!cpuFrequency)␊ |
789 | ␉␉␉␉{␊ |
790 | ␉␉␉␉␉fsbFrequency = (tscFrequency / maxcoef);␊ |
791 | ␉␉␉␉}␊ |
792 | ␉␉␉␉else␊ |
793 | ␉␉␉␉{␊ |
794 | ␉␉␉␉␉fsbFrequency = (cpuFrequency / maxcoef);␊ |
795 | ␉␉␉␉}␊ |
796 | ␉␉␉␉//verbose("%d\n", currcoef);␊ |
797 | ␉␉␉}␊ |
798 | ␉␉}␊ |
799 | ␉␉else if (currcoef)␊ |
800 | ␉␉{␊ |
801 | ␉␉␉if (currdiv)␊ |
802 | ␉␉␉{␊ |
803 | ␉␉␉␉fsbFrequency = ((tscFrequency * currdiv) / currcoef);␊ |
804 | ␉␉␉␉//verbose("%d.%d\n", currcoef / currdiv, ((currcoef % currdiv) * 100) / currdiv);␊ |
805 | ␉␉␉}␊ |
806 | ␉␉␉else␊ |
807 | ␉␉␉{␊ |
808 | ␉␉␉␉fsbFrequency = (tscFrequency / currcoef);␊ |
809 | ␉␉␉␉//verbose("%d\n", currcoef);␊ |
810 | ␉␉␉}␊ |
811 | ␉␉}␊ |
812 | ␉␉if (!cpuFrequency) cpuFrequency = tscFrequency;␊ |
813 | ␉}␊ |
814 | ␉␊ |
815 | #if 0␊ |
816 | ␉if (!fsbFrequency)␊ |
817 | ␉{␊ |
818 | ␉␉fsbFrequency = (DEFAULT_FSB * 1000);␊ |
819 | ␉␉verbose("CPU: fsbFrequency=0! using the default value for FSB!\n");␊ |
820 | ␉␉cpuFrequency = tscFrequency;␊ |
821 | ␉}␊ |
822 | ␊ |
823 | ␉//verbose("cpu freq = 0x%016llxn", timeRDTSC() * 20);␊ |
824 | ␊ |
825 | #endif␊ |
826 | ␊ |
827 | ␉p->CPU.MaxCoef = maxcoef;␊ |
828 | ␉p->CPU.MaxDiv = maxdiv;␊ |
829 | ␉p->CPU.CurrCoef = currcoef;␊ |
830 | ␉p->CPU.CurrDiv = currdiv;␊ |
831 | ␉p->CPU.TSCFrequency = tscFrequency;␊ |
832 | ␉p->CPU.FSBFrequency = fsbFrequency;␊ |
833 | ␉p->CPU.CPUFrequency = cpuFrequency;␊ |
834 | ␊ |
835 | ␉// keep formatted with spaces instead of tabs␊ |
836 | ␉//verbose("\n---------------------------------------------\n");␊ |
837 | ␉verbose("\n------------------ CPU INFO -----------------\n");␊ |
838 | ␉//verbose("---------------------------------------------\n");␊ |
839 | ␉verbose("\nCPUID Raw Values:\n");␊ |
840 | ␉for (i = 0; i < CPUID_MAX; i++)␊ |
841 | ␉{␊ |
842 | ␉␉verbose("%02d: %08X-%08X-%08X-%08X\n", i, p->CPU.CPUID[i][eax], p->CPU.CPUID[i][ebx], p->CPU.CPUID[i][ecx], p->CPU.CPUID[i][edx]);␊ |
843 | ␉}␊ |
844 | ␉verbose("\n");␊ |
845 | ␉verbose("Brand String: %s\n",␉␉p->CPU.BrandString);␉// Processor name (BIOS)␊ |
846 | ␉verbose("Vendor: 0x%X\n",␉␉p->CPU.Vendor);␉␉// Vendor ex: GenuineIntel␊ |
847 | ␉verbose("Family: 0x%X\n",␉␉p->CPU.Family);␉␉// Family ex: 6 (06h)␊ |
848 | ␉verbose("ExtFamily: 0x%X\n",␉␉p->CPU.ExtFamily);␊ |
849 | ␉verbose("Signature: 0x%08X\n",␉␉p->CPU.Signature);␉// CPUID signature␊ |
850 | ␉verbose("Model: 0x%X\n",␉␉p->CPU.Model);␉␉// Model ex: 37 (025h)␊ |
851 | ␉verbose("ExtModel: 0x%X\n",␉␉p->CPU.ExtModel);␊ |
852 | ␉verbose("Stepping: 0x%X\n",␉␉p->CPU.Stepping);␉// Stepping ex: 5 (05h)␊ |
853 | ␉verbose("MaxCoef: %d\n",␉␉p->CPU.MaxCoef);␊ |
854 | ␉verbose("CurrCoef: %d\n",␉␉p->CPU.CurrCoef);␊ |
855 | ␉verbose("MaxDiv: %d\n",␉␉p->CPU.MaxDiv);␊ |
856 | ␉verbose("CurrDiv: %d\n",␉␉p->CPU.CurrDiv);␊ |
857 | ␉verbose("TSCFreq: %dMHz\n",␉␉p->CPU.TSCFrequency / 1000000);␊ |
858 | ␉verbose("FSBFreq: %dMHz\n",␉␉p->CPU.FSBFrequency / 1000000);␊ |
859 | ␉verbose("CPUFreq: %dMHz\n",␉␉p->CPU.CPUFrequency / 1000000);␊ |
860 | ␉verbose("Cores: %d\n",␉␉p->CPU.NoCores);␉// Cores␊ |
861 | ␉verbose("Logical procesors: %d\n",␉␉p->CPU.NoThreads);␉// Threads␊ |
862 | ␉verbose("Features: 0x%08x\n",␉␉p->CPU.Features);␊ |
863 | ␊ |
864 | ␉verbose("---------------------------------------------\n\n");␊ |
865 | #if DEBUG_CPU␊ |
866 | ␉pause("\n[DEBUG CPU] ");␊ |
867 | #endif␊ |
868 | }␊ |
869 | |