Root/
Source at commit HEAD created 5 years 6 days ago. By ifabio, Few update to kernelPatcher (Credits to CrazyBirdy) | |
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1 | /*␊ |
2 | *␉HDA injector / Audio Enabler␊ |
3 | *␊ |
4 | *␉Copyright (C) 2012␉Chameleon Team␊ |
5 | *␉Edit by Fabio (ErmaC)␊ |
6 | *␉HDA bus scans and codecs enumeration by Zenith432␊ |
7 | *␊ |
8 | *␉HDA injector is free software: you can redistribute it and/or modify␊ |
9 | *␉it under the terms of the GNU General Public License as published by␊ |
10 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
11 | *␉(at your option) any later version.␊ |
12 | *␊ |
13 | *␉HDA injector is distributed in the hope that it will be useful,␊ |
14 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
15 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
16 | *␉GNU General Public License for more details.␊ |
17 | *␊ |
18 | *␉Alternatively you can choose to comply with APSL␊ |
19 | *␊ |
20 | *␉Permission is hereby granted, free of charge, to any person obtaining a␊ |
21 | *␉copy of this software and associated documentation files (the "Software"),␊ |
22 | *␉to deal in the Software without restriction, including without limitation␊ |
23 | *␉the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
24 | *␉and/or sell copies of the Software, and to permit persons to whom the␊ |
25 | *␉Software is furnished to do so, subject to the following conditions:␊ |
26 | *␊ |
27 | *␉The above copyright notice and this permission notice shall be included in␊ |
28 | *␉all copies or substantial portions of the Software.␊ |
29 | *␊ |
30 | ******************************************************************************␊ |
31 | * http://www.leidinger.net/FreeBSD/dox/dev_sound/html/df/d54/hdac_8c_source.html␊ |
32 | *␊ |
33 | * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>␊ |
34 | * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>␊ |
35 | * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>␊ |
36 | * All rights reserved.␊ |
37 | *␊ |
38 | * Redistribution and use in source and binary forms, with or without␊ |
39 | * modification, are permitted provided that the following conditions␊ |
40 | * are met:␊ |
41 | * 1. Redistributions of source code must retain the above copyright␊ |
42 | * notice, this list of conditions and the following disclaimer.␊ |
43 | * 2. Redistributions in binary form must reproduce the above copyright␊ |
44 | * notice, this list of conditions and the following disclaimer in the␊ |
45 | * documentation and/or other materials provided with the distribution.␊ |
46 | *␊ |
47 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND␊ |
48 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE␊ |
49 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE␊ |
50 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE␊ |
51 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL␊ |
52 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS␊ |
53 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)␊ |
54 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT␊ |
55 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY␊ |
56 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF␊ |
57 | * SUCH DAMAGE.␊ |
58 | *␊ |
59 | * Intel High Definition Audio (Controller) driver for FreeBSD.␊ |
60 | *␊ |
61 | ******************************************************************************/␊ |
62 | ␊ |
63 | #include "config.h"␊ |
64 | #include "boot.h"␊ |
65 | #include "bootstruct.h"␊ |
66 | #include "cpu.h"␊ |
67 | #include "pci.h"␊ |
68 | #include "pci_root.h"␊ |
69 | #include "platform.h"␊ |
70 | #include "device_inject.h"␊ |
71 | #include "convert.h"␊ |
72 | #include "hda.h"␊ |
73 | ␊ |
74 | #define STRINGIFY(x) #x␊ |
75 | #define TOSTRING(x) STRINGIFY(x)␊ |
76 | ␊ |
77 | #define HEADER __FILE__ " [" TOSTRING(__LINE__) "]: "␊ |
78 | ␊ |
79 | #if DEBUG_HDA␊ |
80 | ␉#define DBG(x...) verbose(x)␊ |
81 | #else␊ |
82 | ␉#define DBG(x...)␊ |
83 | #endif␊ |
84 | ␊ |
85 | #if DEBUG_CODEC␊ |
86 | ␉#define CDBG(x...) verbose(x)␊ |
87 | #else␊ |
88 | ␉#define CDBG(x...)␊ |
89 | #endif␊ |
90 | ␊ |
91 | #define UNKNOWN "Unknown "␊ |
92 | ␊ |
93 | #define hdacc_lock(codec) snd_mtxlock((codec)->lock)␊ |
94 | #define hdacc_unlock(codec) snd_mtxunlock((codec)->lock)␊ |
95 | #define hdacc_lockassert(codec) snd_mtxassert((codec)->lock)␊ |
96 | #define hdacc_lockowned(codec) mtx_owned((codec)->lock)␊ |
97 | ␊ |
98 | const char *hda_slot_name[]␉␉=␉{ "AAPL,slot-name", "Built In" };␊ |
99 | ␊ |
100 | uint8_t default_HDEF_layout_id[]␉␉=␉{0x01, 0x00, 0x00, 0x00};␊ |
101 | #define HDEF_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) )␊ |
102 | uint8_t default_HDAU_layout_id[]␉␉=␉{0x01, 0x00, 0x00, 0x00};␊ |
103 | #define HDAU_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) )␊ |
104 | static uint8_t connector_type_value[] =␉{0x00, 0x08, 0x00, 0x00};␊ |
105 | ␊ |
106 | /* Structures */␊ |
107 | ␊ |
108 | static hda_controller_devices know_hda_controller[] = {␊ |
109 | ␉//8086 Intel Corporation␊ |
110 | ␉{ HDA_INTEL_OAK,␉"Oaktrail"␉␉/*, 0, 0 */ },␊ |
111 | ␉{ HDA_INTEL_BAY,␉"BayTrail"␉␉/*, 0, 0 */ },␊ |
112 | ␉{ HDA_INTEL_HSW1,␉"Haswell"␉␉/*, 0, 0 */ },␊ |
113 | ␉{ HDA_INTEL_HSW2,␉"Haswell"␉␉/*, 0, 0 */ },␊ |
114 | ␉{ HDA_INTEL_HSW3,␉"Haswell"␉␉/*, 0, 0 */ },␊ |
115 | ␉{ HDA_INTEL_BDW,␉"Broadwell"␉␉/*, 0, 0 */ },␊ |
116 | ␉{ HDA_INTEL_BROXTON_T,␉"Broxton-T"␉␉/*, 0, 0 */ },␊ |
117 | ␉{ HDA_INTEL_CPT,␉"Cougar Point"␉␉/*, 0, 0 */ },␊ |
118 | ␉{ HDA_INTEL_PATSBURG,␉"Patsburg"␉␉/*, 0, 0 */ },␊ |
119 | ␉{ HDA_INTEL_PPT1,␉"Panther Point"␉␉/*, 0, 0 */ },␊ |
120 | ␉{ HDA_INTEL_BRASWELL,␉"Braswell"␉␉/*, 0, 0 */ },␊ |
121 | ␉{ HDA_INTEL_82801F,␉"82801F"␉␉/*, 0, 0 */ },␊ |
122 | ␉{ HDA_INTEL_63XXESB,␉"631x/632xESB"␉␉/*, 0, 0 */ },␊ |
123 | ␉{ HDA_INTEL_82801G,␉"82801G"␉␉/*, 0, 0 */ },␊ |
124 | ␉{ HDA_INTEL_82801H,␉"82801H"␉␉/*, 0, 0 */ },␊ |
125 | ␉{ HDA_INTEL_82801I,␉"82801I"␉␉/*, 0, 0 */ },␊ |
126 | ␉{ HDA_INTEL_ICH9,␉"ICH9"␉␉␉/*, 0, 0 */ },␊ |
127 | ␉{ HDA_INTEL_82801JI,␉"82801JI"␉␉/*, 0, 0 */ },␊ |
128 | ␉{ HDA_INTEL_82801JD,␉"82801JD"␉␉/*, 0, 0 */ },␊ |
129 | ␉{ HDA_INTEL_PCH,␉"5 Series/3400 Series"␉/*, 0, 0 */ },␊ |
130 | ␉{ HDA_INTEL_PCH2,␉"5 Series/3400 Series"␉/*, 0, 0 */ },␊ |
131 | ␉{ HDA_INTEL_BROXTON_P,␉"Apollolake"␉␉/*, 0, 0 */ }, // Broxton-P␊ |
132 | ␉{ HDA_INTEL_SCH,␉"SCH"␉␉␉/*, 0, 0 */ },␊ |
133 | ␉{ HDA_INTEL_LPT1,␉"Lynx Point"␉␉/*, 0, 0 */ },␊ |
134 | ␉{ HDA_INTEL_LPT2,␉"Lynx Point"␉␉/*, 0, 0 */ },␊ |
135 | ␉{ HDA_INTEL_WCPT,␉"Wildcat Point"␉␉/*, 0, 0 */ },␊ |
136 | ␉{ HDA_INTEL_WELLS1,␉"Wellsburg"␉␉/*, 0, 0 */ },␊ |
137 | ␉{ HDA_INTEL_WELLS2,␉"Wellsburg"␉␉/*, 0, 0 */ },␊ |
138 | ␉{ HDA_INTEL_WCPTLP,␉"Wildcat Point-LP"␉/*, 0, 0 */ },␊ |
139 | ␉{ HDA_INTEL_LPTLP1,␉"Lynx Point-LP"␉␉/*, 0, 0 */ },␊ |
140 | ␉{ HDA_INTEL_LPTLP2,␉"Lynx Point-LP"␉␉/*, 0, 0 */ },␊ |
141 | ␉{ HDA_INTEL_SRSPLP,␉"Sunrise Point-LP"␉/*, 0, 0 */ },␊ |
142 | ␉{ HDA_INTEL_KABYLAKE_LP, "Kabylake-LP"␉␉/*, 0, 0 */ }, // Kabylake-LP␊ |
143 | ␉{ HDA_INTEL_SRSP,␉"Sunrise Point"␉␉/*, 0, 0 */ },␊ |
144 | ␉{ HDA_INTEL_KABYLAKE,␉"Kabylake"␉␉/*, 0, 0 */ }, // Kabylake␊ |
145 | ␉{ HDA_INTEL_LEWISBURG1,␉"Lewisburg"␉␉/*, 0, 0 */ }, // Lewisburg␊ |
146 | ␉{ HDA_INTEL_LEWISBURG2,␉"Lewisburg"␉␉/*, 0, 0 */ }, // Lewisburg␊ |
147 | ␉{ HDA_INTEL_UNPT,␉"Union Point"␉␉/*, 0, 0 */ }, // Kabylake-H␊ |
148 | ␊ |
149 | ␉//10de NVIDIA Corporation␊ |
150 | ␉{ HDA_NVIDIA_MCP51,␉"MCP51" /*, 0, HDAC_QUIRK_MSI */ },␊ |
151 | ␉{ HDA_NVIDIA_MCP55,␉"MCP55" /*, 0, HDAC_QUIRK_MSI */ },␊ |
152 | ␉{ HDA_NVIDIA_MCP61_1,␉"MCP61" /*, 0, 0 */ },␊ |
153 | ␉{ HDA_NVIDIA_MCP61_2,␉"MCP61" /*, 0, 0 */ },␊ |
154 | ␉{ HDA_NVIDIA_MCP65_1,␉"MCP65" /*, 0, 0 */ },␊ |
155 | ␉{ HDA_NVIDIA_MCP65_2,␉"MCP65" /*, 0, 0 */ },␊ |
156 | ␉{ HDA_NVIDIA_MCP67_1,␉"MCP67" /*, 0, 0 */ },␊ |
157 | ␉{ HDA_NVIDIA_MCP67_2,␉"MCP67" /*, 0, 0 */ },␊ |
158 | ␉{ HDA_NVIDIA_MCP73_1,␉"MCP73" /*, 0, 0 */ },␊ |
159 | ␉{ HDA_NVIDIA_MCP73_2,␉"MCP73" /*, 0, 0 */ },␊ |
160 | ␉{ HDA_NVIDIA_MCP78_1,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
161 | ␉{ HDA_NVIDIA_MCP78_2,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
162 | ␉{ HDA_NVIDIA_MCP78_3,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
163 | ␉{ HDA_NVIDIA_MCP78_4,␉"MCP78" /*, 0, HDAC_QUIRK_64BIT */ },␊ |
164 | ␉{ HDA_NVIDIA_MCP79_1,␉"MCP79" /*, 0, 0 */ },␊ |
165 | ␉{ HDA_NVIDIA_MCP79_2,␉"MCP79" /*, 0, 0 */ },␊ |
166 | ␉{ HDA_NVIDIA_MCP79_3,␉"MCP79" /*, 0, 0 */ },␊ |
167 | ␉{ HDA_NVIDIA_MCP79_4,␉"MCP79" /*, 0, 0 */ },␊ |
168 | ␉{ HDA_NVIDIA_MCP89_1,␉"MCP89" /*, 0, 0 */ },␊ |
169 | ␉{ HDA_NVIDIA_MCP89_2,␉"MCP89" /*, 0, 0 */ },␊ |
170 | ␉{ HDA_NVIDIA_MCP89_3,␉"MCP89" /*, 0, 0 */ },␊ |
171 | ␉{ HDA_NVIDIA_MCP89_4,␉"MCP89" /*, 0, 0 */ },␊ |
172 | ␉{ HDA_NVIDIA_0BE2,␉"(0x0be2)" /*, 0, HDAC_QUIRK_MSI */ },␊ |
173 | ␉{ HDA_NVIDIA_0BE3,␉"(0x0be3)" /*, 0, HDAC_QUIRK_MSI */ },␊ |
174 | ␉{ HDA_NVIDIA_0BE4,␉"(0x0be4)" /*, 0, HDAC_QUIRK_MSI */ },␊ |
175 | ␉{ HDA_NVIDIA_GT100,␉"GT100" /*, 0, HDAC_QUIRK_MSI */ },␊ |
176 | ␉{ HDA_NVIDIA_GT104,␉"GT104" /*, 0, HDAC_QUIRK_MSI */ },␊ |
177 | ␉{ HDA_NVIDIA_GT106,␉"GT106" /*, 0, HDAC_QUIRK_MSI */ },␊ |
178 | ␉{ HDA_NVIDIA_GT108,␉"GT108" /*, 0, HDAC_QUIRK_MSI */ },␊ |
179 | ␉{ HDA_NVIDIA_GT116,␉"GT116" /*, 0, HDAC_QUIRK_MSI */ },␊ |
180 | ␉{ HDA_NVIDIA_GF119,␉"GF119" /*, 0, 0 */ },␊ |
181 | ␉{ HDA_NVIDIA_GF110_1,␉"GF110" /*, 0, HDAC_QUIRK_MSI */ },␊ |
182 | ␉{ HDA_NVIDIA_GF110_2,␉"GF110" /*, 0, HDAC_QUIRK_MSI */ },␊ |
183 | ␉{ HDA_NVIDIA_GK110,␉"GK110" /*, 0, ? */ },␊ |
184 | ␉{ HDA_NVIDIA_GK106,␉"GK106" /*, 0, ? */ },␊ |
185 | ␉{ HDA_NVIDIA_GK107,␉"GK107" /*, 0, ? */ },␊ |
186 | ␉{ HDA_NVIDIA_GK104,␉"GK104" /*, 0, ? */ },␊ |
187 | ␉{ HDA_NVIDIA_GP104_2,␉"Pascal GP104-200" /*, 0, ? */ },␊ |
188 | ␉{ HDA_NVIDIA_GM204_2,␉"Maxwell GP204-200" /*, 0, ? */ },␊ |
189 | ␊ |
190 | ␉//1002 Advanced Micro Devices [AMD] nee ATI Technologies Inc␊ |
191 | ␉{ HDA_ATI_SB450,␉"SB4x0" /*, 0, 0 */ },␊ |
192 | ␉{ HDA_ATI_SB600,␉"SB600" /*, 0, 0 */ },␊ |
193 | ␉{ HDA_ATI_RS600,␉"RS600" /*, 0, 0 */ },␊ |
194 | ␉{ HDA_ATI_HUDSON,␉"Hudson" /*, 0, 0 */ },␊ |
195 | ␉{ HDA_ATI_RS690,␉"RS690" /*, 0, 0 */ },␊ |
196 | ␉{ HDA_ATI_RS780,␉"RS780" /*, 0, 0 */ },␊ |
197 | ␉{ HDA_ATI_RS880,␉"RS880" /*, 0, 0 */ },␊ |
198 | ␉{ HDA_ATI_TRINITY,␉"Trinity" /*, 0, ? */ },␊ |
199 | ␉{ HDA_ATI_R600,␉␉"R600" /*, 0, 0 */ },␊ |
200 | ␉{ HDA_ATI_RV610,␉"RV610" /*, 0, 0 */ },␊ |
201 | ␉{ HDA_ATI_RV620,␉"RV620" /*, 0, 0 */ },␊ |
202 | ␉{ HDA_ATI_RV630,␉"RV630" /*, 0, 0 */ },␊ |
203 | ␉{ HDA_ATI_RV635,␉"RV635" /*, 0, 0 */ },␊ |
204 | ␉{ HDA_ATI_RV710,␉"RV710" /*, 0, 0 */ },␊ |
205 | ␉{ HDA_ATI_RV730,␉"RV730" /*, 0, 0 */ },␊ |
206 | ␉{ HDA_ATI_RV740,␉"RV740" /*, 0, 0 */ },␊ |
207 | ␉{ HDA_ATI_RV770,␉"RV770" /*, 0, 0 */ },␊ |
208 | ␉{ HDA_ATI_RV810,␉"RV810" /*, 0, 0 */ },␊ |
209 | ␉{ HDA_ATI_RV830,␉"RV830" /*, 0, 0 */ },␊ |
210 | ␉{ HDA_ATI_RV840,␉"RV840" /*, 0, 0 */ },␊ |
211 | ␉{ HDA_ATI_RV870,␉"RV870" /*, 0, 0 */ },␊ |
212 | ␉{ HDA_ATI_RV910,␉"RV910" /*, 0, 0 */ },␊ |
213 | ␉{ HDA_ATI_RV930,␉"RV930" /*, 0, 0 */ },␊ |
214 | ␉{ HDA_ATI_RV940,␉"RV940" /*, 0, 0 */ },␊ |
215 | ␉{ HDA_ATI_RV970,␉"RV970" /*, 0, 0 */ },␊ |
216 | ␉{ HDA_ATI_R1000,␉"R1000" /*, 0, 0 */ }, // HDMi␊ |
217 | ␉{ HDA_ATI_SI,␉␉"SI" /*, 0, 0 */ },␊ |
218 | ␉{ HDA_ATI_VERDE,␉"Cape Verde" /*, 0, ? */ }, // HDMi␊ |
219 | ␊ |
220 | ␉//17f3 RDC Semiconductor, Inc.␊ |
221 | ␉{ HDA_RDC_M3010,␉"M3010" /*, 0, 0 */ },␊ |
222 | ␊ |
223 | ␉//1106 VIA Technologies, Inc.␊ |
224 | ␉{ HDA_VIA_VT82XX,␉"VT8251/8237A" /*, 0, 0 */ },␊ |
225 | ␊ |
226 | ␉//1039 Silicon Integrated Systems [SiS]␊ |
227 | ␉{ HDA_SIS_966,␉␉"966" /*, 0, 0 */ },␊ |
228 | ␊ |
229 | ␉//10b9 ULi Electronics Inc.(Split off ALi Corporation in 2003)␊ |
230 | ␉{ HDA_ULI_M5461,␉"M5461" /*, 0, 0 */ },␊ |
231 | ␊ |
232 | ␉/* Unknown */␊ |
233 | ␉{ HDA_INTEL_ALL,␉"Unknown Intel device" /*, 0, 0 */ },␊ |
234 | ␉{ HDA_NVIDIA_ALL,␉"Unknown NVIDIA device" /*, 0, 0 */ },␊ |
235 | ␉{ HDA_ATI_ALL,␉␉"Unknown ATI device" /*, 0, 0 */ },␊ |
236 | ␉{ HDA_VIA_ALL,␉␉"Unknown VIA device" /*, 0, 0 */ },␊ |
237 | ␉{ HDA_SIS_ALL,␉␉"Unknown SiS device" /*, 0, 0 */ },␊ |
238 | ␉{ HDA_ULI_ALL,␉␉"Unknown ULI device" /*, 0, 0 */ },␊ |
239 | };␊ |
240 | #define HDAC_DEVICES_LEN (sizeof(know_hda_controller) / sizeof(know_hda_controller[0]))␊ |
241 | ␊ |
242 | /* CODECs */␊ |
243 | /*␊ |
244 | * ErmaC: There's definitely a lot of different versions of the same audio codec variant out there...␊ |
245 | * in the next struct you will find a "generic" but IMHO detailed list of␊ |
246 | * possible codec... anyway to specific a new one or find difference beetween revision␊ |
247 | * check it under linux enviroment with:␊ |
248 | * $cat /proc/asound/Intel/codec#0␊ |
249 | * --------------------------------␊ |
250 | * Codec: Analog Devices AD1989B␊ |
251 | * Address: 0␊ |
252 | * AFG Function Id: 0x1 (unsol 0)␊ |
253 | * Vendor Id: 0x11d4989b␊ |
254 | * Subsystem Id: 0x10438372␊ |
255 | * Revision Id: 0x100300␊ |
256 | * --------------------------------␊ |
257 | * or␊ |
258 | * $cat /proc/asound/NVidia/codec#0␊ |
259 | * --------------------------------␊ |
260 | * Codec: Nvidia GPU 14 HDMI/DP␊ |
261 | * Address: 0␊ |
262 | * AFG Function Id: 0x1 (unsol 0)␊ |
263 | * Vendor Id: 0x10de0014␊ |
264 | * Subsystem Id: 0x10de0101␊ |
265 | * Revision Id: 0x100100␊ |
266 | * --------------------------------␊ |
267 | */␊ |
268 | ␊ |
269 | static hdacc_codecs know_codecs[] = {␊ |
270 | ␉{ HDA_CODEC_CS4206, 0,␉␉"CS4206" },␊ |
271 | ␉{ HDA_CODEC_CS4207, 0,␉␉"CS4207" },␊ |
272 | ␉{ HDA_CODEC_CS4208, 0,␉␉"CS4208" },␊ |
273 | ␉{ HDA_CODEC_CS4210, 0,␉␉"CS4210" },␊ |
274 | ␉{ HDA_CODEC_CS4213, 0, "CS4213" },␊ |
275 | ␊ |
276 | ␉{ HDA_CODEC_ALC221, 0, "ALC221" },␊ |
277 | ␉{ HDA_CODEC_ALC231, 0, "ALC231" },␊ |
278 | ␉{ HDA_CODEC_ALC233, 0, "ALC233" },␊ |
279 | ␉{ HDA_CODEC_ALC233, 0x0003,␉"ALC3236" },␊ |
280 | ␉{ HDA_CODEC_ALC235, 0, "ALC235" },␊ |
281 | ␉{ HDA_CODEC_ALC255, 0, "ALC255" },␊ |
282 | ␉{ HDA_CODEC_ALC256, 0, "ALC256" },␊ |
283 | ␉{ HDA_CODEC_ALC260, 0, "ALC260" },␊ |
284 | //␉{ HDA_CODEC_ALC262, 0x0100,␉"ALC262" }, // Revision Id: 0x100100␊ |
285 | ␉{ HDA_CODEC_ALC262, 0, "ALC262" },␊ |
286 | ␉{ HDA_CODEC_ALC267, 0, "ALC267" },␊ |
287 | ␉{ HDA_CODEC_ALC268, 0, "ALC268" },␊ |
288 | ␉{ HDA_CODEC_ALC269, 0, "ALC269" },␊ |
289 | ␉{ HDA_CODEC_ALC270, 0, "ALC270" },␊ |
290 | ␉{ HDA_CODEC_ALC272, 0, "ALC272" },␊ |
291 | ␉{ HDA_CODEC_ALC273, 0, "ALC273" },␊ |
292 | ␉{ HDA_CODEC_ALC275, 0, "ALC275" },␊ |
293 | ␉{ HDA_CODEC_ALC276, 0, "ALC276" },␊ |
294 | ␉{ HDA_CODEC_ALC280, 0, "ALC280" },␊ |
295 | ␉{ HDA_CODEC_ALC282, 0, "ALC282" },␊ |
296 | ␉{ HDA_CODEC_ALC283, 0, "ALC283" },␊ |
297 | ␉{ HDA_CODEC_ALC284, 0, "ALC284" },␊ |
298 | ␉{ HDA_CODEC_ALC285, 0, "ALC285" },␊ |
299 | ␉{ HDA_CODEC_ALC286, 0, "ALC286" },␊ |
300 | ␉{ HDA_CODEC_ALC288, 0, "ALC288" },␊ |
301 | ␉{ HDA_CODEC_ALC290, 0, "ALC290" },␊ |
302 | ␉{ HDA_CODEC_ALC292, 0, "ALC292" },␊ |
303 | ␉{ HDA_CODEC_ALC292, 0x0001, "ALC3232" },␊ |
304 | ␉{ HDA_CODEC_ALC293, 0, "ALC293" },␊ |
305 | ␉{ HDA_CODEC_ALC298, 0, "ALC298" },␊ |
306 | ␉{ HDA_CODEC_ALC660, 0, "ALC660-VD" },␊ |
307 | ␉{ HDA_CODEC_ALC662, 0, "ALC662" },␊ |
308 | ␉{ HDA_CODEC_ALC662, 0x0101,␉"ALC662 rev1" },␊ |
309 | ␉{ HDA_CODEC_ALC662, 0x0002,␉"ALC662 rev2" },␊ |
310 | ␉{ HDA_CODEC_ALC662, 0x0300,␉"ALC662 rev3" },␊ |
311 | ␉{ HDA_CODEC_ALC663, 0, "ALC663" },␊ |
312 | ␉{ HDA_CODEC_ALC665, 0, "ALC665" },␊ |
313 | ␉{ HDA_CODEC_ALC667, 0, "ALC667" },␊ |
314 | ␉{ HDA_CODEC_ALC668, 0, "ALC668" },␊ |
315 | ␉{ HDA_CODEC_ALC670, 0, "ALC670" },␊ |
316 | ␉{ HDA_CODEC_ALC671, 0, "ALC671" },␊ |
317 | ␉{ HDA_CODEC_ALC680, 0, "ALC680" },␊ |
318 | ␉{ HDA_CODEC_ALC861, 0x0340,␉"ALC660" },␊ |
319 | ␉{ HDA_CODEC_ALC861, 0, "ALC861" },␊ |
320 | ␉{ HDA_CODEC_ALC861VD, 0, "ALC861-VD" },␊ |
321 | ␉{ HDA_CODEC_ALC867, 0, "ALC891" },␊ |
322 | //␉{ HDA_CODEC_ALC880, 0x0800,␉"ALC880" }, // Revision Id: 0x100800␊ |
323 | ␉{ HDA_CODEC_ALC880, 0, "ALC880" },␊ |
324 | ␉{ HDA_CODEC_ALC882, 0, "ALC882" },␊ |
325 | ␉{ HDA_CODEC_ALC883, 0, "ALC883" },␊ |
326 | ␉{ HDA_CODEC_ALC885, 0x0101,␉"ALC889A" }, // Revision Id: 0x100101␊ |
327 | ␉{ HDA_CODEC_ALC885, 0x0103,␉"ALC889A" }, // Revision Id: 0x100103␊ |
328 | ␉{ HDA_CODEC_ALC885, 0, "ALC885" },␊ |
329 | ␉{ HDA_CODEC_ALC886, 0, "ALC886" },␊ |
330 | ␉{ HDA_CODEC_ALC887, 0, "ALC887" },␊ |
331 | ␉{ HDA_CODEC_ALC888, 0x0101,␉"ALC1200" }, // Revision Id: 0x100101␊ |
332 | ␉{ HDA_CODEC_ALC888, 0, "ALC888" },␊ |
333 | ␉{ HDA_CODEC_ALC889, 0, "ALC889" },␊ |
334 | ␉{ HDA_CODEC_ALC892, 0, "ALC892" },␊ |
335 | ␉{ HDA_CODEC_ALC898, 0, "ALC898" },␊ |
336 | //␉{ HDA_CODEC_ALC899, 0,␉␉"ALC899" },␊ |
337 | ␉{ HDA_CODEC_ALC900, 0, "ALC1150" },␊ |
338 | ␉{ HDA_CODEC_ALCS1220A, 0,␉"ALCS1220A" },␊ |
339 | ␉{ HDA_CODEC_ALC1220, 0, "ALC1220" },␊ |
340 | ␊ |
341 | ␉{ HDA_CODEC_AD1882, 0, "AD1882" },␊ |
342 | ␉{ HDA_CODEC_AD1882A, 0, "AD1882A" },␊ |
343 | ␉{ HDA_CODEC_AD1883, 0, "AD1883" },␊ |
344 | ␉{ HDA_CODEC_AD1884, 0, "AD1884" },␊ |
345 | ␉{ HDA_CODEC_AD1884A, 0, "AD1884A" },␊ |
346 | ␉{ HDA_CODEC_AD1981HD, 0, "AD1981HD" },␊ |
347 | ␉{ HDA_CODEC_AD1983, 0, "AD1983" },␊ |
348 | ␉{ HDA_CODEC_AD1984, 0, "AD1984" },␊ |
349 | ␉{ HDA_CODEC_AD1984A, 0, "AD1984A" },␊ |
350 | ␉{ HDA_CODEC_AD1984B, 0, "AD1984B" },␊ |
351 | ␉{ HDA_CODEC_AD1986A, 0, "AD1986A" },␊ |
352 | ␉{ HDA_CODEC_AD1987, 0, "AD1987" },␊ |
353 | ␉{ HDA_CODEC_AD1988, 0, "AD1988A" },␊ |
354 | ␉{ HDA_CODEC_AD1988B, 0, "AD1988B" },␊ |
355 | ␉{ HDA_CODEC_AD1989A, 0, "AD1989A" },␊ |
356 | ␉{ HDA_CODEC_AD1989B, 0x0200,␉"AD2000B" }, // Revision Id: 0x100200␊ |
357 | ␉{ HDA_CODEC_AD1989B, 0x0300,␉"AD2000B" }, // Revision Id: 0x100300␊ |
358 | ␉{ HDA_CODEC_AD1989B, 0, "AD1989B" },␊ |
359 | ␊ |
360 | ␉{ HDA_CODEC_XFIEA, 0, "X-Fi Extreme A" },␊ |
361 | ␉{ HDA_CODEC_XFIED, 0, "X-Fi Extreme D" },␊ |
362 | ␉{ HDA_CODEC_CA0132, 0, "CA0132" },␊ |
363 | ␉{ HDA_CODEC_SB0880, 0, "SB0880 X-Fi" },␊ |
364 | ␉{ HDA_CODEC_CMI9880, 0, "CMI9880" },␊ |
365 | ␉{ HDA_CODEC_CMI98802, 0, "CMI9880" },␊ |
366 | ␊ |
367 | ␉{ HDA_CODEC_CXD9872RDK, 0, "CXD9872RD/K" },␊ |
368 | ␉{ HDA_CODEC_CXD9872AKD, 0, "CXD9872AKD" },␊ |
369 | ␉{ HDA_CODEC_STAC9200D, 0, "STAC9200D" },␊ |
370 | ␉{ HDA_CODEC_STAC9204X, 0, "STAC9204X" },␊ |
371 | ␉{ HDA_CODEC_STAC9204D, 0, "STAC9204D" },␊ |
372 | ␉{ HDA_CODEC_STAC9205X, 0, "STAC9205X" },␊ |
373 | ␉{ HDA_CODEC_STAC9205D, 0, "STAC9205D" },␊ |
374 | ␉{ HDA_CODEC_STAC9220, 0, "STAC9220" },␊ |
375 | ␉{ HDA_CODEC_STAC9220_A1, 0, "STAC9220_A1" },␊ |
376 | ␉{ HDA_CODEC_STAC9220_A2, 0, "STAC9220_A2" },␊ |
377 | ␉{ HDA_CODEC_STAC9221, 0, "STAC9221" },␊ |
378 | ␉{ HDA_CODEC_STAC9221_A2, 0, "STAC9221_A2" },␊ |
379 | ␉{ HDA_CODEC_STAC9221D, 0, "STAC9221D" },␊ |
380 | ␉{ HDA_CODEC_STAC922XD, 0, "STAC9220D/9223D" },␊ |
381 | ␉{ HDA_CODEC_STAC9227X, 0, "STAC9227X" },␊ |
382 | ␉{ HDA_CODEC_STAC9227D, 0, "STAC9227D" },␊ |
383 | ␉{ HDA_CODEC_STAC9228X, 0, "STAC9228X" },␊ |
384 | ␉{ HDA_CODEC_STAC9228D, 0, "STAC9228D" },␊ |
385 | ␉{ HDA_CODEC_STAC9229X, 0, "STAC9229X" },␊ |
386 | ␉{ HDA_CODEC_STAC9229D, 0, "STAC9229D" },␊ |
387 | ␉{ HDA_CODEC_STAC9230X, 0, "STAC9230X" },␊ |
388 | ␉{ HDA_CODEC_STAC9230D, 0, "STAC9230D" },␊ |
389 | ␉{ HDA_CODEC_STAC9250, 0, "STAC9250" },␊ |
390 | ␉{ HDA_CODEC_STAC9250D, 0,␉"STAC9250D" },␊ |
391 | ␉{ HDA_CODEC_STAC9251, 0, "STAC9251" },␊ |
392 | ␉{ HDA_CODEC_STAC9250D_1, 0,␉"STAC9250D" },␊ |
393 | ␉{ HDA_CODEC_STAC9255, 0, "STAC9255" },␊ |
394 | ␉{ HDA_CODEC_STAC9255D, 0, "STAC9255D" },␊ |
395 | ␉{ HDA_CODEC_STAC9254, 0, "STAC9254" },␊ |
396 | ␉{ HDA_CODEC_STAC9254D, 0, "STAC9254D" },␊ |
397 | ␉{ HDA_CODEC_STAC9271X, 0, "STAC9271X" },␊ |
398 | ␉{ HDA_CODEC_STAC9271D, 0, "STAC9271D" },␊ |
399 | ␉{ HDA_CODEC_STAC9272X, 0, "STAC9272X" },␊ |
400 | ␉{ HDA_CODEC_STAC9272D, 0, "STAC9272D" },␊ |
401 | ␉{ HDA_CODEC_STAC9273X, 0, "STAC9273X" },␊ |
402 | ␉{ HDA_CODEC_STAC9273D, 0, "STAC9273D" },␊ |
403 | ␉{ HDA_CODEC_STAC9274, 0, "STAC9274" },␊ |
404 | ␉{ HDA_CODEC_STAC9274D, 0, "STAC9274D" },␊ |
405 | ␉{ HDA_CODEC_STAC9274X5NH, 0, "STAC9274X5NH" },␊ |
406 | ␉{ HDA_CODEC_STAC9274D5NH, 0, "STAC9274D5NH" },␊ |
407 | ␉{ HDA_CODEC_STAC9202, 0,␉"STAC9202" },␊ |
408 | ␉{ HDA_CODEC_STAC9202D, 0,␉"STAC9202D" },␊ |
409 | ␉{ HDA_CODEC_STAC9872AK, 0, "STAC9872AK" },␊ |
410 | ␊ |
411 | ␉{ HDA_CODEC_IDT92HD005, 0, "92HD005" },␊ |
412 | ␉{ HDA_CODEC_IDT92HD005D, 0, "92HD005D" },␊ |
413 | ␉{ HDA_CODEC_IDT92HD206X, 0, "92HD206X" },␊ |
414 | ␉{ HDA_CODEC_IDT92HD206D, 0, "92HD206D" },␊ |
415 | ␉{ HDA_CODEC_IDT92HD66B1X5, 0, "92HD66B1X5" },␊ |
416 | ␉{ HDA_CODEC_IDT92HD66B2X5, 0, "92HD66B2X5" },␊ |
417 | ␉{ HDA_CODEC_IDT92HD66B3X5, 0, "92HD66B3X5" },␊ |
418 | ␉{ HDA_CODEC_IDT92HD66C1X5, 0, "92HD66C1X5" },␊ |
419 | ␉{ HDA_CODEC_IDT92HD66C2X5, 0, "92HD66C2X5" },␊ |
420 | ␉{ HDA_CODEC_IDT92HD66C3X5, 0, "92HD66C3X5" },␊ |
421 | ␉{ HDA_CODEC_IDT92HD66B1X3, 0, "92HD66B1X3" },␊ |
422 | ␉{ HDA_CODEC_IDT92HD66B2X3, 0, "92HD66B2X3" },␊ |
423 | ␉{ HDA_CODEC_IDT92HD66B3X3, 0, "92HD66B3X3" },␊ |
424 | ␉{ HDA_CODEC_IDT92HD66C1X3, 0, "92HD66C1X3" },␊ |
425 | ␉{ HDA_CODEC_IDT92HD66C2X3, 0, "92HD66C2X3" },␊ |
426 | ␉{ HDA_CODEC_IDT92HD66C3_65, 0, "92HD66C3_65" },␊ |
427 | ␉{ HDA_CODEC_IDT92HD700X, 0, "92HD700X" },␊ |
428 | ␉{ HDA_CODEC_IDT92HD700D, 0, "92HD700D" },␊ |
429 | ␉{ HDA_CODEC_IDT92HD71B5, 0, "92HD71B5" },␊ |
430 | ␉{ HDA_CODEC_IDT92HD71B5_2, 0, "92HD71B5" },␊ |
431 | ␉{ HDA_CODEC_IDT92HD71B6, 0, "92HD71B6" },␊ |
432 | ␉{ HDA_CODEC_IDT92HD71B6_2, 0, "92HD71B6" },␊ |
433 | ␉{ HDA_CODEC_IDT92HD71B7, 0, "92HD71B7" },␊ |
434 | ␉{ HDA_CODEC_IDT92HD71B7_2, 0, "92HD71B7" },␊ |
435 | ␉{ HDA_CODEC_IDT92HD71B8, 0, "92HD71B8" },␊ |
436 | ␉{ HDA_CODEC_IDT92HD71B8_2, 0, "92HD71B8" },␊ |
437 | ␉{ HDA_CODEC_IDT92HD73C1, 0, "92HD73C1" },␊ |
438 | ␉{ HDA_CODEC_IDT92HD73D1, 0, "92HD73D1" },␊ |
439 | ␉{ HDA_CODEC_IDT92HD73E1, 0, "92HD73E1" },␊ |
440 | ␉{ HDA_CODEC_IDT92HD95, 0,␉"92HD95" },␊ |
441 | ␉{ HDA_CODEC_IDT92HD75B3, 0, "92HD75B3" },␊ |
442 | ␉{ HDA_CODEC_IDT92HD88B3, 0, "92HD88B3" },␊ |
443 | ␉{ HDA_CODEC_IDT92HD88B1, 0, "92HD88B1" },␊ |
444 | ␉{ HDA_CODEC_IDT92HD88B2, 0, "92HD88B2" },␊ |
445 | ␉{ HDA_CODEC_IDT92HD88B4, 0, "92HD88B4" },␊ |
446 | ␉{ HDA_CODEC_IDT92HD75BX, 0, "92HD75BX" },␊ |
447 | ␉{ HDA_CODEC_IDT92HD81B1C, 0, "92HD81B1C" },␊ |
448 | ␉{ HDA_CODEC_IDT92HD81B1X, 0, "92HD81B1X" },␊ |
449 | ␉{ HDA_CODEC_IDT92HD83C1C, 0, "92HD83C1C" },␊ |
450 | ␉{ HDA_CODEC_IDT92HD83C1X, 0, "92HD83C1X" },␊ |
451 | ␉{ HDA_CODEC_IDT92HD87B1_3, 0, "92HD87B1/3" },␊ |
452 | ␉{ HDA_CODEC_IDT92HD87B2_4, 0, "92HD87B2/4" },␊ |
453 | ␉{ HDA_CODEC_IDT92HD89C3, 0, "92HD89C3" },␊ |
454 | ␉{ HDA_CODEC_IDT92HD89C2, 0, "92HD89C2" },␊ |
455 | ␉{ HDA_CODEC_IDT92HD89C1, 0, "92HD89C1" },␊ |
456 | ␉{ HDA_CODEC_IDT92HD89B3, 0, "92HD89B3" },␊ |
457 | ␉{ HDA_CODEC_IDT92HD89B2, 0, "92HD89B2" },␊ |
458 | ␉{ HDA_CODEC_IDT92HD89B1, 0, "92HD89B1" },␊ |
459 | ␉{ HDA_CODEC_IDT92HD89E3, 0, "92HD89E3" },␊ |
460 | ␉{ HDA_CODEC_IDT92HD89E2, 0, "92HD89E2" },␊ |
461 | ␉{ HDA_CODEC_IDT92HD89E1, 0, "92HD89E1" },␊ |
462 | ␉{ HDA_CODEC_IDT92HD89D3, 0, "92HD89D3" },␊ |
463 | ␉{ HDA_CODEC_IDT92HD89D2, 0, "92HD89D2" },␊ |
464 | ␉{ HDA_CODEC_IDT92HD89D1, 0, "92HD89D1" },␊ |
465 | ␉{ HDA_CODEC_IDT92HD89F3, 0, "92HD89F3" },␊ |
466 | ␉{ HDA_CODEC_IDT92HD89F2, 0, "92HD89F2" },␊ |
467 | ␉{ HDA_CODEC_IDT92HD89F1, 0, "92HD89F1" },␊ |
468 | ␉{ HDA_CODEC_IDT92HD90BXX, 0, "92HD90BXX" },␊ |
469 | ␉{ HDA_CODEC_IDT92HD91BXX, 0, "92HD91BXX" },␊ |
470 | ␉{ HDA_CODEC_IDT92HD93BXX, 0, "92HD93BXX" },␊ |
471 | ␉{ HDA_CODEC_IDT92HD98BXX, 0, "92HD98BXX" },␊ |
472 | ␉{ HDA_CODEC_IDT92HD99BXX, 0, "92HD99BXX" },␊ |
473 | ␊ |
474 | ␉{ HDA_CODEC_CX20549, 0, "CX20549 (Venice)" },␊ |
475 | ␉{ HDA_CODEC_CX20551, 0, "CX20551 (Waikiki)" },␊ |
476 | ␉{ HDA_CODEC_CX20561, 0, "CX20561 (Hermosa)" },␊ |
477 | ␉{ HDA_CODEC_CX20582, 0, "CX20582 (Pebble)" },␊ |
478 | ␉{ HDA_CODEC_CX20583, 0, "CX20583 (Pebble HSF)" },␊ |
479 | ␉{ HDA_CODEC_CX20584, 0, "CX20584" },␊ |
480 | ␉{ HDA_CODEC_CX20585, 0, "CX20585" },␊ |
481 | ␉{ HDA_CODEC_CX20588, 0, "CX20588" },␊ |
482 | ␉{ HDA_CODEC_CX20590, 0, "CX20590" },␊ |
483 | ␉{ HDA_CODEC_CX20631, 0, "CX20631" },␊ |
484 | ␉{ HDA_CODEC_CX20632, 0, "CX20632" },␊ |
485 | ␉{ HDA_CODEC_CX20641, 0, "CX20641" },␊ |
486 | ␉{ HDA_CODEC_CX20642, 0, "CX20642" },␊ |
487 | ␉{ HDA_CODEC_CX20651, 0, "CX20651" },␊ |
488 | ␉{ HDA_CODEC_CX20652, 0, "CX20652" },␊ |
489 | ␉{ HDA_CODEC_CX20664, 0, "CX20664" },␊ |
490 | ␉{ HDA_CODEC_CX20665, 0, "CX20665" },␊ |
491 | ␉{ HDA_CODEC_CX20751, 0,␉␉"CX20751/2" },␊ |
492 | ␉{ HDA_CODEC_CX20751_2, 0,␉"CX20751/2" },␊ |
493 | ␉{ HDA_CODEC_CX20751_4, 0,␉"CX20753/4" },␊ |
494 | ␉{ HDA_CODEC_CX20755, 0, "CX20755" },␊ |
495 | ␉{ HDA_CODEC_CX20756, 0, "CX20756" },␊ |
496 | ␉{ HDA_CODEC_CX20757, 0, "CX20757" },␊ |
497 | ␉{ HDA_CODEC_CX20952, 0, "CX20952" },␊ |
498 | ␊ |
499 | ␉{ HDA_CODEC_VT1708_8, 0, "VT1708_8" },␊ |
500 | ␉{ HDA_CODEC_VT1708_9, 0, "VT1708_9" },␊ |
501 | ␉{ HDA_CODEC_VT1708_A, 0, "VT1708_A" },␊ |
502 | ␉{ HDA_CODEC_VT1708_B, 0, "VT1708_B" },␊ |
503 | ␉{ HDA_CODEC_VT1709_0, 0, "VT1709_0" },␊ |
504 | ␉{ HDA_CODEC_VT1709_1, 0, "VT1709_1" },␊ |
505 | ␉{ HDA_CODEC_VT1709_2, 0, "VT1709_2" },␊ |
506 | ␉{ HDA_CODEC_VT1709_3, 0, "VT1709_3" },␊ |
507 | ␉{ HDA_CODEC_VT1709_4, 0, "VT1709_4" },␊ |
508 | ␉{ HDA_CODEC_VT1709_5, 0, "VT1709_5" },␊ |
509 | ␉{ HDA_CODEC_VT1709_6, 0, "VT1709_6" },␊ |
510 | ␉{ HDA_CODEC_VT1709_7, 0, "VT1709_7" },␊ |
511 | ␉{ HDA_CODEC_VT1708B_0, 0, "VT1708B_0" },␊ |
512 | ␉{ HDA_CODEC_VT1708B_1, 0, "VT1708B_1" },␊ |
513 | ␉{ HDA_CODEC_VT1708B_2, 0, "VT1708B_2" },␊ |
514 | ␉{ HDA_CODEC_VT1708B_3, 0, "VT1708B_3" },␊ |
515 | ␉{ HDA_CODEC_VT1708B_4, 0, "VT1708B_4" },␊ |
516 | ␉{ HDA_CODEC_VT1708B_5, 0, "VT1708B_5" },␊ |
517 | ␉{ HDA_CODEC_VT1708B_6, 0, "VT1708B_6" },␊ |
518 | ␉{ HDA_CODEC_VT1708B_7, 0, "VT1708B_7" },␊ |
519 | ␉{ HDA_CODEC_VT1708S_0, 0, "VT1708S_0" },␊ |
520 | ␉{ HDA_CODEC_VT1708S_1, 0, "VT1708S_1" },␊ |
521 | ␉{ HDA_CODEC_VT1708S_2, 0, "VT1708S_2" },␊ |
522 | ␉{ HDA_CODEC_VT1708S_3, 0, "VT1708S_3" },␊ |
523 | ␉{ HDA_CODEC_VT1708S_4, 0, "VT1708S_4" },␊ |
524 | ␉{ HDA_CODEC_VT1708S_5, 0, "VT1708S_5" },␊ |
525 | ␉{ HDA_CODEC_VT1708S_6, 0, "VT1708S_6" },␊ |
526 | ␉{ HDA_CODEC_VT1708S_7, 0, "VT1708S_7" },␊ |
527 | ␉{ HDA_CODEC_VT1702_0, 0, "VT1702_0" },␊ |
528 | ␉{ HDA_CODEC_VT1702_1, 0, "VT1702_1" },␊ |
529 | ␉{ HDA_CODEC_VT1702_2, 0, "VT1702_2" },␊ |
530 | ␉{ HDA_CODEC_VT1702_3, 0, "VT1702_3" },␊ |
531 | ␉{ HDA_CODEC_VT1702_4, 0, "VT1702_4" },␊ |
532 | ␉{ HDA_CODEC_VT1702_5, 0, "VT1702_5" },␊ |
533 | ␉{ HDA_CODEC_VT1702_6, 0, "VT1702_6" },␊ |
534 | ␉{ HDA_CODEC_VT1702_7, 0, "VT1702_7" },␊ |
535 | ␉{ HDA_CODEC_VT1716S_0, 0, "VT1716S_0" },␊ |
536 | ␉{ HDA_CODEC_VT1716S_1, 0, "VT1716S_1" },␊ |
537 | ␉{ HDA_CODEC_VT1718S_0, 0, "VT1718S_0" },␊ |
538 | ␉{ HDA_CODEC_VT1718S_1, 0, "VT1718S_1" },␊ |
539 | ␉{ HDA_CODEC_VT1802_0, 0, "VT1802_0" },␊ |
540 | ␉{ HDA_CODEC_VT1802_1, 0, "VT1802_1" },␊ |
541 | ␉{ HDA_CODEC_VT1812, 0, "VT1812" },␊ |
542 | ␉{ HDA_CODEC_VT1818S, 0, "VT1818S" },␊ |
543 | ␉{ HDA_CODEC_VT1828S, 0, "VT1828S" },␊ |
544 | ␉{ HDA_CODEC_VT2002P_0, 0, "VT2002P_0" },␊ |
545 | ␉{ HDA_CODEC_VT2002P_1, 0, "VT2002P_1" },␊ |
546 | ␉{ HDA_CODEC_VT2020, 0, "VT2020" },␊ |
547 | ␊ |
548 | ␉{ HDA_CODEC_ATIRS600_1, 0, "RS600" },␊ |
549 | ␉{ HDA_CODEC_ATIRS600_2, 0, "RS600" },␊ |
550 | ␉{ HDA_CODEC_ATIRS690, 0, "RS690/780" },␊ |
551 | ␉{ HDA_CODEC_ATIR6XX, 0, "R6xx" },␊ |
552 | ␊ |
553 | ␉{ HDA_CODEC_NVIDIAMCP67, 0, "MCP67" },␊ |
554 | ␉{ HDA_CODEC_NVIDIAMCP73, 0, "MCP73" },␊ |
555 | ␉{ HDA_CODEC_NVIDIAMCP78, 0, "MCP78" },␊ |
556 | ␉{ HDA_CODEC_NVIDIAMCP78_2, 0, "MCP78" },␊ |
557 | ␉{ HDA_CODEC_NVIDIAMCP78_3, 0, "MCP78" },␊ |
558 | ␉{ HDA_CODEC_NVIDIAMCP78_4, 0, "MCP78" },␊ |
559 | ␉{ HDA_CODEC_NVIDIAMCP7A, 0, "MCP7A" },␊ |
560 | ␉{ HDA_CODEC_NVIDIAGT220, 0, "GT220" },␊ |
561 | ␉{ HDA_CODEC_NVIDIAGT21X, 0, "GT21x" },␊ |
562 | ␉{ HDA_CODEC_NVIDIAMCP89, 0, "MCP89" },␊ |
563 | ␉{ HDA_CODEC_NVIDIAGT240, 0, "GT240" },␊ |
564 | ␉{ HDA_CODEC_NVIDIAGTS450, 0, "GTS450" },␊ |
565 | ␉{ HDA_CODEC_NVIDIAGT440, 0, "GT440" }, // Revision Id: 0x100100␊ |
566 | ␉{ HDA_CODEC_NVIDIAGTX470, 0, "GT470" },␊ |
567 | ␉{ HDA_CODEC_NVIDIAGTX550, 0, "GTX550" },␊ |
568 | ␉{ HDA_CODEC_NVIDIAGTX570, 0, "GTX570" },␊ |
569 | ␉{ HDA_CODEC_NVIDIAGT610, 0,␉"GT610" },␊ |
570 | ␊ |
571 | ␊ |
572 | ␉{ HDA_CODEC_INTELIP, 0, "Ibex Peak" },␊ |
573 | ␉{ HDA_CODEC_INTELBL, 0, "Bearlake" },␊ |
574 | ␉{ HDA_CODEC_INTELCA, 0, "Cantiga" },␊ |
575 | ␉{ HDA_CODEC_INTELEL, 0, "Eaglelake" },␊ |
576 | ␉{ HDA_CODEC_INTELIP2, 0, "Ibex Peak" },␊ |
577 | ␉{ HDA_CODEC_INTELCPT, 0, "Cougar Point" },␊ |
578 | ␉{ HDA_CODEC_INTELPPT, 0, "Panther Point" },␊ |
579 | ␉{ HDA_CODEC_INTELLLP, 0, "Haswell" },␊ |
580 | ␉{ HDA_CODEC_INTELBRW, 0, "Broadwell" },␊ |
581 | ␉{ HDA_CODEC_INTELSKL, 0, "Skylake" },␊ |
582 | ␉{ HDA_CODEC_INTELBRO, 0, "Broxton" },␊ |
583 | ␉{ HDA_CODEC_INTELKAB, 0, "Kabylake" },␊ |
584 | ␉{ HDA_CODEC_INTELCDT, 0, "CedarTrail" },␊ |
585 | ␉{ HDA_CODEC_INTELVLV, 0, "Valleyview2" },␊ |
586 | ␉{ HDA_CODEC_INTELBSW, 0, "Braswell" },␊ |
587 | ␉{ HDA_CODEC_INTELCL, 0, "Crestline" },␊ |
588 | ␊ |
589 | ␉{ HDA_CODEC_SII1390, 0, "SiI1390 HDMi" },␊ |
590 | ␉{ HDA_CODEC_SII1392, 0, "SiI1392 HDMi" },␊ |
591 | ␊ |
592 | ␉// Unknown CODECs␊ |
593 | ␉{ HDA_CODEC_ADXXXX, 0, "Analog Devices" },␊ |
594 | ␉{ HDA_CODEC_AGEREXXXX, 0, "Lucent/Agere Systems" },␊ |
595 | ␉{ HDA_CODEC_ALCXXXX, 0, "Realtek" },␊ |
596 | ␉{ HDA_CODEC_ATIXXXX, 0, "ATI" },␊ |
597 | ␉{ HDA_CODEC_CAXXXX, 0, "Creative" },␊ |
598 | ␉{ HDA_CODEC_CMIXXXX, 0, "CMedia" },␊ |
599 | ␉{ HDA_CODEC_CMIXXXX2, 0, "CMedia" },␊ |
600 | ␉{ HDA_CODEC_CSXXXX, 0, "Cirrus Logic" },␊ |
601 | ␉{ HDA_CODEC_CXXXXX, 0, "Conexant" },␊ |
602 | ␉{ HDA_CODEC_CHXXXX, 0, "Chrontel" },␊ |
603 | //␉{ HDA_CODEC_LGXXXX, 0, "LG" },␊ |
604 | //␉{ HDA_CODEC_WMXXXX, 0, "Wolfson Microelectronics" },␊ |
605 | //␉{ HDA_CODEC_QEMUXXXX, 0, "QEMU" },␊ |
606 | ␉{ HDA_CODEC_IDTXXXX, 0, "IDT" },␊ |
607 | ␉{ HDA_CODEC_INTELXXXX, 0, "Intel" },␊ |
608 | ␉{ HDA_CODEC_MOTOXXXX, 0, "Motorola" },␊ |
609 | ␉{ HDA_CODEC_NVIDIAXXXX, 0, "NVIDIA" },␊ |
610 | ␉{ HDA_CODEC_SIIXXXX, 0, "Silicon Image" },␊ |
611 | ␉{ HDA_CODEC_STACXXXX, 0, "Sigmatel" },␊ |
612 | ␉{ HDA_CODEC_VTXXXX, 0, "VIA" },␊ |
613 | };␊ |
614 | ␊ |
615 | #define HDACC_CODECS_LEN (sizeof(know_codecs) / sizeof(know_codecs[0]))␊ |
616 | ␊ |
617 | /*****************␊ |
618 | * Device Methods␊ |
619 | *****************/␊ |
620 | ␊ |
621 | /* get HDA device name */␊ |
622 | static char *get_hda_controller_name(uint16_t controller_device_id, uint16_t controller_vendor_id)␊ |
623 | {␊ |
624 | ␉static char desc[128];␊ |
625 | ␊ |
626 | ␉const char *name_format = "Unknown HD Audio device %s";␊ |
627 | ␉uint32_t controller_model = ((controller_device_id << 16) | controller_vendor_id);␊ |
628 | ␉int i;␊ |
629 | ␊ |
630 | ␉/* Get format for vendor ID */␊ |
631 | ␉switch (controller_vendor_id)␊ |
632 | ␉{␊ |
633 | ␉␉case ATI_VENDORID:␊ |
634 | ␉␉␉name_format = "ATI %s HDA Controller (HDMi)"; break;␊ |
635 | ␊ |
636 | ␉␉case INTEL_VENDORID:␊ |
637 | ␉␉␉name_format = "Intel %s HDA Controller"; break;␊ |
638 | ␊ |
639 | ␉␉case NVIDIA_VENDORID:␊ |
640 | ␉␉␉name_format = "nVidia %s HDA Controller (HDMi)"; break;␊ |
641 | ␊ |
642 | ␉␉case RDC_VENDORID:␊ |
643 | ␉␉␉name_format = "RDC %s HDA Controller"; break;␊ |
644 | ␊ |
645 | ␉␉case SIS_VENDORID:␊ |
646 | ␉␉␉name_format = "SiS %s HDA Controller"; break;␊ |
647 | ␊ |
648 | ␉␉case ULI_VENDORID:␊ |
649 | ␉␉␉name_format = "ULI %s HDA Controller"; break;␊ |
650 | ␊ |
651 | ␉␉case VIA_VENDORID:␊ |
652 | ␉␉␉name_format = "VIA %s HDA Controller"; break;␊ |
653 | ␊ |
654 | ␉␉default:␊ |
655 | ␉␉␉break;␊ |
656 | ␉}␊ |
657 | ␊ |
658 | ␉for (i = 0; i < HDAC_DEVICES_LEN; i++)␊ |
659 | ␉{␊ |
660 | ␉␉if (know_hda_controller[i].model == controller_model)␊ |
661 | ␉␉{␊ |
662 | ␉␉␉snprintf(desc, sizeof(desc), name_format, know_hda_controller[i].desc);␊ |
663 | ␉␉␉return desc;␊ |
664 | ␉␉}␊ |
665 | ␉}␊ |
666 | ␊ |
667 | ␉/* Not in table */␊ |
668 | ␉snprintf(desc, sizeof(desc), "Unknown HDA device, vendor %04x, model %04x",␊ |
669 | ␉␉controller_vendor_id, controller_device_id);␊ |
670 | ␉return desc;␊ |
671 | }␊ |
672 | ␊ |
673 | /* get Codec name */␊ |
674 | static char *get_hda_codec_name( uint16_t codec_vendor_id, uint16_t codec_device_id, uint8_t codec_revision_id, uint8_t codec_stepping_id )␊ |
675 | {␊ |
676 | ␉static char desc[128];␊ |
677 | ␊ |
678 | ␉char␉␉*lName_format = NULL;␊ |
679 | ␉uint32_t␉lCodec_model = ((uint32_t)(codec_vendor_id) << 16) + (codec_device_id);␊ |
680 | ␉uint32_t␉lCodec_rev = (((uint16_t)(codec_revision_id) << 8) + codec_stepping_id);␊ |
681 | ␉int i;␊ |
682 | ␊ |
683 | ␉// Get format for vendor ID␊ |
684 | ␉switch ( codec_vendor_id ) // uint16_t␊ |
685 | ␉{␊ |
686 | ␉␉case ANALOGDEVICES_VENDORID:␊ |
687 | ␉␉␉lName_format = "Analog Devices %s"; break;␊ |
688 | ␊ |
689 | ␉␉case AGERE_VENDORID:␊ |
690 | ␉␉␉lName_format = "Agere Systems %s "; break;␊ |
691 | ␊ |
692 | ␉␉case REALTEK_VENDORID:␊ |
693 | ␉␉␉lName_format = "Realtek %s"; break;␊ |
694 | ␊ |
695 | ␉␉case ATI_VENDORID:␊ |
696 | ␉␉␉lName_format = "ATI %s"; break;␊ |
697 | ␊ |
698 | ␉␉case CREATIVE_VENDORID:␊ |
699 | ␉␉␉lName_format = "Creative %s"; break;␊ |
700 | ␊ |
701 | ␉␉case CMEDIA_VENDORID:␊ |
702 | ␉␉case CMEDIA2_VENDORID:␊ |
703 | ␉␉␉lName_format = "CMedia %s"; break;␊ |
704 | ␊ |
705 | ␉␉case CIRRUSLOGIC_VENDORID:␊ |
706 | ␉␉␉lName_format = "Cirrus Logic %s"; break;␊ |
707 | ␊ |
708 | ␉␉case CONEXANT_VENDORID:␊ |
709 | ␉␉␉lName_format = "Conexant %s"; break;␊ |
710 | ␊ |
711 | ␉␉case CHRONTEL_VENDORID:␊ |
712 | ␉␉␉lName_format = "Chrontel %s"; break;␊ |
713 | ␊ |
714 | ␉␉case IDT_VENDORID:␊ |
715 | ␉␉␉lName_format = "IDT %s"; break;␊ |
716 | ␊ |
717 | ␉␉case INTEL_VENDORID:␊ |
718 | ␉␉␉lName_format = "Intel %s"; break;␊ |
719 | ␊ |
720 | ␉␉case MOTO_VENDORID:␊ |
721 | ␉␉␉lName_format = "Motorola %s"; break;␊ |
722 | ␊ |
723 | ␉␉case NVIDIA_VENDORID:␊ |
724 | ␉␉␉lName_format = "nVidia %s"; break;␊ |
725 | ␊ |
726 | ␉␉case SII_VENDORID:␊ |
727 | ␉␉␉lName_format = "Silicon Image %s"; break;␊ |
728 | ␊ |
729 | ␉␉case SIGMATEL_VENDORID:␊ |
730 | ␉␉␉lName_format = "Sigmatel %s"; break;␊ |
731 | ␊ |
732 | ␉␉case VIA_VENDORID:␊ |
733 | ␉␉␉lName_format = "VIA %s"; break;␊ |
734 | ␊ |
735 | ␉␉default:␊ |
736 | ␉␉␉lName_format = UNKNOWN; break;␊ |
737 | ␉␉␉break;␊ |
738 | ␉}␊ |
739 | ␊ |
740 | ␉for (i = 0; i < HDACC_CODECS_LEN; i++)␊ |
741 | ␉{␊ |
742 | ␉␉if ( know_codecs[i].id == lCodec_model )␊ |
743 | ␉␉{␊ |
744 | ␉␉␉if ( ( know_codecs[i].rev == 0x00000000 ) || ( know_codecs[i].rev == lCodec_rev ) )␊ |
745 | ␉␉␉{␊ |
746 | //␉␉␉␉verbose("\tRevision in table (%06x) | burned chip revision (%06x).\n", know_codecs[i].rev, lCodec_rev );␊ |
747 | ␉␉␉␉snprintf(desc, sizeof(desc), lName_format, know_codecs[i].name);␊ |
748 | ␉␉␉␉return desc;␊ |
749 | ␉␉␉}␊ |
750 | ␉␉}␊ |
751 | ␉}␊ |
752 | ␊ |
753 | ␉if ( ( lName_format != UNKNOWN ) && ( strstr(lName_format, "%s" ) != NULL ) )␊ |
754 | ␉{␊ |
755 | ␉␉// Dirty way to remove '%s' from the end of the lName_format␊ |
756 | ␉␉int len = strlen(lName_format);␊ |
757 | ␉␉lName_format[len-2] = '\0';␊ |
758 | ␉}␊ |
759 | ␊ |
760 | ␉// Not in table␊ |
761 | ␉snprintf(desc, sizeof(desc), "unknown %s Codec", lName_format);␊ |
762 | ␉return desc;␊ |
763 | }␊ |
764 | ␊ |
765 | bool setup_hda_devprop(pci_dt_t *hda_dev)␊ |
766 | {␊ |
767 | ␉struct␉␉DevPropDevice␉*device = NULL;␊ |
768 | ␉char␉␉*devicepath = NULL;␊ |
769 | ␉char␉␉*controller_name = NULL;␊ |
770 | ␉int␉␉len;␊ |
771 | ␉uint8_t␉␉BuiltIn = 0x00;␊ |
772 | ␉uint16_t␉controller_vendor_id = hda_dev->vendor_id;␊ |
773 | ␉uint16_t␉controller_device_id = hda_dev->device_id;␊ |
774 | ␉const char␉*value;␊ |
775 | ␊ |
776 | ␉// Skip keys␊ |
777 | ␉bool do_skip_n_devprop = false;␊ |
778 | ␉bool do_skip_a_devprop = false;␊ |
779 | ␉getBoolForKey(kSkipNvidiaGfx, &do_skip_n_devprop, &bootInfo->chameleonConfig);␊ |
780 | ␉getBoolForKey(kSkipAtiGfx, &do_skip_a_devprop, &bootInfo->chameleonConfig);␊ |
781 | ␊ |
782 | ␉verbose("\tClass code: [%04X]\n", hda_dev->class_id);␊ |
783 | ␊ |
784 | ␉devicepath = get_pci_dev_path(hda_dev);␊ |
785 | ␉controller_name = get_hda_controller_name(controller_device_id, controller_vendor_id);␊ |
786 | ␊ |
787 | ␉if (!string)␊ |
788 | ␉{␊ |
789 | ␉␉string = devprop_create_string();␊ |
790 | ␉␉if (!string)␊ |
791 | ␉␉{␊ |
792 | ␉␉␉return 0;␊ |
793 | ␉␉}␊ |
794 | ␉}␊ |
795 | ␊ |
796 | ␉if (!devicepath)␊ |
797 | ␉{␊ |
798 | ␉␉return 0;␊ |
799 | ␉}␊ |
800 | ␊ |
801 | ␉device = devprop_add_device(string, devicepath);␊ |
802 | ␉if (!device)␊ |
803 | ␉{␊ |
804 | ␉␉return 0;␊ |
805 | ␉}␊ |
806 | ␊ |
807 | ␉verbose("\tModel name: %s [%04x:%04x] (rev %02x)\n\tSubsystem: [%04x:%04x]\n\t%s\n",␊ |
808 | ␉␉ controller_name, hda_dev->vendor_id, hda_dev->device_id, hda_dev->revision_id,␊ |
809 | ␉␉hda_dev->subsys_id.subsys.vendor_id, hda_dev->subsys_id.subsys.device_id, devicepath);␊ |
810 | ␊ |
811 | ␉probe_hda_bus(hda_dev->dev.addr);␊ |
812 | ␊ |
813 | ␉switch ((controller_device_id << 16) | controller_vendor_id)␊ |
814 | ␉{␊ |
815 | ␊ |
816 | ␉/***********************************************************************␊ |
817 | ␉* The above case are intended as for HDEF device at address 0x001B0000␊ |
818 | ␉***********************************************************************/␊ |
819 | ␉␉case HDA_INTEL_OAK:␊ |
820 | ␉␉case HDA_INTEL_BAY:␊ |
821 | ␉␉case HDA_INTEL_HSW1:␊ |
822 | ␉␉case HDA_INTEL_HSW2:␊ |
823 | ␉␉case HDA_INTEL_HSW3:␊ |
824 | ␉␉case HDA_INTEL_BDW:␊ |
825 | ␉␉case HDA_INTEL_CPT:␊ |
826 | ␉␉case HDA_INTEL_PATSBURG:␊ |
827 | ␉␉case HDA_INTEL_PPT1:␊ |
828 | ␉␉case HDA_INTEL_BRASWELL:␊ |
829 | ␉␉case HDA_INTEL_82801F:␊ |
830 | ␉␉case HDA_INTEL_63XXESB:␊ |
831 | ␉␉case HDA_INTEL_82801G:␊ |
832 | ␉␉case HDA_INTEL_82801H:␊ |
833 | ␉␉case HDA_INTEL_82801I:␊ |
834 | ␉␉case HDA_INTEL_ICH9:␊ |
835 | ␉␉case HDA_INTEL_82801JI:␊ |
836 | ␉␉case HDA_INTEL_82801JD:␊ |
837 | ␉␉case HDA_INTEL_PCH:␊ |
838 | ␉␉case HDA_INTEL_PCH2:␊ |
839 | ␉␉case HDA_INTEL_SCH:␊ |
840 | ␉␉case HDA_INTEL_LPT1:␊ |
841 | ␉␉case HDA_INTEL_LPT2:␊ |
842 | ␉␉case HDA_INTEL_WCPT:␊ |
843 | ␉␉case HDA_INTEL_WELLS1:␊ |
844 | ␉␉case HDA_INTEL_WELLS2:␊ |
845 | ␉␉case HDA_INTEL_WCPTLP:␊ |
846 | ␉␉case HDA_INTEL_LPTLP1:␊ |
847 | ␉␉case HDA_INTEL_LPTLP2:␊ |
848 | ␉␉case HDA_INTEL_SRSPLP:␊ |
849 | ␉␉case HDA_INTEL_SRSP:␊ |
850 | ␊ |
851 | ␉␉␉/* if the key value kHDEFLayoutID as a value set that value, if not will assign a default layout */␊ |
852 | ␉␉␉if (getValueForKey(kHDEFLayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDEF_LEN * 2)␊ |
853 | ␉␉␉{␊ |
854 | ␉␉␉␉uint8_t new_HDEF_layout_id[HDEF_LEN];␊ |
855 | ␉␉␉␉if (hex2bin(value, new_HDEF_layout_id, HDEF_LEN) == 0)␊ |
856 | ␉␉␉␉{␊ |
857 | ␉␉␉␉␉memcpy(default_HDEF_layout_id, new_HDEF_layout_id, HDEF_LEN);␊ |
858 | ␉␉␉␉␉verbose("\tUsing user supplied HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
859 | ␉␉␉␉␉default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]);␊ |
860 | ␉␉␉␉}␊ |
861 | ␉␉␉}␊ |
862 | ␉␉␉else␊ |
863 | ␉␉␉{␊ |
864 | ␉␉␉␉verbose("\tUsing default HDEF layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
865 | ␉␉␉␉␉default_HDEF_layout_id[0], default_HDEF_layout_id[1], default_HDEF_layout_id[2], default_HDEF_layout_id[3]);␊ |
866 | ␉␉␉}␊ |
867 | ␉␉␉devprop_add_value(device, "layout-id", default_HDEF_layout_id, HDEF_LEN);␊ |
868 | ␉␉␉devprop_add_value(device, "AAPL,slot-name", (uint8_t *)"Built-in", sizeof("Built-in")); // 0x09␊ |
869 | ␉␉␉devprop_add_value(device, "name", (uint8_t *)"audio", 6); // 0x06␊ |
870 | ␉␉␉devprop_add_value(device, "device-type", (uint8_t *)"High Definition Audio Controller", sizeof("High Definition Audio Controller"));␊ |
871 | ␉␉␉devprop_add_value(device, "device_type", (uint8_t *)"Sound", sizeof("Sound"));␊ |
872 | ␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊ |
873 | ␉␉␉devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-1", sizeof("onboard-1")); // 0x0a␊ |
874 | ␉␉␉// "AFGLowPowerState" = <03000000>␊ |
875 | ␉␉␉break;␊ |
876 | ␊ |
877 | ␉/*****************************************************************************************************************␊ |
878 | ␉ * The above case are intended as for HDAU (NVIDIA) device onboard audio for GFX card with Audio controller HDMi *␊ |
879 | ␉ *****************************************************************************************************************/␊ |
880 | ␉␉case HDA_NVIDIA_GK107:␊ |
881 | ␉␉case HDA_NVIDIA_GF110_1:␊ |
882 | ␉␉case HDA_NVIDIA_GF110_2:␊ |
883 | ␉␉case HDA_NVIDIA_GK106:␊ |
884 | ␉␉case HDA_NVIDIA_GK104:␊ |
885 | ␉␉case HDA_NVIDIA_GF119:␊ |
886 | ␉␉case HDA_NVIDIA_GT116:␊ |
887 | ␉␉case HDA_NVIDIA_GT104:␊ |
888 | ␉␉case HDA_NVIDIA_GT108:␊ |
889 | ␉␉case HDA_NVIDIA_GT106:␊ |
890 | ␉␉case HDA_NVIDIA_GT100:␊ |
891 | ␉␉case HDA_NVIDIA_0BE4:␊ |
892 | ␉␉case HDA_NVIDIA_0BE3:␊ |
893 | ␉␉case HDA_NVIDIA_0BE2:␊ |
894 | ␉␉␉if ( do_skip_n_devprop )␊ |
895 | ␉␉␉{␊ |
896 | ␉␉␉␉verbose("Skip Nvidia audio device!\n");␊ |
897 | ␉␉␉}␊ |
898 | ␉␉␉else␊ |
899 | ␉␉␉{␊ |
900 | ␉␉␉␉/* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */␊ |
901 | ␉␉␉␉if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2)␊ |
902 | ␉␉␉␉{␊ |
903 | ␉␉␉␉␉uint8_t new_HDAU_layout_id[HDAU_LEN];␊ |
904 | ␉␉␉␉␉if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0)␊ |
905 | ␉␉␉␉␉{␊ |
906 | ␉␉␉␉␉␉memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN);␊ |
907 | ␉␉␉␉␉␉verbose("\tUsing user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
908 | ␉␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
909 | ␉␉␉␉␉}␊ |
910 | ␉␉␉␉}␊ |
911 | ␉␉␉␉else␊ |
912 | ␉␉␉␉{␊ |
913 | ␉␉␉␉␉verbose("\tUsing default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
914 | ␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
915 | ␉␉␉␉}␊ |
916 | ␊ |
917 | ␉␉␉␉devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/␊ |
918 | ␉␉␉␉devprop_add_value(device, "@0,connector-type", connector_type_value, 4);␊ |
919 | ␉␉␉␉devprop_add_value(device, "@1,connector-type", connector_type_value, 4);␊ |
920 | ␉␉␉␉devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", sizeof("onboard-2"));␊ |
921 | ␉␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊ |
922 | ␉␉␉}␊ |
923 | ␉␉␉break;␊ |
924 | ␊ |
925 | ␉␉/**************************************************************************************************************␊ |
926 | ␉␉ * The above case are intended as for HDAU (ATi) device onboard audio for GFX card with Audio controller HDMi *␊ |
927 | ␉␉ **************************************************************************************************************/␊ |
928 | ␉␉case HDA_ATI_SB450:␊ |
929 | ␉␉case HDA_ATI_SB600:␊ |
930 | ␉␉case HDA_ATI_HUDSON:␊ |
931 | ␉␉case HDA_ATI_RS600:␊ |
932 | ␉␉case HDA_ATI_RS690:␊ |
933 | ␉␉case HDA_ATI_RS780:␊ |
934 | ␉␉case HDA_ATI_R600:␊ |
935 | ␉␉case HDA_ATI_RV630:␊ |
936 | ␉␉case HDA_ATI_RV610:␊ |
937 | ␉␉case HDA_ATI_RV670:␊ |
938 | ␉␉case HDA_ATI_RV635:␊ |
939 | ␉␉case HDA_ATI_RV620:␊ |
940 | ␉␉case HDA_ATI_RV770:␊ |
941 | ␉␉case HDA_ATI_RV730:␊ |
942 | ␉␉case HDA_ATI_RV710:␊ |
943 | ␉␉case HDA_ATI_RV740:␊ |
944 | ␉␉case HDA_ATI_RV870:␊ |
945 | ␉␉case HDA_ATI_RV840:␊ |
946 | ␉␉case HDA_ATI_RV830:␊ |
947 | ␉␉case HDA_ATI_RV810:␊ |
948 | ␉␉case HDA_ATI_RV970:␊ |
949 | ␉␉case HDA_ATI_RV940:␊ |
950 | ␉␉case HDA_ATI_RV930:␊ |
951 | ␉␉case HDA_ATI_RV910:␊ |
952 | ␉␉case HDA_ATI_R1000:␊ |
953 | ␉␉case HDA_ATI_SI:␊ |
954 | ␉␉case HDA_ATI_VERDE:␊ |
955 | ␉␉␉if ( do_skip_a_devprop )␊ |
956 | ␉␉␉{␊ |
957 | ␉␉␉␉verbose("Skip ATi/AMD audio device!\n");␊ |
958 | ␉␉␉}␊ |
959 | ␉␉␉else␊ |
960 | ␉␉␉{␊ |
961 | ␉␉␉␉/* if the key value kHDAULayoutID as a value set that value, if not will assign a default layout */␊ |
962 | ␉␉␉␉if (getValueForKey(kHDAULayoutID, &value, &len, &bootInfo->chameleonConfig) && len == HDAU_LEN * 2)␊ |
963 | ␉␉␉␉{␊ |
964 | ␉␉␉␉␉uint8_t new_HDAU_layout_id[HDAU_LEN];␊ |
965 | ␉␉␉␉␉if (hex2bin(value, new_HDAU_layout_id, HDAU_LEN) == 0)␊ |
966 | ␉␉␉␉␉{␊ |
967 | ␉␉␉␉␉␉memcpy(default_HDAU_layout_id, new_HDAU_layout_id, HDAU_LEN);␊ |
968 | ␉␉␉␉␉␉verbose("\tUsing user supplied HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
969 | ␉␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
970 | ␉␉␉␉␉}␊ |
971 | ␉␉␉␉}␊ |
972 | ␉␉␉␉else␊ |
973 | ␉␉␉␉{␊ |
974 | ␉␉␉␉␉verbose("\tUsing default HDAU layout-id: 0x%02x, 0x%02x, 0x%02x, 0x%02x\n",␊ |
975 | ␉␉␉␉␉␉default_HDAU_layout_id[0], default_HDAU_layout_id[1], default_HDAU_layout_id[2], default_HDAU_layout_id[3]);␊ |
976 | ␉␉␉␉}␊ |
977 | ␊ |
978 | ␉␉␉␉devprop_add_value(device, "layout-id", default_HDAU_layout_id, HDAU_LEN); /*FIX ME*/␊ |
979 | ␉␉␉␉devprop_add_value(device, "hda-gfx", (uint8_t *)"onboard-2", 10);␊ |
980 | ␉␉␉␉devprop_add_value(device, "built-in", &BuiltIn, 1);␊ |
981 | ␉␉␉}␊ |
982 | ␉␉␉break;␊ |
983 | ␊ |
984 | ␉␉default:␊ |
985 | ␉␉␉break;␊ |
986 | ␉}␊ |
987 | ␊ |
988 | ␉stringdata = malloc(sizeof(uint8_t) * string->length);␊ |
989 | ␉memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);␊ |
990 | ␉stringlength = string->length;␊ |
991 | ␊ |
992 | ␉return true;␊ |
993 | }␊ |
994 | ␊ |
995 | /*␊ |
996 | * Structure of HDA MMIO Region␊ |
997 | */␊ |
998 | struct HDARegs␊ |
999 | {␊ |
1000 | ␉uint16_t gcap;␊ |
1001 | ␉uint8_t vmin;␊ |
1002 | ␉uint8_t vmaj;␊ |
1003 | ␉uint16_t outpay;␊ |
1004 | ␉uint16_t inpay;␊ |
1005 | ␉uint32_t gctl;␊ |
1006 | ␉uint16_t wakeen;␊ |
1007 | ␉uint16_t statests;␊ |
1008 | ␉uint16_t gsts;␊ |
1009 | ␉uint8_t rsvd0[6];␊ |
1010 | ␉uint16_t outstrmpay;␊ |
1011 | ␉uint16_t instrmpay;␊ |
1012 | ␉uint8_t rsvd1[4];␊ |
1013 | ␉uint32_t intctl;␊ |
1014 | ␉uint32_t intsts;␊ |
1015 | ␉uint8_t rsvd2[8];␊ |
1016 | ␉uint32_t walclk;␊ |
1017 | ␉uint8_t rsvd3[4];␊ |
1018 | ␉uint32_t ssync;␊ |
1019 | ␉uint8_t rsvd4[4];␊ |
1020 | ␉uint32_t corblbase;␊ |
1021 | ␉uint32_t corbubase;␊ |
1022 | ␉uint16_t corbwp;␊ |
1023 | ␉uint16_t corbrp;␊ |
1024 | ␉uint8_t corbctl;␊ |
1025 | ␉uint8_t corbsts;␊ |
1026 | ␉uint8_t corbsize;␊ |
1027 | ␉uint8_t rsvd5;␊ |
1028 | ␉uint32_t rirblbase;␊ |
1029 | ␉uint32_t rirbubase;␊ |
1030 | ␉uint16_t rirbwp;␊ |
1031 | ␉uint16_t rintcnt;␊ |
1032 | ␉uint8_t rirbctl;␊ |
1033 | ␉uint8_t rirbsts;␊ |
1034 | ␉uint8_t rirbsize;␊ |
1035 | ␉uint8_t rsvd6;␊ |
1036 | ␉uint32_t icoi;␊ |
1037 | ␉uint32_t icii;␊ |
1038 | ␉uint16_t icis;␊ |
1039 | ␉uint8_t rsvd7[6];␊ |
1040 | ␉uint32_t dpiblbase;␊ |
1041 | ␉uint32_t dpibubase;␊ |
1042 | ␉uint8_t rsvd8[8];␊ |
1043 | /*␊ |
1044 | * Stream Descriptors follow␊ |
1045 | */␊ |
1046 | } __attribute__((aligned(16), packed));␊ |
1047 | ␊ |
1048 | /*␊ |
1049 | * Data to be discovered for HDA codecs␊ |
1050 | */␊ |
1051 | ␊ |
1052 | struct HDACodecInfo␊ |
1053 | {␊ |
1054 | ␉uint16_t vendor_id;␊ |
1055 | ␉uint16_t device_id;␊ |
1056 | ␉uint8_t revision_id;␊ |
1057 | ␉uint8_t stepping_id;␊ |
1058 | ␉uint8_t maj_rev;␊ |
1059 | ␉uint8_t min_rev;␊ |
1060 | ␉uint8_t num_function_groups;␊ |
1061 | ␉const char *name;␊ |
1062 | };␊ |
1063 | ␊ |
1064 | /*␊ |
1065 | * Timing Functions␊ |
1066 | */␊ |
1067 | ␊ |
1068 | static int wait_for_register_state_16(uint16_t const volatile* reg,␊ |
1069 | ␉␉␉␉uint16_t target_mask,␊ |
1070 | ␉␉␉␉uint16_t target_value,␊ |
1071 | ␉␉␉␉uint32_t timeout_us,␊ |
1072 | ␉␉␉␉uint32_t tsc_ticks_per_us)␊ |
1073 | {␊ |
1074 | ␉uint64_t deadline = rdtsc64() + MultU32x32(timeout_us, tsc_ticks_per_us);␊ |
1075 | ␉do␊ |
1076 | ␉{␊ |
1077 | ␉␉uint16_t value = *reg;␊ |
1078 | ␉␉if ((value & target_mask) == target_value)␊ |
1079 | ␉␉␉return 0;␊ |
1080 | ␉␉CpuPause();␊ |
1081 | ␉}␊ |
1082 | ␉while (rdtsc64() < deadline);␊ |
1083 | ␉return -1;␊ |
1084 | }␊ |
1085 | ␊ |
1086 | static void delay_us(uint32_t timeout_us, uint32_t tsc_ticks_per_us)␊ |
1087 | {␊ |
1088 | ␉uint64_t deadline = rdtsc64() + MultU32x32(timeout_us, tsc_ticks_per_us);␊ |
1089 | ␊ |
1090 | ␉do␊ |
1091 | ␉{␊ |
1092 | ␉␉CpuPause();␊ |
1093 | ␉}␊ |
1094 | ␉while (rdtsc64() < deadline);␊ |
1095 | }␊ |
1096 | ␊ |
1097 | static struct HDARegs volatile* hdaMemory = NULL;␊ |
1098 | static uint32_t tsc_ticks_per_us = 0U;␊ |
1099 | ␊ |
1100 | #define ICIS_ICB 1U␊ |
1101 | #define ICIS_IRV 2U␊ |
1102 | ␊ |
1103 | static int immediate_command(uint32_t command, uint32_t* response)␊ |
1104 | {␊ |
1105 | ␉/*␊ |
1106 | ␉ * Wait up to 1ms for for ICB 0␊ |
1107 | ␉ */␊ |
1108 | ␉(void) wait_for_register_state_16(&hdaMemory->icis, ICIS_ICB, 0U, 1000U, tsc_ticks_per_us);␊ |
1109 | ␉/*␊ |
1110 | ␉ * Ignore timeout and force ICB to 0␊ |
1111 | ␉ * Clear IRV while at it␊ |
1112 | ␉ */␊ |
1113 | ␉hdaMemory->icis = ICIS_IRV;␊ |
1114 | ␉/*␊ |
1115 | ␉ * Program command␊ |
1116 | ␉ */␊ |
1117 | ␉hdaMemory->icoi = command;␊ |
1118 | ␉/*␊ |
1119 | ␉ * Trigger command␊ |
1120 | ␉ * Clear IRV again just in case␊ |
1121 | ␉ */␊ |
1122 | ␉hdaMemory->icis = ICIS_ICB | ICIS_IRV;␊ |
1123 | ␉/*␊ |
1124 | ␉ * Wait up to 1ms for response␊ |
1125 | ␉ */␊ |
1126 | ␉if (wait_for_register_state_16(&hdaMemory->icis, ICIS_IRV, ICIS_IRV, 1000U, tsc_ticks_per_us) < 0)␊ |
1127 | ␉{␊ |
1128 | ␉␉/*␊ |
1129 | ␉␉ * response timed out␊ |
1130 | ␉␉ */␊ |
1131 | ␉␉return -1;␊ |
1132 | ␉}␊ |
1133 | ␉*response = hdaMemory->icii;␊ |
1134 | ␉return 0;␊ |
1135 | }␊ |
1136 | ␊ |
1137 | #define PACK_CID(x) ((x & 15U) << 28)␊ |
1138 | #define PACK_NID(x) ((x & 127U) << 20)␊ |
1139 | #define PACK_VERB_12BIT(x) ((x & 4095U) << 8)␊ |
1140 | #define PACK_PAYLOAD_8BIT(x) (x & UINT8_MAX)␊ |
1141 | #define VERB_GET_PARAMETER 0xF00U␊ |
1142 | ␊ |
1143 | static uint32_t get_parameter(uint8_t codec_id, uint8_t node_id, uint8_t parameter_id)␊ |
1144 | {␊ |
1145 | ␉uint32_t command, response;␊ |
1146 | ␊ |
1147 | ␉command = PACK_CID(codec_id) | PACK_NID(node_id) | PACK_VERB_12BIT(VERB_GET_PARAMETER) | PACK_PAYLOAD_8BIT(parameter_id);␊ |
1148 | ␉response = UINT32_MAX;␊ |
1149 | ␊ |
1150 | ␉/*␊ |
1151 | ␉ * Ignore timeout, return UINT32_MAX as error value␊ |
1152 | ␉ */␊ |
1153 | ␉(void) immediate_command(command, &response);␊ |
1154 | ␉return response;␊ |
1155 | }␊ |
1156 | ␊ |
1157 | #define PARAMETER_VID_DID 0U␊ |
1158 | #define PARAMETER_RID 2U␊ |
1159 | #define PARAMETER_NUM_NODES 4U␊ |
1160 | ␊ |
1161 | static void probe_hda_codec(uint8_t codec_id, struct HDACodecInfo *codec_info)␊ |
1162 | {␊ |
1163 | ␉uint32_t response;␊ |
1164 | ␉CDBG("\tprobing codec %d\n", codec_id);␊ |
1165 | ␉response = get_parameter(codec_id, 0U, PARAMETER_VID_DID);␊ |
1166 | ␉codec_info->vendor_id = (response >> 16) & UINT16_MAX;␊ |
1167 | ␉codec_info->device_id = response & UINT16_MAX;␊ |
1168 | ␉response = get_parameter(codec_id, 0U, PARAMETER_RID);␊ |
1169 | ␉codec_info->revision_id = (response >> 8) & UINT8_MAX;␊ |
1170 | ␉codec_info->stepping_id = response & UINT8_MAX;␊ |
1171 | ␉codec_info->maj_rev = (response >> 20) & 15U;␊ |
1172 | ␉codec_info->min_rev = (response >> 16) & 15U;␊ |
1173 | ␉response = get_parameter(codec_id, 0U, PARAMETER_NUM_NODES);␊ |
1174 | ␉codec_info->num_function_groups = response & UINT8_MAX;␊ |
1175 | ␉codec_info->name = get_hda_codec_name(codec_info->vendor_id, codec_info->device_id, codec_info->revision_id, codec_info->stepping_id);␊ |
1176 | ␊ |
1177 | }␊ |
1178 | ␊ |
1179 | static int getHDABar(uint32_t pci_addr, uint32_t* bar_phys_addr)␊ |
1180 | {␊ |
1181 | ␉uint32_t barlow = pci_config_read32(pci_addr, PCI_BASE_ADDRESS_0);␊ |
1182 | ␊ |
1183 | ␉if ((barlow & PCI_BASE_ADDRESS_SPACE) != PCI_BASE_ADDRESS_SPACE_MEMORY)␊ |
1184 | ␉{␊ |
1185 | ␉␉CDBG("\tBAR0 for HDA Controller 0x%x is not an MMIO space\n", pci_addr);␊ |
1186 | ␉␉return -1;␊ |
1187 | ␉}␊ |
1188 | ␊ |
1189 | ␉if ((barlow & PCI_BASE_ADDRESS_MEM_TYPE_MASK) == PCI_BASE_ADDRESS_MEM_TYPE_64)␊ |
1190 | ␉{␊ |
1191 | ␉␉uint32_t barhigh = pci_config_read32(pci_addr, PCI_BASE_ADDRESS_1);␊ |
1192 | ␊ |
1193 | ␉␉if (barhigh)␊ |
1194 | ␉␉{␊ |
1195 | ␉␉␉//verbose("\tBAR0 for HDA Controller 0x%x is located ouside 32-bit physical address space (0x%x%08x)\n",␊ |
1196 | ␉␉␉//pci_addr, barhigh, barlow & PCI_BASE_ADDRESS_MEM_MASK);␊ |
1197 | ␉␉␉return -1;␊ |
1198 | ␉␉}␊ |
1199 | ␉}␊ |
1200 | ␊ |
1201 | ␉if (bar_phys_addr)␊ |
1202 | ␉{␊ |
1203 | ␉␉*bar_phys_addr = (barlow & PCI_BASE_ADDRESS_MEM_MASK);␊ |
1204 | ␉}␊ |
1205 | ␉return 0;␊ |
1206 | }␊ |
1207 | ␊ |
1208 | void probe_hda_bus(uint32_t pci_addr)␊ |
1209 | {␊ |
1210 | ␉uint64_t tsc_frequency;␊ |
1211 | ␉uint32_t bar_phys_addr;␊ |
1212 | ␉uint16_t pci_cmd, statests;␊ |
1213 | ␉uint16_t const pci_cmd_wanted = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;␊ |
1214 | ␉uint8_t codec_id, original_reset_state;␊ |
1215 | ␉struct HDACodecInfo codec_info;␊ |
1216 | ␊ |
1217 | ␉CDBG("\tlooking for HDA bar0 on pci_addr 0x%x\n", pci_addr);␊ |
1218 | ␉if (getHDABar(pci_addr, &bar_phys_addr) < 0)␊ |
1219 | ␉{␊ |
1220 | ␉␉return;␊ |
1221 | ␉}␊ |
1222 | ␊ |
1223 | ␉CDBG("\tfound HDA memory at 0x%x\n", bar_phys_addr);␊ |
1224 | ␉hdaMemory = (struct HDARegs volatile*) bar_phys_addr;␊ |
1225 | ␊ |
1226 | ␉tsc_frequency = Platform.CPU.TSCFrequency;␊ |
1227 | ␉tsc_ticks_per_us = DivU64x32(tsc_frequency, 1000000U); // TSC ticks per microsecond␊ |
1228 | ␉CDBG("\ttsc_ticks_per_us %d\n", tsc_ticks_per_us);␊ |
1229 | ␊ |
1230 | ␉/*␊ |
1231 | ␉ * Enable Memory Space and Bus Mastering␊ |
1232 | ␉ */␊ |
1233 | ␉pci_cmd = pci_config_read16(pci_addr, PCI_COMMAND);␊ |
1234 | ␉if ((pci_cmd & pci_cmd_wanted) != pci_cmd_wanted)␊ |
1235 | ␉{␊ |
1236 | ␉␉pci_cmd |= pci_cmd_wanted;␊ |
1237 | ␉␉pci_config_write16(pci_addr, PCI_COMMAND, pci_cmd);␊ |
1238 | ␉}␊ |
1239 | ␊ |
1240 | ␉/*␊ |
1241 | ␉ * Remember entering reset state␊ |
1242 | ␉ */␊ |
1243 | ␉original_reset_state = (hdaMemory->gctl & HDAC_GCTL_CRST) ? 1U : 0U;␊ |
1244 | ␊ |
1245 | ␉/*␊ |
1246 | ␉ * Reset HDA Controller␊ |
1247 | ␉ */␊ |
1248 | ␉hdaMemory->wakeen = 0U;␊ |
1249 | ␉hdaMemory->statests = UINT16_MAX;␊ |
1250 | ␉hdaMemory->gsts = UINT16_MAX;␊ |
1251 | ␉hdaMemory->intctl = 0U;␊ |
1252 | ␉CDBG("\tStarting reset\n");␊ |
1253 | ␉hdaMemory->gctl = 0U;␊ |
1254 | ␊ |
1255 | ␉/*␊ |
1256 | ␉ * Wait up to 10ms to enter Reset␊ |
1257 | ␉ */␊ |
1258 | ␉if (wait_for_register_state_16((uint16_t volatile const*) &hdaMemory->gctl,␊ |
1259 | ␉␉␉␉HDAC_GCTL_CRST,␊ |
1260 | ␉␉␉␉0U,␊ |
1261 | ␉␉␉␉10000U,␊ |
1262 | ␉␉␉␉tsc_ticks_per_us) < 0)␊ |
1263 | ␉{␊ |
1264 | ␉␉CDBG("\tHDA Controller 0x%x timed out 10ms entering reset\n", pci_addr);␊ |
1265 | ␉␉return;␊ |
1266 | ␉}␊ |
1267 | ␉CDBG("\tReset asserted, delay 100us\n");␊ |
1268 | ␊ |
1269 | ␉/*␊ |
1270 | ␉ * Delay 2400 BCLK (100us)␊ |
1271 | ␉ */␊ |
1272 | ␉delay_us(100U, tsc_ticks_per_us);␊ |
1273 | ␉CDBG("\tDeasserting reset\n");␊ |
1274 | ␊ |
1275 | ␉/*␊ |
1276 | ␉ * Wait up to 10ms to exit Reset␊ |
1277 | ␉ */␊ |
1278 | ␉hdaMemory->gctl = HDAC_GCTL_CRST;␊ |
1279 | ␉if (wait_for_register_state_16((uint16_t volatile const*) &hdaMemory->gctl,␊ |
1280 | ␉␉␉␉HDAC_GCTL_CRST,␊ |
1281 | ␉␉␉␉HDAC_GCTL_CRST,␊ |
1282 | ␉␉␉␉10000U,␊ |
1283 | ␉␉␉␉tsc_ticks_per_us) < 0)␊ |
1284 | ␉{␊ |
1285 | ␉␉CDBG("\tHDA Controller 0x%x timed out 10ms exiting reset\n", pci_addr);␊ |
1286 | ␉␉return;␊ |
1287 | ␉}␊ |
1288 | ␉CDBG("\tReset complete\n");␊ |
1289 | ␊ |
1290 | ␉/*␊ |
1291 | ␉ * Wait 1ms for codecs to request enumeration (spec says 521us).␊ |
1292 | ␉ */␊ |
1293 | ␉delay_us(1000U, tsc_ticks_per_us);␊ |
1294 | ␊ |
1295 | ␉/*␊ |
1296 | ␉ * See which codecs want enumeration␊ |
1297 | ␉ */␊ |
1298 | ␉statests = hdaMemory->statests;␊ |
1299 | ␉hdaMemory->statests = statests; // clear statests␊ |
1300 | ␉CDBG("\tstatests is now 0x%x\n", statests);␊ |
1301 | ␉codec_id = 0U;␊ |
1302 | ␉while (statests)␊ |
1303 | ␉{␊ |
1304 | ␉␉if (statests & 1U)␊ |
1305 | ␉␉{␊ |
1306 | ␉␉␉probe_hda_codec(codec_id, &codec_info);␊ |
1307 | ␊ |
1308 | ␉␉␉verbose("\tFound %s (%04x%04x), rev(%04x)",␊ |
1309 | ␉␉␉codec_info.name,␊ |
1310 | ␉␉␉codec_info.vendor_id,␊ |
1311 | ␉␉␉codec_info.device_id,␊ |
1312 | ␉␉␉codec_info.revision_id);␊ |
1313 | #if DEBUG_CODEC␊ |
1314 | ␉␉␉verbose(", stepping 0x%x, major rev 0x%x, minor rev 0x%x, %d function groups",␊ |
1315 | ␉␉␉codec_info.stepping_id,␊ |
1316 | ␉␉␉codec_info.maj_rev,␊ |
1317 | ␉␉␉codec_info.min_rev,␊ |
1318 | ␉␉␉codec_info.num_function_groups);␊ |
1319 | #endif␊ |
1320 | ␉␉␉verbose("\n");␊ |
1321 | ␉␉}␊ |
1322 | ␉␉++codec_id;␊ |
1323 | ␉␉statests >>= 1;␊ |
1324 | ␉}␊ |
1325 | ␊ |
1326 | ␉/*␊ |
1327 | ␉ * Restore reset state entered with␊ |
1328 | ␉ */␊ |
1329 | ␉if (!original_reset_state)␊ |
1330 | ␉{␊ |
1331 | ␉␉hdaMemory->gctl = 0U;␊ |
1332 | ␉}␊ |
1333 | }␊ |
1334 |