Root/
Source at commit HEAD created 5 years 6 days ago. By ifabio, Few update to kernelPatcher (Credits to CrazyBirdy) | |
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1 | /*␊ |
2 | *␉NVidia injector␊ |
3 | *␊ |
4 | *␉Copyright (C) 2009␉Jasmin Fazlic, iNDi␊ |
5 | *␊ |
6 | *␉NVidia injector modified by Fabio (ErmaC) on May 2012,␊ |
7 | *␉for allow the cosmetics injection also based on SubVendorID and SubDeviceID.␊ |
8 | *␊ |
9 | *␉NVidia injector is free software: you can redistribute it and/or modify␊ |
10 | *␉it under the terms of the GNU General Public License as published by␊ |
11 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
12 | *␉(at your option) any later version.␊ |
13 | *␊ |
14 | *␉NVidia driver and injector is distributed in the hope that it will be useful,␊ |
15 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
16 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
17 | *␉GNU General Public License for more details.␊ |
18 | *␊ |
19 | *␉You should have received a copy of the GNU General Public License␊ |
20 | *␉along with NVidia injector.␉ If not, see <http://www.gnu.org/licenses/>.␊ |
21 | *␊ |
22 | *␉Alternatively you can choose to comply with APSL␊ |
23 | *␊ |
24 | *␉DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:␊ |
25 | *␊ |
26 | *␊ |
27 | *␉Copyright 2005-2006 Erik Waling␊ |
28 | *␉Copyright 2006 Stephane Marchesin␊ |
29 | *␉Copyright 2007-2009 Stuart Bennett␊ |
30 | *␊ |
31 | *␉Permission is hereby granted, free of charge, to any person obtaining a␊ |
32 | *␉copy of this software and associated documentation files (the "Software"),␊ |
33 | *␉to deal in the Software without restriction, including without limitation␊ |
34 | *␉the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
35 | *␉and/or sell copies of the Software, and to permit persons to whom the␊ |
36 | *␉Software is furnished to do so, subject to the following conditions:␊ |
37 | *␊ |
38 | *␉The above copyright notice and this permission notice shall be included in␊ |
39 | *␉all copies or substantial portions of the Software.␊ |
40 | *␊ |
41 | *␉THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR␊ |
42 | *␉IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,␊ |
43 | *␉FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL␊ |
44 | *␉THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,␊ |
45 | *␉WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF␊ |
46 | *␉OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE␊ |
47 | *␉SOFTWARE.␊ |
48 | */␊ |
49 | ␊ |
50 | #ifndef __LIBSAIO_NVIDIA_H␊ |
51 | #define __LIBSAIO_NVIDIA_H␊ |
52 | ␊ |
53 | bool setup_nvidia_devprop(pci_dt_t *nvda_dev);␊ |
54 | ␊ |
55 | struct nvidia_pci_info_t;␊ |
56 | typedef struct {␊ |
57 | ␉uint32_t device; // VendorID + DeviceID␊ |
58 | ␉char *name_model;␊ |
59 | } nvidia_pci_info_t;␊ |
60 | ␊ |
61 | struct nvidia_card_info_t;␊ |
62 | typedef struct {␊ |
63 | ␉uint32_t device; // VendorID + DeviceID␊ |
64 | ␉uint32_t subdev; // SubdeviceID + SubvendorID␊ |
65 | ␉char *name_model;␊ |
66 | ␉//bool kEnableHDMIAudio //␉HDMi␊ |
67 | ␉//VRAM␊ |
68 | } nvidia_card_info_t;␊ |
69 | ␊ |
70 | #define DCB_MAX_NUM_ENTRIES 16␊ |
71 | #define DCB_MAX_NUM_I2C_ENTRIES 16␊ |
72 | #define DCB_MAX_NUM_GPIO_ENTRIES 32␊ |
73 | #define DCB_MAX_NUM_CONNECTOR_ENTRIES 16␊ |
74 | #define DCB_LOC_ON_CHIP 0␊ |
75 | ␊ |
76 | struct bios {␊ |
77 | ␉uint16_t␉signature;␉␉/* 0x55AA */␊ |
78 | ␉uint8_t␉␉size;␉␉␉/* Size in multiples of 512 */␊ |
79 | };␊ |
80 | ␊ |
81 | #define NV_PMC_OFFSET␉␉␉␉␉␉␉0x00000000␊ |
82 | #define NV_PMC_SIZE 0x00001000 // 0x2ffff␊ |
83 | #define NV_PDISPLAY_OFFSET␉␉␉␉␉␉0x610000␊ |
84 | #define NV_PDISPLAY_SIZE␉␉␉␉␉␉0x10000␊ |
85 | ␊ |
86 | #define NV_PROM_OFFSET␉␉␉␉␉␉␉0x00300000␊ |
87 | #define NV_PROM_SIZE␉␉␉␉␉␉␉0x00010000␊ |
88 | #define NV_PRAMIN_OFFSET␉␉␉␉␉␉0x00700000␊ |
89 | #define NV_PRAMIN_SIZE␉␉␉␉␉␉␉0x00100000␊ |
90 | #define NV04_PFB_FIFO_DATA␉␉␉␉␉␉0x0010020c␊ |
91 | #define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK␉␉␉␉0xfff00000␊ |
92 | #define NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_SHIFT␉␉␉␉20␊ |
93 | #define NVC0_MEM_CTRLR_RAM_AMOUNT␉␉␉␉␉0x0010f20c␊ |
94 | #define NVC0_MEM_CTRLR_COUNT␉␉␉␉␉␉0x00121c74␊ |
95 | ␊ |
96 | #define NV_PBUS_PCI_NV_19␉␉␉␉␉␉0x0000184C␊ |
97 | #define NV_PBUS_PCI_NV_20␉␉␉␉␉␉0x00001850␊ |
98 | #define NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED␉(0 << 0)␊ |
99 | #define NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED␉(1 << 0)␊ |
100 | ␊ |
101 | #define REG8(reg) ((volatile uint8_t *)regs)[(reg)]␊ |
102 | #define REG16(reg) ((volatile uint16_t *)regs)[(reg) >> 1]␊ |
103 | #define REG32(reg) ((volatile uint32_t *)regs)[(reg) >> 2]␊ |
104 | ␊ |
105 | #define NV_ARCH_03 0x03␊ |
106 | #define NV_ARCH_04 0x04␊ |
107 | #define NV_ARCH_10 0x10␊ |
108 | #define NV_ARCH_20 0x20␊ |
109 | #define NV_ARCH_30 0x30␊ |
110 | #define NV_ARCH_40 0x40␊ |
111 | #define NV_ARCH_50 0x50␊ |
112 | #define NV_ARCH_C0 0xC0␊ |
113 | #define NV_ARCH_D0 0xD0␊ |
114 | #define NV_ARCH_E0 0xE0␊ |
115 | ␊ |
116 | #define CHIPSET_NV03 0x0010␊ |
117 | #define CHIPSET_NV04 0x0020␊ |
118 | #define CHIPSET_NV10 0x0100␊ |
119 | #define CHIPSET_NV11 0x0110␊ |
120 | #define CHIPSET_NV15 0x0150␊ |
121 | #define CHIPSET_NV17 0x0170␊ |
122 | #define CHIPSET_NV18 0x0180␊ |
123 | #define CHIPSET_NFORCE 0x01A0␊ |
124 | #define CHIPSET_NFORCE2 0x01F0␊ |
125 | #define CHIPSET_NV20 0x0200␊ |
126 | #define CHIPSET_NV25 0x0250␊ |
127 | #define CHIPSET_NV28 0x0280␊ |
128 | #define CHIPSET_NV30 0x0300␊ |
129 | #define CHIPSET_NV31 0x0310␊ |
130 | #define CHIPSET_NV34 0x0320␊ |
131 | #define CHIPSET_NV35 0x0330␊ |
132 | #define CHIPSET_NV36 0x0340␊ |
133 | #define CHIPSET_NV40 0x0040␊ |
134 | #define CHIPSET_NV41 0x00C0␊ |
135 | #define CHIPSET_NV43 0x0140␊ |
136 | #define CHIPSET_NV44 0x0160␊ |
137 | #define CHIPSET_NV44A 0x0220␊ |
138 | #define CHIPSET_NV45 0x0210␊ |
139 | #define CHIPSET_NV50 0x0190␊ |
140 | #define CHIPSET_NV84 0x0400␊ |
141 | #define CHIPSET_MISC_BRIDGED 0x00F0␊ |
142 | #define CHIPSET_G70 0x0090␊ |
143 | #define CHIPSET_G71 0x0290␊ |
144 | #define CHIPSET_G72 0x01D0␊ |
145 | #define CHIPSET_G73 0x0390␊ |
146 | ␊ |
147 | // integrated GeForces (6100, 6150)␊ |
148 | #define CHIPSET_C51 0x0240␊ |
149 | ␊ |
150 | // variant of C51, seems based on a G70 design␊ |
151 | #define CHIPSET_C512 0x03D0␊ |
152 | #define CHIPSET_G73_BRIDGED 0x02E0␊ |
153 | ␊ |
154 | #endif /* !__LIBSAIO_NVIDIA_H */␊ |
155 |