Root/
Source at commit HEAD created 5 years 6 days ago. By ifabio, Few update to kernelPatcher (Credits to CrazyBirdy) | |
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1 | /*␊ |
2 | * Add (c) here␊ |
3 | *␊ |
4 | * Copyright .... All rights reserved.␊ |
5 | *␊ |
6 | */␊ |
7 | ␊ |
8 | #include "config.h"␊ |
9 | #include "smbios_getters.h"␊ |
10 | #include "bootstruct.h"␊ |
11 | ␊ |
12 | #if DEBUG_SMBIOS␊ |
13 | ␉#define DBG(x...)␉printf(x)␊ |
14 | #else␊ |
15 | ␉#define DBG(x...)␊ |
16 | #endif␊ |
17 | ␊ |
18 | #define XEON "Xeon"␊ |
19 | #define CORE_M "Core(TM) M"␊ |
20 | #define CORE_M3 "Core(TM) m3"␊ |
21 | #define CORE_M5 "Core(TM) m5"␊ |
22 | #define CORE_M7 "Core(TM) m7"␊ |
23 | #define CORE_I3 "Core(TM) i3"␊ |
24 | #define CORE_I5 "Core(TM) i5"␊ |
25 | #define CORE_I7 "Core(TM) i7"␊ |
26 | ␊ |
27 | bool getProcessorInformationExternalClock(returnType *value)␊ |
28 | {␊ |
29 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
30 | ␉{␊ |
31 | ␉␉switch (Platform.CPU.Family)␊ |
32 | ␉␉{␊ |
33 | ␉␉␉case 0x06:␊ |
34 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
35 | ␉␉␉␉{␊ |
36 | ␉␉␉␉␉// set external clock to 0 for SANDY␊ |
37 | ␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊ |
38 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␊ |
39 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␊ |
40 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
41 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␊ |
42 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
43 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␊ |
44 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␊ |
45 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␊ |
46 | ␊ |
47 | ␉␉␉␉␉␉value->word = 0;␊ |
48 | ␉␉␉␉␉␉break;␊ |
49 | ␉␉␉␉␉default:␊ |
50 | ␉␉␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
51 | ␉␉␉␉␉␉break;␊ |
52 | ␉␉␉␉}␊ |
53 | ␉␉␉␉break;␊ |
54 | ␊ |
55 | ␉␉␉default:␊ |
56 | ␉␉␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
57 | ␉␉␉␉break;␊ |
58 | ␉␉}␊ |
59 | ␉}␊ |
60 | ␉else␊ |
61 | ␉{␊ |
62 | ␉␉value->word = (uint16_t)(Platform.CPU.FSBFrequency/1000000LL);␊ |
63 | ␉}␊ |
64 | ␊ |
65 | ␉return true;␊ |
66 | }␊ |
67 | ␊ |
68 | bool getProcessorInformationMaximumClock(returnType *value)␊ |
69 | {␊ |
70 | ␉value->word = (uint16_t)(Platform.CPU.CPUFrequency/1000000LL);␊ |
71 | ␉return true;␊ |
72 | }␊ |
73 | ␊ |
74 | bool getSMBOemProcessorBusSpeed(returnType *value)␊ |
75 | {␊ |
76 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
77 | ␉{␊ |
78 | ␉␉switch (Platform.CPU.Family)␊ |
79 | ␉␉{␊ |
80 | ␉␉␉case 0x06:␊ |
81 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
82 | ␉␉␉␉{␊ |
83 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
84 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉// Intel Pentium M␊ |
85 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉// Intel Mobile Core Solo, Duo␊ |
86 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉// Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
87 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉// Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
88 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉// Intel Atom (45nm)␊ |
89 | ␉␉␉␉␉␉return false;␊ |
90 | ␊ |
91 | ␉␉␉␉␉case 0x19:␊ |
92 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
93 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
94 | ␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␊ |
95 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉// Intel Core i3, i5 LGA1156 (32nm)␊ |
96 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
97 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊ |
98 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊ |
99 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
100 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊ |
101 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
102 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␊ |
103 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␊ |
104 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␊ |
105 | ␉␉␉␉␉{␊ |
106 | ␉␉␉␉␉␉// thanks to dgobe for i3/i5/i7 bus speed detection␊ |
107 | ␉␉␉␉␉␉int nhm_bus = 0x3F;␊ |
108 | ␉␉␉␉␉␉static long possible_nhm_bus[] = {0xFF, 0x7F, 0x3F};␊ |
109 | ␉␉␉␉␉␉unsigned long did, vid;␊ |
110 | ␉␉␉␉␉␉unsigned long qpimult, qpibusspeed = 0;␊ |
111 | ␉␉␉␉␉␉int i;␊ |
112 | ␉␉␉␉␉␉␊ |
113 | ␉␉␉␉␉␉// Nehalem supports Scrubbing␊ |
114 | ␉␉␉␉␉␉// First, locate the PCI bus where the MCH is located␊ |
115 | ␉␉␉␉␉␉for(i = 0; i < (sizeof(possible_nhm_bus)/sizeof(possible_nhm_bus[0])); i++)␊ |
116 | ␉␉␉␉␉␉{␊ |
117 | ␉␉␉␉␉␉␉vid = (pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x00) & 0xFFFF);␊ |
118 | ␉␉␉␉␉␉␉did = (pci_config_read16(PCIADDR(possible_nhm_bus[i], 3, 4), 0x02) & 0xFF00);␊ |
119 | ␉␉␉␉␉␉␉␊ |
120 | ␉␉␉␉␉␉␉if(vid == 0x8086 && did >= 0x2C00)␊ |
121 | ␉␉␉␉␉␉␉{␊ |
122 | ␉␉␉␉␉␉␉␉nhm_bus = possible_nhm_bus[i];␊ |
123 | ␉␉␉␉␉␉␉}␊ |
124 | ␉␉␉␉␉␉}␊ |
125 | ␊ |
126 | ␉␉␉␉␉␉qpimult = (pci_config_read32(PCIADDR(nhm_bus, 2, 1), 0x50) & 0x7F);␊ |
127 | ␉␉␉␉␉␉DBG("qpimult %d\n", qpimult);␊ |
128 | ␉␉␉␉␉␉qpibusspeed = (qpimult * 2 * (Platform.CPU.FSBFrequency/1000000LL));␊ |
129 | ␉␉␉␉␉␉// Rek: rounding decimals to match original mac profile info␊ |
130 | ␉␉␉␉␉␉if (qpibusspeed % 100 != 0)␊ |
131 | ␉␉␉␉␉␉{␊ |
132 | ␉␉␉␉␉␉␉qpibusspeed = ((qpibusspeed + 50) / 100) * 100;␊ |
133 | ␉␉␉␉␉␉}␊ |
134 | ␉␉␉␉␉␉DBG("qpibusspeed %d\n", qpibusspeed);␊ |
135 | ␉␉␉␉␉␉value->word = qpibusspeed;␊ |
136 | ␉␉␉␉␉␉return true;␊ |
137 | ␉␉␉␉␉}␊ |
138 | ␉␉␉␉␉break;␊ |
139 | ␊ |
140 | ␉␉␉␉␉default:␊ |
141 | ␉␉␉␉␉␉break;␊ |
142 | ␉␉␉␉}␊ |
143 | ␉␉␉␉break;␊ |
144 | ␊ |
145 | ␉␉␉default:␊ |
146 | ␉␉␉␉break;␊ |
147 | ␉␉}␊ |
148 | ␉}␊ |
149 | ␊ |
150 | ␉return false; //Unsupported CPU type␊ |
151 | }␊ |
152 | ␊ |
153 | //bool getSMBOemPlatformFeature(returnType *value)␊ |
154 | //{␊ |
155 | // value->word = (uint64_t)(0x0000000000000001);␊ |
156 | // return true;␊ |
157 | //}␊ |
158 | ␊ |
159 | uint16_t simpleGetSMBOemProcessorType(void)␊ |
160 | {␊ |
161 | ␉if (Platform.CPU.NoCores >= 4)␊ |
162 | ␉{␊ |
163 | ␉␉return 0x402;␉// 1026 - Quad-Core Xeon␊ |
164 | ␉}␊ |
165 | ␉else if (Platform.CPU.NoCores == 1)␊ |
166 | ␉{␊ |
167 | ␉␉return 0x201;␉// 513 - Core Duo␊ |
168 | ␉};␊ |
169 | ␉␊ |
170 | ␉return 0x301;␉␉// 769 - Core 2 Duo␊ |
171 | }␊ |
172 | ␊ |
173 | bool getSMBOemProcessorType(returnType *value)␊ |
174 | {␊ |
175 | ␉static bool done = false;␊ |
176 | ␊ |
177 | ␉value->word = simpleGetSMBOemProcessorType();␊ |
178 | ␊ |
179 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_INTEL) // Intel␊ |
180 | ␉{␊ |
181 | ␉␉if (!done)␊ |
182 | ␉␉{␊ |
183 | ␉␉␉verbose("CPU is %s, family 0x%x, model 0x%x\n", Platform.CPU.BrandString, (uint32_t)Platform.CPU.Family, (uint32_t)Platform.CPU.Model);␊ |
184 | ␉␉␉done = true;␊ |
185 | ␉␉}␊ |
186 | ␊ |
187 | ␉␉switch (Platform.CPU.Family)␊ |
188 | ␉␉{␊ |
189 | ␉␉␉case 0x0F:␊ |
190 | ␉␉␉case 0x06:␊ |
191 | ␊ |
192 | ␉␉␉␉switch (Platform.CPU.Model)␊ |
193 | ␉␉␉␉{␊ |
194 | ␉␉␉␉␉case CPUID_MODEL_PENTIUM_M:␊ |
195 | ␉␉␉␉␉case CPUID_MODEL_DOTHAN:␉␉␉// 0x0D - Intel Pentium M model D␊ |
196 | ␉␉␉␉␉case CPUID_MODEL_PRESCOTT:␊ |
197 | ␉␉␉␉␉case CPUID_MODEL_NOCONA:␊ |
198 | ␊ |
199 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
200 | ␉␉␉␉␉␉{␊ |
201 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
202 | ␉␉␉␉␉␉␉return true;␊ |
203 | ␉␉␉␉␉␉}␊ |
204 | ␊ |
205 | ␉␉␉␉␉␉return true;␊ |
206 | ␊ |
207 | ␉␉␉␉␉case CPUID_MODEL_PRESLER:␊ |
208 | ␉␉␉␉␉case CPUID_MODEL_CONROE:␊ |
209 | ␉␉␉␉␉case CPUID_MODEL_YONAH:␉␉␉␉// 0x0E - Intel Mobile Core Solo, Duo␊ |
210 | ␉␉␉␉␉␉value->word = 0x201;␉␉␉// 513␊ |
211 | ␉␉␉␉␉␉return true;␊ |
212 | ␊ |
213 | ␉␉␉␉␉case CPUID_MODEL_MEROM:␉␉␉␉// 0x0F - Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊ |
214 | ␉␉␉␉␉case CPUID_MODEL_XEON_MP:␉␉␉// 0x1D - Six-Core Xeon 7400, "Dunnington", 45nm␊ |
215 | ␉␉␉␉␉case CPUID_MODEL_PENRYN:␉␉␉// 0x17 - Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊ |
216 | ␊ |
217 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
218 | ␉␉␉␉␉␉{␊ |
219 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Xeon␊ |
220 | ␉␉␉␉␉␉␉return true;␊ |
221 | ␉␉␉␉␉␉}␊ |
222 | ␊ |
223 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
224 | ␉␉␉␉␉␉{␊ |
225 | ␉␉␉␉␉␉␉value->word = 0x301;␉␉// 769 - Core 2 Duo␊ |
226 | ␉␉␉␉␉␉␉return true;␊ |
227 | ␉␉␉␉␉␉}␊ |
228 | ␉␉␉␉␉␉else␊ |
229 | ␉␉␉␉␉␉{␊ |
230 | ␉␉␉␉␉␉␉value->word = 0x402;␉␉// 1026 - Core 2 Quad as Xeon␊ |
231 | ␉␉␉␉␉␉␉return true;␊ |
232 | ␉␉␉␉␉␉}␊ |
233 | ␊ |
234 | ␉␉␉␉␉␉return true;␊ |
235 | ␊ |
236 | ␉␉␉␉␉case CPUID_MODEL_LINCROFT:␉␉␉// 0x27 - Intel Atom, "Lincroft", 45nm␊ |
237 | ␉␉␉␉␉case CPUID_MODEL_ATOM:␉␉␉␉// 0x1C - Intel Atom (45nm)␊ |
238 | ␊ |
239 | ␉␉␉␉␉␉return true;␊ |
240 | ␊ |
241 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM_EX:␉␉␉// 0x2E - Nehalem-ex, "Beckton", 45nm␊ |
242 | ␉␉␉␉␉case CPUID_MODEL_NEHALEM:␉␉␉// 0x1A - Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊ |
243 | ␉␉␉␉␉case CPUID_MODEL_FIELDS:␉␉␉// 0x1E - Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊ |
244 | ␉␉␉␉␉case CPUID_MODEL_CLARKDALE:␉␉␉// 0x1F - Intel Core i5, i7 LGA1156 (45nm) (Havendale, Auburndale)␊ |
245 | ␊ |
246 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
247 | ␉␉␉␉␉␉{␊ |
248 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Lynnfiled Quad-Core Xeon␊ |
249 | ␉␉␉␉␉␉␉return true;␊ |
250 | ␉␉␉␉␉␉}␊ |
251 | ␊ |
252 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
253 | ␉␉␉␉␉␉{␊ |
254 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
255 | ␉␉␉␉␉␉␉return true;␊ |
256 | ␉␉␉␉␉␉}␊ |
257 | ␊ |
258 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
259 | ␉␉␉␉␉␉{␊ |
260 | ␉␉␉␉␉␉␉value->word = 0x601;␉␉␉// Core i5␊ |
261 | ␉␉␉␉␉␉␉return true;␊ |
262 | ␉␉␉␉␉␉}␊ |
263 | ␊ |
264 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
265 | ␉␉␉␉␉␉{␊ |
266 | ␉␉␉␉␉␉␉value->word = 0x701;␉␉␉// 1793 - Core i7␊ |
267 | ␉␉␉␉␉␉␉return true;␊ |
268 | ␉␉␉␉␉␉}␊ |
269 | ␊ |
270 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
271 | ␉␉␉␉␉␉{␊ |
272 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉␉// - Core i3␊ |
273 | ␉␉␉␉␉␉␉return true;␊ |
274 | ␉␉␉␉␉␉}␊ |
275 | ␊ |
276 | ␉␉␉␉␉␉return true;␊ |
277 | ␊ |
278 | ␉␉␉␉␉case CPUID_MODEL_DALES:␉␉␉␉// 0x25 - Intel Core i3, i5 LGA1156 (32nm) (Clarkdale, Arrandale)␊ |
279 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE:␉␉␉// 0x2C - Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊ |
280 | ␉␉␉␉␉case CPUID_MODEL_WESTMERE_EX:␉␉␉// 0x2F - Intel Xeon E7␊ |
281 | ␊ |
282 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
283 | ␉␉␉␉␉␉{␊ |
284 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
285 | ␉␉␉␉␉␉␉return true;␊ |
286 | ␉␉␉␉␉␉}␊ |
287 | ␊ |
288 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
289 | ␉␉␉␉␉␉{␊ |
290 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// 2305 - Core i3␊ |
291 | ␉␉␉␉␉␉␉return true;␊ |
292 | ␉␉␉␉␉␉}␊ |
293 | ␊ |
294 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
295 | ␉␉␉␉␉␉{␊ |
296 | ␉␉␉␉␉␉␉value->word = 0x602;␉␉// 1538 - Core i5␊ |
297 | ␉␉␉␉␉␉␉return true;␊ |
298 | ␉␉␉␉␉␉}␊ |
299 | ␊ |
300 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
301 | ␉␉␉␉␉␉{␊ |
302 | ␉␉␉␉␉␉␉value->word = 0x702;␉␉// 1794 -Core i7␊ |
303 | ␉␉␉␉␉␉␉return true;␊ |
304 | ␉␉␉␉␉␉}␊ |
305 | ␊ |
306 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
307 | ␉␉␉␉␉␉{␊ |
308 | ␉␉␉␉␉␉␉value->word = 0x901;␉␉// - Core i3␊ |
309 | ␉␉␉␉␉␉␉return true;␊ |
310 | ␉␉␉␉␉␉}␊ |
311 | ␊ |
312 | ␉␉␉␉␉␉return true;␊ |
313 | ␊ |
314 | ␉␉␉␉␉case CPUID_MODEL_JAKETOWN:␉␉␉// 0x2D - Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊ |
315 | ␉␉␉␉␉case CPUID_MODEL_SANDYBRIDGE:␉␉␉// 0x2A - Intel Core i3, i5, i7 LGA1155 (32nm)␊ |
316 | ␊ |
317 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
318 | ␉␉␉␉␉␉{␊ |
319 | ␉␉␉␉␉␉␉value->word = 0x501;␉␉// 1281 - Xeon␊ |
320 | ␉␉␉␉␉␉␉return true;␊ |
321 | ␉␉␉␉␉␉}␊ |
322 | ␊ |
323 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
324 | ␉␉␉␉␉␉{␊ |
325 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// 2306 -Core i3␊ |
326 | ␉␉␉␉␉␉␉return true;␊ |
327 | ␉␉␉␉␉␉}␊ |
328 | ␊ |
329 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
330 | ␉␉␉␉␉␉{␊ |
331 | ␉␉␉␉␉␉␉value->word = 0x603;␉␉// 1539 - Core i5␊ |
332 | ␉␉␉␉␉␉␉return true;␊ |
333 | ␉␉␉␉␉␉}␊ |
334 | ␊ |
335 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
336 | ␉␉␉␉␉␉{␊ |
337 | ␉␉␉␉␉␉␉value->word = 0x703;␉␉// 1795 - Core i7␊ |
338 | ␉␉␉␉␉␉␉return true;␊ |
339 | ␉␉␉␉␉␉}␊ |
340 | ␊ |
341 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
342 | ␉␉␉␉␉␉{␊ |
343 | ␉␉␉␉␉␉␉value->word = 0x902;␉␉// - Core i5␊ |
344 | ␉␉␉␉␉␉␉return true;␊ |
345 | ␉␉␉␉␉␉}␊ |
346 | ␊ |
347 | ␉␉␉␉␉␉return true;␊ |
348 | ␊ |
349 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE:␉␉␉// 0x3A - Intel Core i3, i5, i7 LGA1155 (22nm)␊ |
350 | ␊ |
351 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
352 | ␉␉␉␉␉␉{␊ |
353 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
354 | ␉␉␉␉␉␉␉return true;␊ |
355 | ␉␉␉␉␉␉}␊ |
356 | ␊ |
357 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
358 | ␉␉␉␉␉␉{␊ |
359 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// 2307 - Core i3 - Apple doesn't use it␊ |
360 | ␉␉␉␉␉␉␉return true;␊ |
361 | ␉␉␉␉␉␉}␊ |
362 | ␊ |
363 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
364 | ␉␉␉␉␉␉{␊ |
365 | ␉␉␉␉␉␉␉value->word = 0x604;␉␉// 1540 - Core i5␊ |
366 | ␉␉␉␉␉␉␉return true;␊ |
367 | ␉␉␉␉␉␉}␊ |
368 | ␊ |
369 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
370 | ␉␉␉␉␉␉{␊ |
371 | ␉␉␉␉␉␉␉value->word = 0x704;␉␉// 1796 - Core i7␊ |
372 | ␉␉␉␉␉␉␉return true;␊ |
373 | ␉␉␉␉␉␉}␊ |
374 | ␊ |
375 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
376 | ␉␉␉␉␉␉{␊ |
377 | ␉␉␉␉␉␉␉value->word = 0x903;␉␉// - Core i5␊ |
378 | ␉␉␉␉␉␉␉return true;␊ |
379 | ␉␉␉␉␉␉}␊ |
380 | ␊ |
381 | ␉␉␉␉␉␉return true;␊ |
382 | ␊ |
383 | ␉␉␉␉␉␉case CPUID_MODEL_HASWELL_U5:␉␉// 0x3D -␊ |
384 | ␊ |
385 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M))␊ |
386 | ␉␉␉␉␉␉{␊ |
387 | ␉␉␉␉␉␉␉value->word = 0xB06;␉␉// 2822␊ |
388 | ␉␉␉␉␉␉␉return true;␊ |
389 | ␉␉␉␉␉␉}␊ |
390 | ␊ |
391 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
392 | ␉␉␉␉␉␉{␊ |
393 | ␉␉␉␉␉␉␉value->word = 0x906;␉␉// 2310 - Apple doesn't use it␊ |
394 | ␉␉␉␉␉␉␉return true;␊ |
395 | ␉␉␉␉␉␉}␊ |
396 | ␊ |
397 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
398 | ␉␉␉␉␉␉{␊ |
399 | ␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊ |
400 | ␉␉␉␉␉␉␉return true;␊ |
401 | ␉␉␉␉␉␉}␊ |
402 | ␊ |
403 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
404 | ␉␉␉␉␉␉{␊ |
405 | ␉␉␉␉␉␉␉value->word = 0x706;␉␉// 1798␊ |
406 | ␉␉␉␉␉␉␉return true;␊ |
407 | ␉␉␉␉␉␉}␊ |
408 | ␊ |
409 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
410 | ␉␉␉␉␉␉{␊ |
411 | ␉␉␉␉␉␉␉value->word = 0x606;␉␉// 1542␊ |
412 | ␉␉␉␉␉␉␉return true;␊ |
413 | ␉␉␉␉␉␉}␊ |
414 | ␊ |
415 | //␉␉␉␉␉␉value->word = 0x706;␉␉␉// 1798␊ |
416 | ␉␉␉␉␉␉return true;␊ |
417 | ␊ |
418 | ␉␉␉␉␉case CPUID_MODEL_IVYBRIDGE_XEON:␉␉// 0x3E - Mac Pro 6,1␊ |
419 | ␊ |
420 | ␉␉␉␉␉␉value->word = 0xA01;␉␉␉// 2561 - Xeon␊ |
421 | ␉␉␉␉␉␉return true;␊ |
422 | ␊ |
423 | ␉␉␉␉␉case CPUID_MODEL_ATOM_3700:␉␉␉// 0x37␊ |
424 | ␉␉␉␉␉case CPUID_MODEL_HASWELL:␉␉␉// 0x3C␊ |
425 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_SVR:␉␉␉// 0x3F␊ |
426 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULT:␉␉␉// 0x45␊ |
427 | ␉␉␉␉␉case CPUID_MODEL_HASWELL_ULX:␉␉␉// 0x46␊ |
428 | ␉␉␉␉␉case CPUID_MODEL_BROADWELL_HQ:␉␉␉// 0x47␊ |
429 | ␉␉␉␉␉case CPUID_MODEL_SKYLAKE:␉␉␉// 0x4E␊ |
430 | ␉␉␉␉␉case CPUID_MODEL_SKYLAKE_AVX:␉␉␉// 0x55␊ |
431 | ␉␉␉␉␉case CPUID_MODEL_SKYLAKE_S:␉␉␉// 0x5E␊ |
432 | ␊ |
433 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, XEON))␊ |
434 | ␉␉␉␉␉␉{␊ |
435 | ␉␉␉␉␉␉␉value->word = 0xA01;␉␉// 2561 - Xeon␊ |
436 | ␉␉␉␉␉␉␉return true;␊ |
437 | ␉␉␉␉␉␉}␊ |
438 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I3))␊ |
439 | ␉␉␉␉␉␉{␊ |
440 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// 2308 - Core i3 - Apple doesn't use it - but we yes:-)␊ |
441 | ␉␉␉␉␉␉␉return true;␊ |
442 | ␉␉␉␉␉␉}␊ |
443 | ␊ |
444 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I5))␊ |
445 | ␉␉␉␉␉␉{␊ |
446 | ␉␉␉␉␉␉␉value->word = 0x605;␉␉// 1541 - Core i5␊ |
447 | ␉␉␉␉␉␉␉return true;␊ |
448 | ␉␉␉␉␉␉}␊ |
449 | ␊ |
450 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_I7))␊ |
451 | ␉␉␉␉␉␉{␊ |
452 | ␉␉␉␉␉␉␉value->word = 0x705;␉␉// 1797 - Core i7␊ |
453 | ␉␉␉␉␉␉␉return true;␊ |
454 | ␉␉␉␉␉␉}␊ |
455 | ␊ |
456 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M))␊ |
457 | ␉␉␉␉␉␉{␊ |
458 | ␉␉␉␉␉␉␉value->word = 0xB06;␉␉// 2822␊ |
459 | ␉␉␉␉␉␉␉return true;␊ |
460 | ␉␉␉␉␉␉}␊ |
461 | ␊ |
462 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M3))␊ |
463 | ␉␉␉␉␉␉{␊ |
464 | ␉␉␉␉␉␉␉value->word = 0xC05;␊ |
465 | ␉␉␉␉␉␉␉return true;␊ |
466 | ␉␉␉␉␉␉}␊ |
467 | ␊ |
468 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M5))␊ |
469 | ␉␉␉␉␉␉{␊ |
470 | ␉␉␉␉␉␉␉value->word = 0xD05;␊ |
471 | ␉␉␉␉␉␉␉return true;␊ |
472 | ␉␉␉␉␉␉}␊ |
473 | ␊ |
474 | ␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, CORE_M7))␊ |
475 | ␉␉␉␉␉␉{␊ |
476 | ␉␉␉␉␉␉␉value->word = 0xE05;␊ |
477 | ␉␉␉␉␉␉␉return true;␊ |
478 | ␉␉␉␉␉␉}␊ |
479 | ␊ |
480 | ␉␉␉␉␉␉if (Platform.CPU.NoCores <= 2)␊ |
481 | ␉␉␉␉␉␉{␊ |
482 | ␉␉␉␉␉␉␉value->word = 0x904;␉␉// - Core i3␊ |
483 | ␉␉␉␉␉␉␉return true;␊ |
484 | ␉␉␉␉␉␉}␊ |
485 | ␊ |
486 | ␉␉␉␉␉␉return true;␊ |
487 | ␊ |
488 | ␉␉␉␉␉case 0x15:␉␉␉␉␉// EP80579 integrated processor␊ |
489 | ␊ |
490 | ␉␉␉␉␉␉value->word = 0x301;␉␉␉// 769␊ |
491 | ␉␉␉␉␉␉return true;␊ |
492 | ␊ |
493 | ␉␉␉␉␉case 0x13:␉␉␉␉␉// Core i5, Xeon MP, "Havendale", "Auburndale", 45nm␊ |
494 | ␉␉␉␉␉case 0x19:␉␉␉␉␉// Intel Core i5 650 @3.20 Ghz␊ |
495 | ␊ |
496 | ␉␉␉␉␉␉value->word = 0x601;␉␉␉// 1537 - Core i5␊ |
497 | ␉␉␉␉␉␉return true;␊ |
498 | ␊ |
499 | ␉␉␉␉␉default:␊ |
500 | ␊ |
501 | ␉␉␉␉␉␉return true;␊ |
502 | ␉␉␉␉␉␉break; // Unsupported CPU type␊ |
503 | ␉␉␉␉}␊ |
504 | ␉␉␉␉break;␊ |
505 | ␊ |
506 | ␉␉␉default:␊ |
507 | ␉␉␉␉break;␊ |
508 | ␉␉}␊ |
509 | ␉}␊ |
510 | /*␊ |
511 | ␉if (Platform.CPU.Vendor == CPUID_VENDOR_AMD) // AMD␊ |
512 | ␉{␊ |
513 | ␉␉value->word = simpleGetSMBOemProcessorType();␊ |
514 | ␉␉return true;␊ |
515 | ␉}␊ |
516 | */␊ |
517 | ␉return false;␊ |
518 | }␊ |
519 | ␊ |
520 | bool getSMBMemoryDeviceMemoryType(returnType *value)␊ |
521 | {␊ |
522 | ␉static int idx = -1;␊ |
523 | ␉int␉map;␊ |
524 | ␊ |
525 | ␉idx++;␊ |
526 | ␉if (idx < MAX_RAM_SLOTS)␊ |
527 | ␉{␊ |
528 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
529 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Type != 0)␊ |
530 | ␉␉{␊ |
531 | ␉␉␉DBG("RAM Detected Type = %d\n", Platform.RAM.DIMM[map].Type);␊ |
532 | ␉␉␉value->byte = Platform.RAM.DIMM[map].Type;␊ |
533 | ␉␉␉return true;␊ |
534 | ␉␉}␊ |
535 | ␉}␊ |
536 | ␊ |
537 | ␉return false;␊ |
538 | //␉value->byte = SMB_MEM_TYPE_DDR2;␊ |
539 | //␉return true;␊ |
540 | }␊ |
541 | ␊ |
542 | bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊ |
543 | {␊ |
544 | ␉value->word = 0xFFFF;␊ |
545 | ␉return true;␊ |
546 | }␊ |
547 | ␊ |
548 | bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊ |
549 | {␊ |
550 | ␉static int idx = -1;␊ |
551 | ␉int␉map;␊ |
552 | ␊ |
553 | ␉idx++;␊ |
554 | ␉if (idx < MAX_RAM_SLOTS)␊ |
555 | ␉{␊ |
556 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
557 | ␉␉if (Platform.RAM.DIMM[map].InUse && Platform.RAM.DIMM[map].Frequency != 0)␊ |
558 | ␉␉{␊ |
559 | ␉␉␉DBG("RAM Detected Freq = %d Mhz\n", Platform.RAM.DIMM[map].Frequency);␊ |
560 | ␉␉␉value->dword = Platform.RAM.DIMM[map].Frequency;␊ |
561 | ␉␉␉return true;␊ |
562 | ␉␉}␊ |
563 | ␉}␊ |
564 | ␊ |
565 | ␉return false;␊ |
566 | //␉value->dword = 800;␊ |
567 | //␉return true;␊ |
568 | }␊ |
569 | ␊ |
570 | bool getSMBMemoryDeviceManufacturer(returnType *value)␊ |
571 | {␊ |
572 | ␉static int idx = -1;␊ |
573 | ␉int␉map;␊ |
574 | ␊ |
575 | ␉idx++;␊ |
576 | ␉if (idx < MAX_RAM_SLOTS)␊ |
577 | ␉{␊ |
578 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
579 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].Vendor) > 0)␊ |
580 | ␉␉{␊ |
581 | ␉␉␉DBG("RAM Detected Vendor[%d]='%s'\n", idx, Platform.RAM.DIMM[map].Vendor);␊ |
582 | ␉␉␉value->string = Platform.RAM.DIMM[map].Vendor;␊ |
583 | ␉␉␉return true;␊ |
584 | ␉␉}␊ |
585 | ␉}␊ |
586 | ␊ |
587 | ␉if (!bootInfo->memDetect)␊ |
588 | ␉{␊ |
589 | ␉␉return false;␊ |
590 | ␉}␊ |
591 | ␉value->string = NOT_AVAILABLE;␊ |
592 | ␉return true;␊ |
593 | }␊ |
594 | ␊ |
595 | bool getSMBMemoryDeviceSerialNumber(returnType *value)␊ |
596 | {␊ |
597 | ␉static int idx = -1;␊ |
598 | ␉int␉map;␊ |
599 | ␊ |
600 | ␉idx++;␊ |
601 | ␊ |
602 | ␉//DBG("getSMBMemoryDeviceSerialNumber index: %d, MAX_RAM_SLOTS: %d\n", idx, MAX_RAM_SLOTS);␊ |
603 | ␊ |
604 | ␉if (idx < MAX_RAM_SLOTS)␊ |
605 | ␉{␊ |
606 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
607 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].SerialNo) > 0)␊ |
608 | ␉␉{␊ |
609 | ␉␉␉DBG("map=%d, RAM Detected SerialNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].SerialNo);␊ |
610 | ␉␉␉value->string = Platform.RAM.DIMM[map].SerialNo;␊ |
611 | ␉␉␉return true;␊ |
612 | ␉␉}␊ |
613 | ␉}␊ |
614 | ␊ |
615 | ␉if (!bootInfo->memDetect)␊ |
616 | ␉{␊ |
617 | ␉␉return false;␊ |
618 | ␉}␊ |
619 | ␉value->string = NOT_AVAILABLE;␊ |
620 | ␉return true;␊ |
621 | }␊ |
622 | ␊ |
623 | bool getSMBMemoryDevicePartNumber(returnType *value)␊ |
624 | {␊ |
625 | ␉static int idx = -1;␊ |
626 | ␉int␉map;␊ |
627 | ␊ |
628 | ␉idx++;␊ |
629 | ␉if (idx < MAX_RAM_SLOTS)␊ |
630 | ␉{␊ |
631 | ␉␉map = Platform.DMI.DIMM[idx];␊ |
632 | ␉␉if (Platform.RAM.DIMM[map].InUse && strlen(Platform.RAM.DIMM[map].PartNo) > 0)␊ |
633 | ␉␉{␊ |
634 | ␉␉␉DBG("map=%d, RAM Detected PartNo[%d]='%s'\n", map, idx, Platform.RAM.DIMM[map].PartNo);␊ |
635 | ␉␉␉value->string = Platform.RAM.DIMM[map].PartNo;␊ |
636 | ␉␉␉return true;␊ |
637 | ␉␉}␊ |
638 | ␉}␊ |
639 | ␊ |
640 | ␉if (!bootInfo->memDetect)␊ |
641 | ␉{␊ |
642 | ␉␉return false;␊ |
643 | ␉}␊ |
644 | ␉value->string = NOT_AVAILABLE;␊ |
645 | ␉return true;␊ |
646 | }␊ |
647 | ␊ |
648 | // getting smbios addr with fast compare ops, late checksum testing ...␊ |
649 | #define COMPARE_DWORD(a,b) ( *((uint32_t *) a) == *((uint32_t *) b) )␊ |
650 | static const char *const SMTAG = "_SM_";␊ |
651 | //static const char *const SM3TAG = "_SM3_"; // smbios3_decode␊ |
652 | static const char *const DMITAG = "_DMI_";␊ |
653 | ␊ |
654 | SMBEntryPoint *getAddressOfSmbiosTable(void)␊ |
655 | {␊ |
656 | ␉SMBEntryPoint␉*smbios;␊ |
657 | ␉/*␊ |
658 | ␉ * The logic is to start at 0xf0000 and end at 0xfffff iterating 16 bytes at a time looking␊ |
659 | ␉ * for the SMBIOS entry-point structure anchor (literal ASCII "_SM_").␊ |
660 | ␉ */␊ |
661 | ␉smbios = (SMBEntryPoint*)SMBIOS_RANGE_START;␊ |
662 | ␉while (smbios <= (SMBEntryPoint *)SMBIOS_RANGE_END)␊ |
663 | ␉{␊ |
664 | ␉␉if (COMPARE_DWORD(smbios->anchor, SMTAG) &&␊ |
665 | ␉␉␉COMPARE_DWORD(smbios->dmi.anchor, DMITAG) &&␊ |
666 | ␉␉␉smbios->dmi.anchor[4] == DMITAG[4] &&␊ |
667 | ␉␉␉checksum8(smbios, sizeof(SMBEntryPoint)) == 0)␊ |
668 | ␉␉{␊ |
669 | ␉␉␉return smbios;␊ |
670 | ␉ }␊ |
671 | ␉␉smbios = (SMBEntryPoint*)(((char*)smbios) + 16);␊ |
672 | ␉}␊ |
673 | ␉printf("ERROR: Unable to find SMBIOS!\n");␊ |
674 | ␉pause();␊ |
675 | ␉return NULL;␊ |
676 | }␊ |
677 |