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| Source at commit 307 created 12 years 11 months ago. By ifabio, merge changes from trunk (929). Also merge the module changes from Azimutz branche (fix compile error) Also edited the info.plist into AHCIPortInjector.kext: http://forum.voodooprojects.org/index.php/topic,1170.0.html | |
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| 1 | /*␊ |
| 2 | * ␊ |
| 3 | */␊ |
| 4 | ␊ |
| 5 | #include "libsaio.h"␊ |
| 6 | #include "pci.h"␊ |
| 7 | #include "hpet.h"␊ |
| 8 | ␊ |
| 9 | #ifndef DEBUG_HPET␊ |
| 10 | #define DEBUG_HPET 0␊ |
| 11 | #endif␊ |
| 12 | ␊ |
| 13 | #if DEBUG_HPET␊ |
| 14 | #define DBG(x...) printf(x)␊ |
| 15 | #else␊ |
| 16 | #define DBG(x...)␊ |
| 17 | #endif␊ |
| 18 | ␊ |
| 19 | static struct lpc_controller_t lpc_controllers[] = {␊ |
| 20 | ␊ |
| 21 | ␉// Default unknown chipset␊ |
| 22 | ␉{ 0, 0, "" },␊ |
| 23 | ␊ |
| 24 | ␉// Intel␊ |
| 25 | ␉{ 0x8086, 0x24dc, "ICH5" },␊ |
| 26 | ␉{ 0x8086, 0x2640, "ICH6" },␊ |
| 27 | ␉{ 0x8086, 0x2641, "ICH6M" },␊ |
| 28 | ␊ |
| 29 | ␉{ 0x8086, 0x27b0, "ICH7 DH" },␊ |
| 30 | ␉{ 0x8086, 0x27b8, "ICH7" },␊ |
| 31 | ␉{ 0x8086, 0x27b9, "ICH7M" },␊ |
| 32 | ␉{ 0x8086, 0x27bd, "ICH7M DH" },␊ |
| 33 | ␊ |
| 34 | ␉{ 0x8086, 0x27bc, "NM10" },␊ |
| 35 | ␊ |
| 36 | ␉{ 0x8086, 0x2810, "ICH8R" },␊ |
| 37 | ␉{ 0x8086, 0x2811, "ICH8M-E" },␊ |
| 38 | ␉{ 0x8086, 0x2812, "ICH8DH" },␊ |
| 39 | ␉{ 0x8086, 0x2814, "ICH8DO" },␊ |
| 40 | ␉{ 0x8086, 0x2815, "ICH8M" },␊ |
| 41 | ␊ |
| 42 | ␉{ 0x8086, 0x2912, "ICH9DH" },␊ |
| 43 | ␉{ 0x8086, 0x2914, "ICH9DO" },␊ |
| 44 | ␉{ 0x8086, 0x2916, "ICH9R" },␊ |
| 45 | ␉{ 0x8086, 0x2917, "ICH9M-E" },␊ |
| 46 | ␉{ 0x8086, 0x2918, "ICH9" },␊ |
| 47 | ␉{ 0x8086, 0x2919, "ICH9M" },␊ |
| 48 | ␊ |
| 49 | ␉{ 0x8086, 0x3a14, "ICH10DO" },␊ |
| 50 | ␉{ 0x8086, 0x3a16, "ICH10R" },␊ |
| 51 | ␉{ 0x8086, 0x3a18, "ICH10" },␊ |
| 52 | ␉{ 0x8086, 0x3a1a, "ICH10D" },␊ |
| 53 | ␊ |
| 54 | };␊ |
| 55 | ␊ |
| 56 | void force_enable_hpet(pci_dt_t *lpc_dev)␊ |
| 57 | {␊ |
| 58 | ␉int i;␊ |
| 59 | ␉uint32_t␉val, hpet_address = 0xFED00000;␊ |
| 60 | ␉void␉␉*rcba;␊ |
| 61 | ␊ |
| 62 | ␉/* LPC on Intel ICH is always (?) at 00:1f.0 */␊ |
| 63 | ␉for(i = 1; i < sizeof(lpc_controllers) / sizeof(lpc_controllers[0]); i++)␊ |
| 64 | ␉␉if ((lpc_controllers[i].vendor == lpc_dev->vendor_id) ␊ |
| 65 | ␉␉␉&& (lpc_controllers[i].device == lpc_dev->device_id))␊ |
| 66 | ␉␉{␊ |
| 67 | ␉␉␉rcba = (void *)(pci_config_read32(lpc_dev->dev.addr, 0xF0) & 0xFFFFC000);␊ |
| 68 | ␊ |
| 69 | ␉␉␉DBG("Intel(R) %s LPC Interface [%04x:%04x], MMIO @ 0x%lx\n", ␊ |
| 70 | ␉␉␉␉lpc_controllers[i].name, lpc_dev->vendor_id, lpc_dev->device_id, rcba);␊ |
| 71 | ␊ |
| 72 | ␉␉␉if (rcba == 0)␊ |
| 73 | ␉␉␉␉printf(" RCBA disabled; cannot force enable HPET\n");␊ |
| 74 | ␉␉␉else␊ |
| 75 | ␉␉␉{␊ |
| 76 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 77 | ␉␉␉␉if (val & 0x80)␊ |
| 78 | ␉␉␉␉{␊ |
| 79 | ␉␉␉␉␉// HPET is enabled in HPTC. Just not reported by BIOS␊ |
| 80 | ␉␉␉␉␉DBG(" HPET is enabled in HPTC, just not reported by BIOS\n");␊ |
| 81 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 82 | ␉␉␉␉␉DBG(" HPET MMIO @ 0x%lx\n", hpet_address);␊ |
| 83 | ␉␉␉␉}␊ |
| 84 | ␉␉␉␉else␊ |
| 85 | ␉␉␉␉{␊ |
| 86 | ␉␉␉␉␉// HPET disabled in HPTC. Trying to enable␊ |
| 87 | ␉␉␉␉␉DBG(" HPET is disabled in HPTC, trying to enable\n");␉␉␉␉␉␉␉␉␉␊ |
| 88 | ␉␉␉␉␉REG32(rcba, 0x3404) = val | 0x80;␊ |
| 89 | ␉␉␉␉␉hpet_address |= (val & 3) << 12 ;␊ |
| 90 | ␉␉␉␉␉DBG(" Force enabled HPET, MMIO @ 0x%lx\n", hpet_address);␊ |
| 91 | ␉␉␉␉}␊ |
| 92 | ␊ |
| 93 | ␉␉␉␉// verify if the job is done␊ |
| 94 | ␉␉␉␉val = REG32(rcba, 0x3404);␊ |
| 95 | ␉␉␉␉if (!(val & 0x80))␊ |
| 96 | ␉␉␉␉␉printf(" Failed to force enable HPET\n");␊ |
| 97 | ␉␉␉}␊ |
| 98 | ␉␉␉break;␊ |
| 99 | ␉␉}␊ |
| 100 | ␊ |
| 101 | #if DEBUG_HPET␊ |
| 102 | ␉printf("Press [Enter] to continue...\n");␊ |
| 103 | ␉getc();␊ |
| 104 | #endif␊ |
| 105 | }␊ |
| 106 | |
