| 1 | #ifndef SD_H␊ |
| 2 | #define SD_H␊ |
| 3 | ␊ |
| 4 | #include "License.h"␊ |
| 5 | #include "SD_Misc.h"␊ |
| 6 | ␊ |
| 7 | /* SD commands type argument response */␊ |
| 8 | /* class 0 */␊ |
| 9 | /* This is basically the same command as for MMC with some quirks. */␊ |
| 10 | #define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */␊ |
| 11 | #define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */␊ |
| 12 | ␊ |
| 13 | /* class 10 */␊ |
| 14 | #define SD_SWITCH 6 /* adtc [31:0] See below R1 */␊ |
| 15 | ␊ |
| 16 | /* Application commands */␊ |
| 17 | #define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */␊ |
| 18 | #define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */␊ |
| 19 | #define SD_APP_SET_WR_BLK_ERASE_COUNT 23␉/*␉␉ R1 */␊ |
| 20 | #define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */␊ |
| 21 | #define SD_APP_SEND_SCR 51 /* adtc R1 */␊ |
| 22 | ␊ |
| 23 | /* Standard MMC commands (4.1) type argument response */␊ |
| 24 | /* class 1 */␊ |
| 25 | #define SD_GO_IDLE_STATE 0 /* bc */␊ |
| 26 | #define SD_SEND_OP_COND 1 /* bcr [31:0] OCR R3 */␊ |
| 27 | #define SD_ALL_SEND_CID 2 /* bcr R2 */␊ |
| 28 | #define SD_SET_RELATIVE_ADDR 3 /* ac [31:16] RCA R1 */␊ |
| 29 | #define SD_SET_DSR 4 /* bc [31:16] RCA */␊ |
| 30 | #define SD_SWITCH 6 /* ac [31:0] See below R1b */␊ |
| 31 | #define SD_SELECT_CARD 7 /* ac [31:16] RCA R1 */␊ |
| 32 | #define SD_SEND_EXT_CSD 8 /* adtc R1 */␊ |
| 33 | #define SD_SEND_CSD 9 /* ac [31:16] RCA R2 */␊ |
| 34 | #define SD_SEND_CID 10 /* ac [31:16] RCA R2 */␊ |
| 35 | #define SD_READ_DAT_UNTIL_STOP 11 /* adtc [31:0] dadr R1 */␊ |
| 36 | #define SD_STOP_TRANSMISSION 12 /* ac R1b */␊ |
| 37 | #define SD_SEND_STATUS 13 /* ac [31:16] RCA R1 */␊ |
| 38 | #define SD_GO_INACTIVE_STATE 15 /* ac [31:16] RCA */␊ |
| 39 | #define SD_SPI_READ_OCR 58 /* spi spi_R3 */␊ |
| 40 | #define SD_SPI_CRC_ON_OFF 59 /* spi [0:0] flag spi_R1 */␊ |
| 41 | ␊ |
| 42 | /* class 2 */␊ |
| 43 | #define SD_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */␊ |
| 44 | #define SD_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */␊ |
| 45 | #define SD_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */␊ |
| 46 | ␊ |
| 47 | /* class 3 */␊ |
| 48 | #define SD_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */␊ |
| 49 | ␊ |
| 50 | /* class 4 */␊ |
| 51 | #define SD_SET_BLOCK_COUNT 23 /* adtc [31:0] data addr R1 */␊ |
| 52 | #define SD_WRITE_BLOCK 24 /* adtc [31:0] data addr R1 */␊ |
| 53 | #define SD_WRITE_MULTIPLE_BLOCK 25 /* adtc R1 */␊ |
| 54 | #define SD_PROGRAM_CID 26 /* adtc R1 */␊ |
| 55 | #define SD_PROGRAM_CSD 27 /* adtc R1 */␊ |
| 56 | ␊ |
| 57 | /* class 6 */␊ |
| 58 | #define SD_SET_WRITE_PROT 28 /* ac [31:0] data addr R1b */␊ |
| 59 | #define SD_CLR_WRITE_PROT 29 /* ac [31:0] data addr R1b */␊ |
| 60 | #define SD_SEND_WRITE_PROT 30 /* adtc [31:0] wpdata addr R1 */␊ |
| 61 | ␊ |
| 62 | /* class 5 */␊ |
| 63 | #define SD_ERASE_GROUP_START 35 /* ac [31:0] data addr R1 */␊ |
| 64 | #define SD_ERASE_GROUP_END 36 /* ac [31:0] data addr R1 */␊ |
| 65 | #define SD_ERASE 38 /* ac R1b */␊ |
| 66 | ␊ |
| 67 | /* class 9 */␊ |
| 68 | #define SD_FAST_IO 39 /* ac <Complex> R4 */␊ |
| 69 | #define SD_GO_IRQ_STATE 40 /* bcr R5 */␊ |
| 70 | ␊ |
| 71 | /* class 7 */␊ |
| 72 | #define SD_LOCK_UNLOCK 42 /* adtc R1b */␊ |
| 73 | ␊ |
| 74 | /* class 8 */␊ |
| 75 | #define SD_APP_CMD 55 /* ac [31:16] RCA R1 */␊ |
| 76 | #define SD_GEN_CMD 56 /* adtc [0] RD/WR R1 */␊ |
| 77 | ␊ |
| 78 | /*␊ |
| 79 | * MMC_SWITCH argument format:␊ |
| 80 | *␊ |
| 81 | *␉[31:26] Always 0␊ |
| 82 | *␉[25:24] Access Mode␊ |
| 83 | *␉[23:16] Location of target Byte in EXT_CSD␊ |
| 84 | *␉[15:08] Value Byte␊ |
| 85 | *␉[07:03] Always 0␊ |
| 86 | *␉[02:00] Command Set␊ |
| 87 | */␊ |
| 88 | ␊ |
| 89 | /*␊ |
| 90 | MMC status in R1, for native mode (SPI bits are different)␊ |
| 91 | Type␊ |
| 92 | ␉e : error bit␊ |
| 93 | ␉s : status bit␊ |
| 94 | ␉r : detected and set for the actual command response␊ |
| 95 | ␉x : detected and set during command execution. the host must poll␊ |
| 96 | the card by sending status command in order to read these bits.␊ |
| 97 | Clear condition␊ |
| 98 | ␉a : according to the card state␊ |
| 99 | ␉b : always related to the previous command. Reception of␊ |
| 100 | a valid command will clear it (with a delay of one command)␊ |
| 101 | ␉c : clear by read␊ |
| 102 | */␊ |
| 103 | ␊ |
| 104 | #define R1_OUT_OF_RANGE␉␉(1 << 31)␉/* er, c */␊ |
| 105 | #define R1_ADDRESS_ERROR␉(1 << 30)␉/* erx, c */␊ |
| 106 | #define R1_BLOCK_LEN_ERROR␉(1 << 29)␉/* er, c */␊ |
| 107 | #define R1_ERASE_SEQ_ERROR (1 << 28)␉/* er, c */␊ |
| 108 | #define R1_ERASE_PARAM␉␉(1 << 27)␉/* ex, c */␊ |
| 109 | #define R1_WP_VIOLATION␉␉(1 << 26)␉/* erx, c */␊ |
| 110 | #define R1_CARD_IS_LOCKED␉(1 << 25)␉/* sx, a */␊ |
| 111 | #define R1_LOCK_UNLOCK_FAILED␉(1 << 24)␉/* erx, c */␊ |
| 112 | #define R1_COM_CRC_ERROR␉(1 << 23)␉/* er, b */␊ |
| 113 | #define R1_ILLEGAL_COMMAND␉(1 << 22)␉/* er, b */␊ |
| 114 | #define R1_CARD_ECC_FAILED␉(1 << 21)␉/* ex, c */␊ |
| 115 | #define R1_CC_ERROR␉␉(1 << 20)␉/* erx, c */␊ |
| 116 | #define R1_ERROR␉␉(1 << 19)␉/* erx, c */␊ |
| 117 | #define R1_UNDERRUN␉␉(1 << 18)␉/* ex, c */␊ |
| 118 | #define R1_OVERRUN␉␉(1 << 17)␉/* ex, c */␊ |
| 119 | #define R1_CID_CSD_OVERWRITE␉(1 << 16)␉/* erx, c, CID/CSD overwrite */␊ |
| 120 | #define R1_WP_ERASE_SKIP␉(1 << 15)␉/* sx, c */␊ |
| 121 | #define R1_CARD_ECC_DISABLED␉(1 << 14)␉/* sx, a */␊ |
| 122 | #define R1_ERASE_RESET␉␉(1 << 13)␉/* sr, c */␊ |
| 123 | #define R1_STATUS(x) (x & 0xFFFFE000)␊ |
| 124 | #define R1_CURRENT_STATE(x)␉((x & 0x00001E00) >> 9)␉/* sx, b (4 bits) */␊ |
| 125 | #define R1_READY_FOR_DATA␉(1 << 8)␉/* sx, a */␊ |
| 126 | #define R1_APP_CMD␉␉(1 << 5)␉/* sr, c */␊ |
| 127 | ␊ |
| 128 | /*␊ |
| 129 | * MMC/SD in SPI mode reports R1 status always, and R2 for SEND_STATUS␊ |
| 130 | * R1 is the low order byte; R2 is the next highest byte, when present.␊ |
| 131 | */␊ |
| 132 | #define R1_SPI_IDLE␉␉(1 << 0)␊ |
| 133 | #define R1_SPI_ERASE_RESET␉(1 << 1)␊ |
| 134 | #define R1_SPI_ILLEGAL_COMMAND␉(1 << 2)␊ |
| 135 | #define R1_SPI_COM_CRC␉␉(1 << 3)␊ |
| 136 | #define R1_SPI_ERASE_SEQ␉(1 << 4)␊ |
| 137 | #define R1_SPI_ADDRESS␉␉(1 << 5)␊ |
| 138 | #define R1_SPI_PARAMETER␉(1 << 6)␊ |
| 139 | /* R1 bit 7 is always zero */␊ |
| 140 | #define R2_SPI_CARD_LOCKED␉(1 << 8)␊ |
| 141 | #define R2_SPI_WP_ERASE_SKIP␉(1 << 9)␉/* or lock/unlock fail */␊ |
| 142 | #define R2_SPI_LOCK_UNLOCK_FAIL␉R2_SPI_WP_ERASE_SKIP␊ |
| 143 | #define R2_SPI_ERROR␉␉(1 << 10)␊ |
| 144 | #define R2_SPI_CC_ERROR␉␉(1 << 11)␊ |
| 145 | #define R2_SPI_CARD_ECC_ERROR␉(1 << 12)␊ |
| 146 | #define R2_SPI_WP_VIOLATION␉(1 << 13)␊ |
| 147 | #define R2_SPI_ERASE_PARAM␉(1 << 14)␊ |
| 148 | #define R2_SPI_OUT_OF_RANGE␉(1 << 15)␉/* or CSD overwrite */␊ |
| 149 | #define R2_SPI_CSD_OVERWRITE␉R2_SPI_OUT_OF_RANGE␊ |
| 150 | ␊ |
| 151 | /* These are unpacked versions of the actual responses */␊ |
| 152 | ␊ |
| 153 | struct _mmc_csd {␊ |
| 154 | ␉UInt8 csd_structure;␊ |
| 155 | ␉UInt8 spec_vers;␊ |
| 156 | ␉UInt8 taac;␊ |
| 157 | ␉UInt8 nsac;␊ |
| 158 | ␉UInt8 tran_speed;␊ |
| 159 | ␉UInt16 ccc;␊ |
| 160 | ␉UInt8 read_bl_len;␊ |
| 161 | ␉UInt8 read_bl_partial;␊ |
| 162 | ␉UInt8 write_blk_misalign;␊ |
| 163 | ␉UInt8 read_blk_misalign;␊ |
| 164 | ␉UInt8 dsr_imp;␊ |
| 165 | ␉UInt16 c_size;␊ |
| 166 | ␉UInt8 vdd_r_curr_min;␊ |
| 167 | ␉UInt8 vdd_r_curr_max;␊ |
| 168 | ␉UInt8 vdd_w_curr_min;␊ |
| 169 | ␉UInt8 vdd_w_curr_max;␊ |
| 170 | ␉UInt8 c_size_mult;␊ |
| 171 | ␉union {␊ |
| 172 | ␉␉struct { /* MMC system specification version 3.1 */␊ |
| 173 | ␉␉␉UInt8 erase_grp_size;␊ |
| 174 | ␉␉␉UInt8 erase_grp_mult;␊ |
| 175 | ␉␉} v31;␊ |
| 176 | ␉␉struct { /* MMC system specification version 2.2 */␊ |
| 177 | ␉␉␉UInt8 sector_size;␊ |
| 178 | ␉␉␉UInt8 erase_grp_size;␊ |
| 179 | ␉␉} v22;␊ |
| 180 | ␉} erase;␊ |
| 181 | ␉UInt8 wp_grp_size;␊ |
| 182 | ␉UInt8 wp_grp_enable;␊ |
| 183 | ␉UInt8 default_ecc;␊ |
| 184 | ␉UInt8 r2w_factor;␊ |
| 185 | ␉UInt8 write_bl_len;␊ |
| 186 | ␉UInt8 write_bl_partial;␊ |
| 187 | ␉UInt8 file_format_grp;␊ |
| 188 | ␉UInt8 copy;␊ |
| 189 | ␉UInt8 perm_write_protect;␊ |
| 190 | ␉UInt8 tmp_write_protect;␊ |
| 191 | ␉UInt8 file_format;␊ |
| 192 | ␉UInt8 ecc;␊ |
| 193 | };␊ |
| 194 | ␊ |
| 195 | /*␊ |
| 196 | * OCR bits are mostly in host.h␊ |
| 197 | */␊ |
| 198 | #define MMC_CARD_BUSY␉0x80000000␉/* Card Power up status bit */␊ |
| 199 | ␊ |
| 200 | /*␊ |
| 201 | * Card Command Classes (CCC)␊ |
| 202 | */␊ |
| 203 | #define CCC_BASIC␉␉(1<<0)␉/* (0) Basic protocol functions */␊ |
| 204 | ␉␉␉␉␉/* (CMD0,1,2,3,4,7,9,10,12,13,15) */␊ |
| 205 | ␉␉␉␉␉/* (and for SPI, CMD58,59) */␊ |
| 206 | #define CCC_STREAM_READ␉␉(1<<1)␉/* (1) Stream read commands */␊ |
| 207 | ␉␉␉␉␉/* (CMD11) */␊ |
| 208 | #define CCC_BLOCK_READ␉␉(1<<2)␉/* (2) Block read commands */␊ |
| 209 | ␉␉␉␉␉/* (CMD16,17,18) */␊ |
| 210 | #define CCC_STREAM_WRITE␉(1<<3)␉/* (3) Stream write commands */␊ |
| 211 | ␉␉␉␉␉/* (CMD20) */␊ |
| 212 | #define CCC_BLOCK_WRITE␉␉(1<<4)␉/* (4) Block write commands */␊ |
| 213 | ␉␉␉␉␉/* (CMD16,24,25,26,27) */␊ |
| 214 | #define CCC_ERASE␉␉(1<<5)␉/* (5) Ability to erase blocks */␊ |
| 215 | ␉␉␉␉␉/* (CMD32,33,34,35,36,37,38,39) */␊ |
| 216 | #define CCC_WRITE_PROT␉␉(1<<6)␉/* (6) Able to write protect blocks */␊ |
| 217 | ␉␉␉␉␉/* (CMD28,29,30) */␊ |
| 218 | #define CCC_LOCK_CARD␉␉(1<<7)␉/* (7) Able to lock down card */␊ |
| 219 | ␉␉␉␉␉/* (CMD16,CMD42) */␊ |
| 220 | #define CCC_APP_SPEC␉␉(1<<8)␉/* (8) Application specific */␊ |
| 221 | ␉␉␉␉␉/* (CMD55,56,57,ACMD*) */␊ |
| 222 | #define CCC_IO_MODE␉␉(1<<9)␉/* (9) I/O mode */␊ |
| 223 | ␉␉␉␉␉/* (CMD5,39,40,52,53) */␊ |
| 224 | #define CCC_SWITCH␉␉(1<<10)␉/* (10) High speed switch */␊ |
| 225 | ␉␉␉␉␉/* (CMD6,34,35,36,37,50) */␊ |
| 226 | ␉␉␉␉␉/* (11) Reserved */␊ |
| 227 | ␉␉␉␉␉/* (CMD?) */␊ |
| 228 | ␊ |
| 229 | /*␊ |
| 230 | * CSD field definitions␊ |
| 231 | */␊ |
| 232 | ␊ |
| 233 | #define CSD_STRUCT_VER_1_0 0 /* Valid for system specification 1.0 - 1.2 */␊ |
| 234 | #define CSD_STRUCT_VER_1_1 1 /* Valid for system specification 1.4 - 2.2 */␊ |
| 235 | #define CSD_STRUCT_VER_1_2 2 /* Valid for system specification 3.1 - 3.2 - 3.31 - 4.0 - 4.1 */␊ |
| 236 | #define CSD_STRUCT_EXT_CSD 3 /* Version is coded in CSD_STRUCTURE in EXT_CSD */␊ |
| 237 | ␊ |
| 238 | #define CSD_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.2 */␊ |
| 239 | #define CSD_SPEC_VER_1 1 /* Implements system specification 1.4 */␊ |
| 240 | #define CSD_SPEC_VER_2 2 /* Implements system specification 2.0 - 2.2 */␊ |
| 241 | #define CSD_SPEC_VER_3 3 /* Implements system specification 3.1 - 3.2 - 3.31 */␊ |
| 242 | #define CSD_SPEC_VER_4 4 /* Implements system specification 4.0 - 4.1 */␊ |
| 243 | ␊ |
| 244 | /*␊ |
| 245 | * EXT_CSD fields␊ |
| 246 | */␊ |
| 247 | ␊ |
| 248 | #define EXT_CSD_BUS_WIDTH␉183␉/* R/W */␊ |
| 249 | #define EXT_CSD_HS_TIMING␉185␉/* R/W */␊ |
| 250 | #define EXT_CSD_CARD_TYPE␉196␉/* RO */␊ |
| 251 | #define EXT_CSD_REV␉␉192␉/* RO */␊ |
| 252 | #define EXT_CSD_SEC_CNT␉␉212␉/* RO, 4 bytes */␊ |
| 253 | ␊ |
| 254 | /*␊ |
| 255 | * EXT_CSD field definitions␊ |
| 256 | */␊ |
| 257 | ␊ |
| 258 | #define EXT_CSD_CMD_SET_NORMAL␉␉(1<<0)␊ |
| 259 | #define EXT_CSD_CMD_SET_SECURE␉␉(1<<1)␊ |
| 260 | #define EXT_CSD_CMD_SET_CPSECURE␉(1<<2)␊ |
| 261 | ␊ |
| 262 | #define EXT_CSD_CARD_TYPE_26␉(1<<0)␉/* Card can run at 26MHz */␊ |
| 263 | #define EXT_CSD_CARD_TYPE_52␉(1<<1)␉/* Card can run at 52MHz */␊ |
| 264 | ␊ |
| 265 | #define EXT_CSD_BUS_WIDTH_1␉0␉/* Card is in 1 bit mode */␊ |
| 266 | #define EXT_CSD_BUS_WIDTH_4␉1␉/* Card is in 4 bit mode */␊ |
| 267 | #define EXT_CSD_BUS_WIDTH_8␉2␉/* Card is in 8 bit mode */␊ |
| 268 | ␊ |
| 269 | /*␊ |
| 270 | * MMC_SWITCH access modes␊ |
| 271 | */␊ |
| 272 | ␊ |
| 273 | #define MMC_SWITCH_MODE_CMD_SET␉␉0x00␉/* Change the command set */␊ |
| 274 | #define MMC_SWITCH_MODE_SET_BITS␉0x01␉/* Set bits which are 1 in value */␊ |
| 275 | #define MMC_SWITCH_MODE_CLEAR_BITS␉0x02␉/* Clear bits which are 1 in value */␊ |
| 276 | #define MMC_SWITCH_MODE_WRITE_BYTE␉0x03␉/* Set target to value */␊ |
| 277 | ␊ |
| 278 | /*␊ |
| 279 | * SD_SWITCH argument format:␊ |
| 280 | *␊ |
| 281 | * [31] Check (0) or switch (1)␊ |
| 282 | * [30:24] Reserved (0)␊ |
| 283 | * [23:20] Function group 6␊ |
| 284 | * [19:16] Function group 5␊ |
| 285 | * [15:12] Function group 4␊ |
| 286 | * [11:8] Function group 3␊ |
| 287 | * [7:4] Function group 2␊ |
| 288 | * [3:0] Function group 1␊ |
| 289 | */␊ |
| 290 | ␊ |
| 291 | /*␊ |
| 292 | * SD_SEND_IF_COND argument format:␊ |
| 293 | *␊ |
| 294 | *␉[31:12] Reserved (0)␊ |
| 295 | *␉[11:8] Host Voltage Supply Flags␊ |
| 296 | *␉[7:0] Check Pattern (0xAA)␊ |
| 297 | */␊ |
| 298 | ␊ |
| 299 | /*␊ |
| 300 | * SCR field definitions␊ |
| 301 | */␊ |
| 302 | ␊ |
| 303 | #define SCR_SPEC_VER_0␉␉0␉/* Implements system specification 1.0 - 1.01 */␊ |
| 304 | #define SCR_SPEC_VER_1␉␉1␉/* Implements system specification 1.10 */␊ |
| 305 | #define SCR_SPEC_VER_2␉␉2␉/* Implements system specification 2.00 */␊ |
| 306 | ␊ |
| 307 | /*␊ |
| 308 | * SD bus widths␊ |
| 309 | */␊ |
| 310 | #define SD_BUS_WIDTH_1␉␉0␊ |
| 311 | #define SD_BUS_WIDTH_4␉␉2␊ |
| 312 | ␊ |
| 313 | /*␊ |
| 314 | * SD_SWITCH mode␊ |
| 315 | */␊ |
| 316 | #define SD_SWITCH_CHECK␉␉0␊ |
| 317 | #define SD_SWITCH_SET␉␉1␊ |
| 318 | ␊ |
| 319 | /*␊ |
| 320 | * SD_SWITCH function groups␊ |
| 321 | */␊ |
| 322 | #define SD_SWITCH_GRP_ACCESS␉0␊ |
| 323 | ␊ |
| 324 | /*␊ |
| 325 | * SD_SWITCH access modes␊ |
| 326 | */␊ |
| 327 | #define SD_SWITCH_ACCESS_DEF␉0␊ |
| 328 | #define SD_SWITCH_ACCESS_HS␉1␊ |
| 329 | ␊ |
| 330 | /**********************************/␊ |
| 331 | /* From original SDHCI OSX driver */␊ |
| 332 | /**********************************/␊ |
| 333 | #define R0␉0␊ |
| 334 | #define R1␉1␊ |
| 335 | #define R1b␉2␊ |
| 336 | #define R2␉3␊ |
| 337 | #define R3␉4␊ |
| 338 | #define R4␉5␊ |
| 339 | #define R5␉6␊ |
| 340 | #define R5b 7␊ |
| 341 | #define R6␉8␊ |
| 342 | #define R7␉9␊ |
| 343 | ␊ |
| 344 | #define SDCR0␉R0␊ |
| 345 | #define SDCR1␉R0␊ |
| 346 | #define SDCR2␉R2␊ |
| 347 | #define SDCR3␉R6␊ |
| 348 | #define SDCR4␉R0␊ |
| 349 | #define SDCR5␉R0␊ |
| 350 | #define SDCR6␉R1␊ |
| 351 | #define SDCR7␉R1b␊ |
| 352 | #define SDCR8␉R7␊ |
| 353 | #define SDCR9␉R2␊ |
| 354 | #define SDCR10␉R2␊ |
| 355 | #define SDCR11␉R0␊ |
| 356 | #define SDCR12␉R1b␊ |
| 357 | #define SDCR13␉R1␊ |
| 358 | #define SDCR14␉R0␊ |
| 359 | #define SDCR15␉R0␊ |
| 360 | #define SDCR16␉R1␊ |
| 361 | #define SDCR17␉R1␊ |
| 362 | #define SDCR18␉R1␊ |
| 363 | #define SDCR19␉R0␊ |
| 364 | #define SDCR20␉R0␊ |
| 365 | #define SDCR21␉R0␊ |
| 366 | #define SDCR22␉R0␊ |
| 367 | #define SDCR23␉R0␊ |
| 368 | #define SDCR24␉R1␊ |
| 369 | #define SDCR25␉R1␊ |
| 370 | #define SDCR26␉R0␊ |
| 371 | #define SDCR27␉R1␊ |
| 372 | #define SDCR28␉R1b␊ |
| 373 | #define SDCR29␉R1b␊ |
| 374 | #define SDCR30␉R1␊ |
| 375 | #define SDCR31␉R0␊ |
| 376 | #define SDCR32␉R1␊ |
| 377 | #define SDCR33␉R1␊ |
| 378 | #define SDCR34␉R0␊ |
| 379 | #define SDCR35␉R0␊ |
| 380 | #define SDCR36␉R0␊ |
| 381 | #define SDCR37␉R0␊ |
| 382 | #define SDCR38␉R1b␊ |
| 383 | #define SDCR39␉R0␊ |
| 384 | #define SDCR40␉R0␊ |
| 385 | #define SDCR41␉R0␊ |
| 386 | #define SDCR42␉R1␊ |
| 387 | #define SDCR43␉R0␊ |
| 388 | #define SDCR44␉R0␊ |
| 389 | #define SDCR45␉R0␊ |
| 390 | #define SDCR46␉R0␊ |
| 391 | #define SDCR47␉R0␊ |
| 392 | #define SDCR48␉R0␊ |
| 393 | #define SDCR49␉R0␊ |
| 394 | #define SDCR50␉R0␊ |
| 395 | #define SDCR51␉R0␊ |
| 396 | #define SDCR52␉R0␊ |
| 397 | #define SDCR53␉R0␊ |
| 398 | #define SDCR54␉R0␊ |
| 399 | #define SDCR55␉R1␊ |
| 400 | #define SDCR56␉R1␊ |
| 401 | #define SDCR57␉R0␊ |
| 402 | #define SDCR58␉R0␊ |
| 403 | #define SDCR59␉R0␊ |
| 404 | #define SDCR60␉R0␊ |
| 405 | #define SDCR61␉R0␊ |
| 406 | #define SDCR62␉R0␊ |
| 407 | #define SDCR63␉R0␊ |
| 408 | ␊ |
| 409 | #define SDACR0␉R0␊ |
| 410 | #define SDACR1␉R0␊ |
| 411 | #define SDACR2␉R0␊ |
| 412 | #define SDACR3␉R0␊ |
| 413 | #define SDACR4␉R0␊ |
| 414 | #define SDACR5␉R0␊ |
| 415 | #define SDACR6␉R1␊ |
| 416 | #define SDACR7␉R0␊ |
| 417 | #define SDACR8␉R0␊ |
| 418 | #define SDACR9␉R0␊ |
| 419 | #define SDACR10␉R0␊ |
| 420 | #define SDACR11␉R0␊ |
| 421 | #define SDACR12␉R0␊ |
| 422 | #define SDACR13␉R1␊ |
| 423 | #define SDACR14␉R0␊ |
| 424 | #define SDACR15␉R0␊ |
| 425 | #define SDACR16␉R0␊ |
| 426 | #define SDACR17␉R0␊ |
| 427 | #define SDACR18␉R0␊ |
| 428 | #define SDACR19␉R0␊ |
| 429 | #define SDACR20␉R0␊ |
| 430 | #define SDACR21␉R1␊ |
| 431 | #define SDACR22␉R1␊ |
| 432 | #define SDACR23␉R0␊ |
| 433 | #define SDACR24␉R0␊ |
| 434 | #define SDACR25␉R0␊ |
| 435 | #define SDACR26␉R0␊ |
| 436 | #define SDACR27␉R0␊ |
| 437 | #define SDACR28␉R0␊ |
| 438 | #define SDACR29␉R0␊ |
| 439 | #define SDACR30␉R0␊ |
| 440 | #define SDACR31␉R0␊ |
| 441 | #define SDACR32␉R0␊ |
| 442 | #define SDACR33␉R0␊ |
| 443 | #define SDACR34␉R0␊ |
| 444 | #define SDACR35␉R0␊ |
| 445 | #define SDACR36␉R0␊ |
| 446 | #define SDACR37␉R0␊ |
| 447 | #define SDACR38␉R0␊ |
| 448 | #define SDACR39␉R0␊ |
| 449 | #define SDACR40␉R0␊ |
| 450 | #define SDACR41␉R3␊ |
| 451 | #define SDACR42␉R1␊ |
| 452 | #define SDACR43␉R0␊ |
| 453 | #define SDACR44␉R0␊ |
| 454 | #define SDACR45␉R0␊ |
| 455 | #define SDACR46␉R0␊ |
| 456 | #define SDACR47␉R0␊ |
| 457 | #define SDACR48␉R0␊ |
| 458 | #define SDACR49␉R0␊ |
| 459 | #define SDACR50␉R0␊ |
| 460 | #define SDACR51␉R1␊ |
| 461 | #define SDACR52␉R0␊ |
| 462 | #define SDACR53␉R0␊ |
| 463 | #define SDACR54␉R0␊ |
| 464 | #define SDACR55␉R0␊ |
| 465 | #define SDACR56␉R0␊ |
| 466 | #define SDACR57␉R0␊ |
| 467 | #define SDACR58␉R0␊ |
| 468 | #define SDACR59␉R0␊ |
| 469 | #define SDACR60␉R0␊ |
| 470 | #define SDACR61␉R0␊ |
| 471 | #define SDACR62␉R0␊ |
| 472 | #define SDACR63␉R0␊ |
| 473 | ␊ |
| 474 | #endif /* SD_H */␊ |
| 475 | |
