Chameleon

Chameleon Commit Details

Date:2013-07-07 02:52:07 (10 years 9 months ago)
Author:ErmaC
Commit:2253
Parents: 2252
Message:- Revert back commit 2211. - Switch defined processor name to match xnu kernel name (issue 344) - Update ATi and nVidia card list. - Merge Geoff Seeley patch (Issue 59).
Changes:
M/trunk/i386/modules/AcpiCodec/acpi_codec.c
M/trunk/i386/libsaio/dram_controllers.c
M/trunk/i386/libsaio/nvidia.c
M/trunk/i386/boot2/modules.c
M/trunk/CHANGES
M/trunk/i386/libsaio/ati.c
M/trunk/i386/libsaio/nvidia.h
M/trunk/i386/boot2/drivers.c
M/trunk/i386/libsaio/ati.h
M/trunk/i386/libsaio/acpi_patcher.c
M/trunk/i386/libsaio/memvendors.h
M/trunk/i386/libsaio/spd.c
M/trunk/i386/libsaio/cpu.c
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/smbios_getters.c
M/trunk/i386/libsaio/cpu.h
M/trunk/i386/libsaio/smbios.c
M/trunk/i386/libsaio/smbios_getters.h
M/trunk/i386/libsaio/smbios_decode.c
M/trunk/i386/libsaio/xml.c

File differences

trunk/i386/libsaio/smbios_getters.h
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extern bool getSMBOemProcessorBusSpeed(returnType *value);␊
extern bool getSMBOemProcessorType(returnType *value);␊
extern bool getSMBMemoryDeviceMemoryType(returnType *value);␊
extern bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value);␊
extern bool getSMBMemoryDeviceMemorySpeed(returnType *value);␊
extern bool getSMBMemoryDeviceManufacturer(returnType *value);␊
extern bool getSMBMemoryDeviceSerialNumber(returnType *value);␊
trunk/i386/libsaio/xml.c
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␉//printf("ParseTagData unimplimented\n");␊
␉//printf("Data: %s\n", buffer);␊
␉//␉getchar();␊
␉␉␊
␊
␉char* string = BASE64Decode(buffer, strlen(buffer), &actuallen);␊
tmpTag->type = kTagTypeData;␊
tmpTag->string = string;␊
trunk/i386/libsaio/acpi_patcher.c
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␉␉␉␉␉}␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␉␉␊
␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65xx␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␉//␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON: //␊
␉␉␉␉␉//case CPU_MODEL_HASWELL_H:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉//␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULX:␉//␊
␊
␉␉␉␉␉{␊
␉␉␉␉␉if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE_XEON))␊
␉␉␉␉␉if ((Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_JAKETOWN) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE) || (Platform.CPU.Model == CPU_MODEL_HASWELL) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_IVYBRIDGE_XEON) || (Platform.CPU.Model == CPU_MODEL_HASWELL_MB) ||␊
␉␉␉␉␉␉(Platform.CPU.Model == CPU_MODEL_HASWELL_ULT) || (Platform.CPU.Model == CPU_MODEL_HASWELL_ULX))␊
␉␉␉␉␉{␊
␉␉␉␉␉␉ maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;␊
␉␉␉␉␉} else {␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; ␊
␉␉␉␉␉␉maximum.Control = (rdmsr64(MSR_IA32_PERF_STATUS) >> 8) & 0xff;␊
␉␉␉␉␉}␊
␉␉␉␉␉else␊
␉␉␉␉␉{␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff;␊
␉␉␉␉␉}␊
␊
␉␉␉␉␉minimum.Control = (rdmsr64(MSR_PLATFORM_INFO) >> 40) & 0xff;␊
␊
trunk/i386/libsaio/spd.c
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/*␊
* spd.c - serial presence detect memory information␊
*␊
* Originally restored from pcefi10.5␊
* Originally restored from pcefi10.5 by netkas␊
* Dynamic mem detection original impl. by Rekursor␊
* System profiler fix and other fixes by Mozodojo.␊
*/␊
␉{0x8086, 0x3A60, "ICH10B",␉␉read_smb_intel },␊
␉{0x8086, 0x3B30, "5 Series",␉␉read_smb_intel },␊
␉{0x8086, 0x1C22, "6 Series",␉␉read_smb_intel },␊
␉{0x8086, 0x1D22, "C600/X79 Series",␉read_smb_intel },␊
␉{0x8086, 0x1E22, "7 Series",␉␉read_smb_intel },␊
␉{0x8086, 0x5032, "EP80579",␉␉read_smb_intel },␊
␉{0x8086, 0x1D22, "X79 Series",␉␉read_smb_intel },␊
␉{0x8086, 0x8C22, "8 Series",␉␉read_smb_intel },␊
␉{0x8086, 0x9C22, "Lynx Point-LP", read_smb_intel }␊
␊
};␊
␊
trunk/i386/libsaio/memvendors.h
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/*␊
* Memory module vendors as published by JEDEC 106AA ␊
*␊
* Special thanks to indi, memtest and theking for the table␊
* Special thanks to iNDi, memtest and THeKiNG for the table␊
*␊
*/␊
#ifndef __MEMVEN_H␊
#define __MEMVEN_H␊
␊
typedef struct _vidTag {␊
uint8_t bank;␊
uint8_t code;␊
const char* name;␊
typedef struct _vidTag␊
{␊
␉uint8_t␉␉bank;␊
␉uint8_t␉␉code;␊
␉const char*␉name;␊
} VenIdName;␊
␊
VenIdName vendorMap[] = {␊
trunk/i386/libsaio/dram_controllers.c
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␉// Activate MMR I/O␊
␉dev0 = pci_config_read32(dram_dev->dev.addr, 0x48);␊
␉if (!(dev0 & 0x1))␊
␉{␊
␉␉pci_config_write8(dram_dev->dev.addr, 0x48, (dev0 | 1));␊
␉}␊
}␊
␊
int nhm_bus = 0x3F;␊
␉␉did &= 0xFF00;␊
␉␉␊
␉␉if(vid == 0x8086 && did >= 0x2C00)␊
␉␉{␊
␉␉␉nhm_bus = possible_nhm_bus[i]; ␊
␉␉}␊
␉}␊
}␊
␊
␉switch (mch_fsb)␊
␉{␊
␉␉case 533:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 1:␉mch_ratio = 200000; break;␊
␉␉␉case 2:␉mch_ratio = 250000; break;␊
␉␉␉case 3:␉mch_ratio = 300000; break;␊
␉␉}␊
␉␉␉break;␊
␉␉break;␊
␉␉␉␊
␉␉default:␊
␉␉case 800:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 0:␉mch_ratio = 100000; break;␊
␉␉␉case 1:␉mch_ratio = 125000; break;␊
␉␉␉case 4:␉mch_ratio = 266667; break; // 2.666666667␊
␉␉␉case 5:␉mch_ratio = 333333; break; // 3.333333333␊
␉␉}␊
␉␉␉break;␊
␉␉break;␊
␉␉␉␊
␉␉case 1066:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 1:␉mch_ratio = 100000; break;␊
␉␉␉case 2:␉mch_ratio = 125000; break;␊
␉␉␉case 4:␉mch_ratio = 200000; break;␊
␉␉␉case 5:␉mch_ratio = 250000; break;␊
␉␉}␊
␉␉␉break;␊
␉␉break;␊
␉␉␉␊
␉␉case 1333:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 2:␉mch_ratio = 100000; break;␊
␉␉␉case 3:␉mch_ratio = 120000; break;␊
␉␉␉case 4:␉mch_ratio = 160000; break;␊
␉␉␉case 5:␉mch_ratio = 200000; break;␊
␉␉}␊
␉␉␉break;␊
␉␉break;␊
␉␉␉␊
␉␉case 1600:␊
␉␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉switch ((mch_cfg >> 4) & 7)␊
␉␉{␊
␉␉␉case 3:␉mch_ratio = 100000; break;␊
␉␉␉case 4:␉mch_ratio = 133333; break; // 1.333333333␊
␉␉␉case 5:␉mch_ratio = 150000; break;␊
␉␉␉case 6:␉mch_ratio = 200000; break;␊
␉␉}␊
␉␉␉break;␊
␉␉break;␊
␉}␊
␉␊
␉DBG("mch_ratio %d\n", mch_ratio);␊
␉␉␉}␊
␉␉␉break;␊
␉␉case 1066:␊
␉␉␉switch ((mch_cfg >> 4)&7) {␊
␉␉␉switch ((mch_cfg >> 4)&7)␊
␉␉␉{␊
␉␉␉␉case 5:␉mch_ratio = 150000; break;␊
␉␉␉␉case 6:␉mch_ratio = 200000; break;␊
␉␉␉}␊
␉// Compute RAM Frequency␊
␉Platform.RAM.Frequency = Platform.CPU.FSBFrequency * mch_ratio / 2;␊
}␊
␊
␊
/*␊
* Retrieve memory controller info functions␊
*/␊
␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR2;␊
␉else␊
␉␉Platform.RAM.Type = SMB_MEM_TYPE_DDR3;␊
␉␊
␊
␉// CAS Latency (tCAS)␊
␉if(dram_dev->device_id > 0x2E00)␊
␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 6;␊
␉else␊
␉␉Platform.RAM.CAS = ((ODT_Control_Register >> 8) & 0x3F) - 9;␊
␉␊
␊
␉// RAS-To-CAS (tRCD)␊
␉Platform.RAM.TRC = (Read_Register >> 17) & 0xF;␊
␉␊
␉␉fvc_bn = 5; ␊
␉else if(mc_control & 7) ␊
␉␉fvc_bn = 6; ␊
␉␊
␊
␉// Now, detect timings␊
␉mc_channel_bank_timing = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x88);␊
␉mc_channel_mrs_value = pci_config_read32(PCIADDR(nhm_bus, fvc_bn, 0), 0x70);␊
␉␉␉␊
␉␉␉if (dram_controllers[i].initialise != NULL)␊
␉␉␉␉dram_controllers[i].initialise(dram_dev);␊
␉␉␉␉␉␉␉␊
␊
␉␉␉if (dram_controllers[i].poll_timings != NULL)␊
␉␉␉␉dram_controllers[i].poll_timings(dram_dev);␊
␉␉␉␉␉␉␉␉␊
␊
␉␉␉if (dram_controllers[i].poll_speed != NULL)␊
␉␉␉␉dram_controllers[i].poll_speed(dram_dev);␊
␊
␉␉␉␉␉,Platform.RAM.CAS, Platform.RAM.TRC, Platform.RAM.TRP, Platform.RAM.RAS␊
␉␉␉␉␉);␊
//␉␉␉getchar();␉␉␊
␉␉}␉␊
}␉␊
␉␉}␊
}␊
trunk/i386/libsaio/nvidia.c
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const char *nvidia_compatible_1[] =␉{ "@1,compatible",␉"NVDA,NVMac"␉ };␊
const char *nvidia_device_type_0[] =␉{ "@0,device_type",␉"display"␉ };␊
const char *nvidia_device_type_1[] =␉{ "@1,device_type",␉"display"␉ };␊
const char *nvidia_device_type[] =␉{ "device_type",␉"NVDA,Parent"␉ };␊
const char *nvidia_device_type_parent[] =␉{ "device_type",␉"NVDA,Parent"␉ };␊
const char *nvidia_device_type_child[]␉=␉{ "device_type",␉"NVDA,Child"␉ };␊
const char *nvidia_name_0[] =␉{ "@0,name",␉␉"NVDA,Display-A" };␊
const char *nvidia_name_1[] =␉{ "@1,name",␉␉"NVDA,Display-B" };␊
␉// 1180 - 118F␊
␉{ 0x10DE1180,␉"GeForce GTX 680" },␊
␉{ 0x10DE1183,␉"GeForce GTX 660 Ti" },␊
␉{ 0x10DE1184,␉"GeForce GTX 770" },␊
␉{ 0x10DE1185,␉"GeForce GTX 660" },␊
␉{ 0x10DE1188,␉"GeForce GTX 690" },␊
␉{ 0x10DE1189,␉"GeForce GTX 670" },␊
␉{ 0x10DE11C4,␉"GeForce GTX 645" },␊
␉{ 0x10DE11C6,␉"GeForce GTX 650 Ti" },␊
␉// 11D0 - 11DF␊
␉{ 0x10DE11D0,␉"GK106-INT353" },␊
␉// 11E0 - 11EF␊
␉{ 0x10DE11E0,␉"GeForce GTX 770M" },␊
␉{ 0x10DE11E1,␉"N14E-GE-B-A1" },␊
␉// 1270 - 127F␊
␉// 1280 - 128F␊
␉{ 0x10DE1280,␉"GeForce GT 635" },␊
␉{ 0x10DE1282,␉"GeForce GT 640" },␊
␉{ 0x10DE1284,␉"GeForce GT 630" },␊
␉// 1290 - 129F␊
␉{ 0x10DE1290,␉"GeForce GT 730M" },␊
␉{ 0x10DE1291,␉"GeForce GT 735M" },␊
␉␉return 0;␊
␉if (devices_number == 1)␊
␉{␊
␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type))␊
␉␉ return 0;␊
␉␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_parent))␊
␉␉␉return 0;␊
␉}␊
␉else␊
␉{␊
␉ if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
␉␉ return 0;␊
␉␉if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))␊
␉␉␉return 0;␊
␉}␊
␊
␉// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!␊
}␊
␊
static bool checkNvRomSig(uint8_t * aRom){␊
return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);␊
␉return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);␊
}␊
␊
bool setup_nvidia_devprop(pci_dt_t *nvda_dev)␊
{␊
␉struct DevPropDevice␉*device;␊
␉char␉␉␉␉␉*devicepath;␊
␉option_rom_pci_header_t *rom_pci_header;␊
␉struct DevPropDevice␉␉*device = NULL;␊
␉char␉␉␉␉*devicepath = NULL;␊
␉option_rom_pci_header_t␉␉*rom_pci_header;␊
␉volatile uint8_t␉␉*regs;␊
␉uint8_t␉␉␉␉␉*rom;␊
␉uint8_t␉␉␉␉␉*nvRom;␊
␉uint8_t␉␉␉␉␉nvCardType;␊
␉unsigned long long␉␉videoRam;␊
␉uint32_t␉␉␉␉nvBiosOveride;␊
␉uint32_t␉␉␉␉bar[7];␊
␉uint32_t␉␉␉␉boot_display;␊
␉int␉␉␉␉␉␉nvPatch;␊
␉int␉␉␉␉␉␉len;␊
␉char␉␉␉␉␉biosVersion[32];␊
␉char␉␉␉␉␉nvFilename[32];␊
␉char␉␉␉␉␉kNVCAP[12];␊
␉char␉␉␉␉␉*model;␊
␉const char␉␉␉␉*value;␊
␉bool␉␉␉␉␉doit;␊
␉uint8_t␉␉␉␉*rom = NULL;␊
␉uint8_t␉␉␉␉*nvRom;␊
␉uint8_t␉␉␉␉nvCardType = 0;␊
␉unsigned long long␉␉videoRam = 0;␊
␉uint32_t␉␉␉nvBiosOveride;␊
␉uint32_t␉␉␉bar[7];␊
␉uint32_t␉␉␉boot_display = 0;␊
␉int␉␉␉␉nvPatch = 0;␊
␉int␉␉␉␉len;␊
␉char␉␉␉␉biosVersion[64];␊
␉char␉␉␉␉nvFilename[64];␊
␉char␉␉␉␉kNVCAP[12];␊
␉char␉␉␉␉*model = NULL;␊
␉const char␉␉␉*value;␊
␉bool␉␉␉␉doit;␊
␊
␉fill_card_list();␊
␊
␉}␊
␉else␊
␉{␊
rom = malloc(NVIDIA_ROM_SIZE);␊
␉␉rom = malloc(NVIDIA_ROM_SIZE);␊
␊
␉␉// Otherwise read bios from card␊
␉␉nvBiosOveride = 0;␊
␊
// PROM first␊
// Enable PROM access␊
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
␉␉// PROM first␊
␉␉// Enable PROM access␊
␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;␊
␉␉nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];␊
␊
// Valid Signature ?␊
␉␉// Valid Signature ?␊
␉␉if (checkNvRomSig(nvRom))␊
␉␉{␊
bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
}␊
else␊
{␊
␉␉␉bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
␉␉␉DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
␉␉}␊
␉␉else␊
␉␉{␊
␊
// disable PROM access␊
(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
␉␉␉// disable PROM access␊
␉␉␉(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;␊
␊
␉ //PRAM next␊
nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
␉␉␉//PRAM next␊
␉␉␉nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];␊
␊
if(checkNvRomSig(nvRom))␊
{␊
bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
}␊
else␊
␉␉{␊
␉␉␉if(checkNvRomSig(nvRom))␊
␉␉␉{␊
␉␉␉␉bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);␊
␉␉␉␉DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
␉␉␉}␊
␉␉␉else␊
␉␉␉{␊
␉␉␉␉// 0xC0000 last␊
␉␉␉␉bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);␊
␉␉␉␉␊
␊
␉␉␉␉// Valid Signature ?␊
␉␉␉␉if (!checkNvRomSig(rom))␊
␉␉␉␉{␊
␉␉␉␉}␊
␉␉else␊
␉␉{␊
␉␉␉␉␉DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
␉␉␉ DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);␊
␉␉}␊
␉␉}//end PRAM check␊
}//end PROM check␊
␉default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],␊
␉default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);␊
#endif␊
␉␊
␊
␉devprop_add_nvidia_template(device);␊
␉devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);␊
␉devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);␊
trunk/i386/libsaio/ati.c
11381138
11391139
11401140
1141
1141
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11441144
......
11991199
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......
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......
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......
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......
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......
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......
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......
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......
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......
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␊
␉{ 0x7186,␉0x00000000, CHIP_FAMILY_RV515,␉␉"ATI Radeon HD Mobile ", kCaretta␉␉ },␊
␉{ 0x7187,␉0x00000000, CHIP_FAMILY_RV515,␉␉"ATI Radeon HD Desktop ", kCaretta␉␉ },␊
␉{ 0x7188,␉0x00000000, CHIP_FAMILY_RV515,␉␉"ATI Radeon HD Mobile ", kCaretta␉␉ },␊
␉{ 0x7188,␉0x00000000, CHIP_FAMILY_RV515,␉␉"ATI Radeon HD2300 Mobile ", kCaretta␉␉ },␊
␊
␉{ 0x718A,␉0x00000000, CHIP_FAMILY_RV515,␉␉"ATI Radeon HD Mobile ", kCaretta␉␉ },␊
␉{ 0x718B,␉0x00000000, CHIP_FAMILY_RV515,␉␉"ATI Radeon HD Mobile ", kCaretta␉␉ },␊
␉{ 0x724E,␉0x00000000, CHIP_FAMILY_R580,␉␉"ATI Radeon HD Desktop ", kAlopias␉␉ },␊
␉{ 0x724F,␉0x00000000, CHIP_FAMILY_R580,␉␉"ATI Radeon HD Desktop ", kAlopias␉␉ },␊
␊
␉{ 0x7280,␉0x00000000, CHIP_FAMILY_RV570,␉␉"ATI Radeon HD X1950 Pro ", kAlopias␉␉ },␊
␉{ 0x7280,␉0x00000000, CHIP_FAMILY_RV570,␉␉"ATI Radeon X1950 Pro ", kAlopias␉␉ },␊
␉{ 0x7281,␉0x00000000, CHIP_FAMILY_RV560,␉␉"ATI Radeon HD Desktop ", kAlopias␉␉ },␊
␉{ 0x7283,␉0x00000000, CHIP_FAMILY_RV560,␉␉"ATI Radeon HD Desktop ", kAlopias␉␉ },␊
␉{ 0x7284,␉0x00000000, CHIP_FAMILY_R580,␉␉"ATI Radeon HD Mobile ", kAlopias␉␉ },␊
␉{ 0x9402,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 GT", kNull␉␉},␊
␉{ 0x9403,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 GT", kNull␉␉},␊
␉{ 0x9405,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 GT", kNull␉␉},␊
␉{ 0x940A,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 GT", kNull␉␉},␊
␉{ 0x940B,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 GT", kNull␉␉},␊
␉{ 0x940F,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI Radeon HD 2900 GT", kNull␉␉},␊
␉{ 0x940A,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI FireGL V8650", kNull␉␉},␊
␉{ 0x940B,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI FireGL V8600", kNull␉␉},␊
␉{ 0x940F,␉0x00000000, CHIP_FAMILY_R600,␉␉"ATI FireGL V7600", kNull␉␉},␊
␊
␉{ 0x9440,␉0x00000000, CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870 ",␉␉kMotmot␉␉},␊
␉{ 0x9441,␉0x00000000, CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4870 X2", kMotmot␉␉},␊
␉{ 0x9460,␉0x00000000, CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␉{ 0x9462,␉0x00000000, CHIP_FAMILY_RV770,␉␉"ATI Radeon HD 4800 Series",␉␉kMotmot␉␉},␊
␊
␉{ 0x9480,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4650 Series",␉␉kGliff␉␉},␊
␉{ 0x9480,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Mobility Radeon HD 550v",␉␉kGliff␉␉},␊
␊
␉{ 0x9487,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD Series",␉␉kGliff␉␉},␊
␉{ 0x9488,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4650 Series",␉␉kGliff␉␉},␊
␉{ 0x9489,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD Series",␉␉kGliff␉␉},␊
␉{ 0x948A,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD Series",␉␉kGliff␉␉},␊
␉{ 0x948F,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD Series",␉␉kGliff␉␉},␊
␉{ 0x9490,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4710 Series",␉␉kGliff␉␉},␊
␉{ 0x9490,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4670 Series",␉␉kGliff␉␉},␊
␉{ 0x9491,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4600 Series",␉␉kGliff␉␉},␊
␉{ 0x9495,␉0x00000000, CHIP_FAMILY_RV730,␉␉"ATI Radeon HD 4650 Series",␉␉kGliff␉␉},␊
␊
␉{ 0x955F,␉0x00000000, CHIP_FAMILY_RV710,␉␉"ATI Radeon HD 4330M series", kFlicker␉},␊
␊
␉{ 0x9580,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD Series",␉␉␉kHypoprion␉},␊
␉{ 0x9581,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉␉kHypoprion␉},␊
␉{ 0x9581,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 XT",␉␉␉kHypoprion␉},␊
␊
␉{ 0x9583,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3600 Series",␉␉␉kHypoprion␉},␊
␉{ 0x9583,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 XT",␉␉␉kHypoprion␉},␊
␊
␉{ 0x9586,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 XT Series",␉␉␉kHypoprion␉},␊
␉{ 0x9587,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 Pro Series",␉␉␉kHypoprion␉},␊
␉{ 0x9588,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 XT",␉␉␉kHypoprion␉},␊
␉{ 0x9589,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 3610 Series",␉␉␉kHypoprion␉},␊
␉{ 0x9589,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 PRO",␉␉␉kHypoprion␉},␊
␉{ 0x958A,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 X2 Series",␉␉␉kLamna␉␉},␊
␉{ 0x958B,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 X2 Series",␉␉␉kLamna␉␉},␊
␉{ 0x958C,␉0x00000000, CHIP_FAMILY_RV630,␉␉"ATI Radeon HD 2600 X2 Series",␉␉␉kLamna␉␉},␊
␊
␉/* IGP */␊
␉{ 0x9610,␉0x00000000, CHIP_FAMILY_RS780,␉␉"ATI Radeon HD 3200 Graphics",␉␉␉kNull␉␉},␊
␉{ 0x9611,␉0x00000000, CHIP_FAMILY_RS780,␉␉"ATI Radeon 3100 Graphics", ␉kNull␉␉},␊
␉{ 0x9611,␉0x00000000, CHIP_FAMILY_RS780,␉␉"ATI Radeon HD 3100 Graphics", ␉kNull␉␉},␊
␊
␉{ 0x9614,␉0x00000000, CHIP_FAMILY_RS780,␉␉"ATI Radeon HD 3300 Graphics",␉␉␉kNull␉␉},␊
␊
␉{ 0x9616,␉0x00000000, CHIP_FAMILY_RS780,␉␉"ATI Radeon 3000 Graphics", ␉kNull␉␉},␊
␉{ 0x9616,␉0x00000000, CHIP_FAMILY_RS780,␉␉"AMD 760G", ␉kNull␉␉},␊
␊
␉{ 0x9710,␉0x00000000, CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4200 Series",␉␉␉kNull␉␉},␊
␊
␉{ 0x9714,␉0x00000000, CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4290 Series",␉␉␉kNull␉␉},␊
␉{ 0x9715,␉0x00000000, CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4250 Series",␉␉␉kNull␉␉},␊
␉{ 0x9714,␉0x00000000, CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4290",␉␉␉kNull␉␉},␊
␉{ 0x9715,␉0x00000000, CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 4250",␉␉␉kNull␉␉},␊
␊
␉{ 0x9723,␉0x00000000, CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 5450 Series",␉␉␉kNull␉␉},␊
␊
␉{ 0x9806,␉0x00000000, CHIP_FAMILY_RS880,␉␉"ATI Radeon HD 6320 Series",␉␉␉kNull␉␉},␊
␊
␉/* Evergreen */␊
␉{ 0x688D,␉0x00000000, CHIP_FAMILY_CYPRESS,␉"AMD FireStream 9350 Series",␉␉␉kUakari␉␉},␊
␉{ 0x688D,␉0x00000000, CHIP_FAMILY_CYPRESS,␉"AMD FireStream 9350",␉␉␉kZonalis␉␉},␊
␊
␉{ 0x6898,␉0x00000000, CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5800 Series",␉␉␉kUakari␉␉},␊
␉{ 0x6899,␉0x00000000, CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5800 Series",␉␉␉kUakari␉␉},␊
␉{ 0x6898,␉0x00000000, CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5870 Series",␉␉␉kUakari␉␉},␊
␉{ 0x6899,␉0x00000000, CHIP_FAMILY_CYPRESS,␉"ATI Radeon HD 5850 Series",␉␉␉kUakari␉␉},␊
␊
//␉{ 0x689B,␉0x00000000, CHIP_FAMILY_???,␉␉"AMD Radeon HD 6800 Series",␉␉␉kNull␉␉},␊
␉{ 0x689C,␉0x00000000, CHIP_FAMILY_HEMLOCK,␉"ATI Radeon HD 5900 Series",␉␉␉kUakari␉␉},␊
␊
␉{ 0x689E,␉0x00000000, CHIP_FAMILY_HEMLOCK,␉"ATI Radeon HD 5800 Series",␉␉␉kUakari␉␉},␊
␊
␉{ 0x68A0,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Mobility Radeon HD 5800 Series", kNomascus␉}, // CHIP_FAMILY_BROADWAY ??␊
␉{ 0x68A1,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Mobility Radeon HD 5800 Series", kNomascus␉}, // CHIP_FAMILY_BROADWAY ??␊
␉{ 0x68A0,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770 Series",␉␉␉kHoolock␉}, // CHIP_FAMILY_BROADWAY ??␊
␉{ 0x68A1,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5850 Series",␉␉␉kHoolock␉}, // CHIP_FAMILY_BROADWAY ??␊
␊
␉{ 0x68A8,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"AMD Mobility Radeon HD 6800 Series", kNomascus␉␉},␊
␉{ 0x68A9,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI FirePro V5800 (FireGL)",␉␉␉kNull␉␉},␊
␉{ 0x68A8,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 6850M",␉␉␉kHoolock␉␉},␊
␉{ 0x68A9,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI FirePro V5800 (FireGL)",␉␉␉kHoolock␉},␊
␊
␊
␉{ 0x68B0,␉0x00000000, CHIP_FAMILY_CYPRESS,␉"ATI Mobility Radeon HD 5800 Series", kHoolock␉␉}, // CHIP_FAMILY_BROADWAY ??␊
␉{ 0x68B1,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770 Series",␉␉␉kHoolock␉␉},␊
␊
␉{ 0x68B8,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5700 Series",␉␉␉kHoolock␉␉},␊
␉{ 0x68B9,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5600 Series",␉␉␉kHoolock␉␉},␊
␉{ 0x68B8,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5770 Series",␉␉␉kHoolock␉␉},␊
␉{ 0x68B9,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5700 Series",␉␉␉kHoolock␉␉},␊
␉{ 0x68BA,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 6700 Series",␉␉␉kHoolock␉␉},␊
␊
␉{ 0x68BE,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5700 Series",␉␉␉kHoolock␉␉},␊
␉{ 0x68BF,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"AMD Radeon HD 6700 Series",␉␉␉kHoolock␉␉},␊
␉{ 0x68BE,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5750 Series",␉␉␉kHoolock␉␉},␊
␉{ 0x68BF,␉0x00000000, CHIP_FAMILY_JUNIPER,␉"ATI Radeon HD 5700 Series",␉␉␉kHoolock␉␉},␊
␊
␉{ 0x68C0,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"AMD Radeon HD 6570M/5700 Series",␉␉kBaboon␉␉},␊
␉{ 0x68C1,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"AMD Radeon HD 6500M/5600/5700 Series",␉␉kBaboon␉␉},␊
␉{ 0x68C8,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5650 Series",␉␉␉kVervet␉␉},␉␊
␉{ 0x68C9,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI FirePro V3800 (FireGL)",␉␉␉kBaboon␉␉},␊
␉{ 0x68C8,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5650 Series",␉␉␉kBaboon␉␉},␉␊
␉{ 0x68C9,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"FirePro 3D V3800",␉␉␉kBaboon␉␉},␊
␊
␉{ 0x68D8,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5670 Series",␉␉␉kBaboon␉␉},␊
␉{ 0x68D9,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5500/5600 Series",␉␉kBaboon␉␉},␊
//␉{ 0x68DE,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD ??? Series",␉␉␉kNull␉␉},␊
␊
␊
␉{ 0x68E0,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI Mobility Radeon HD 5400 Series", kEulemur␉},␊
␉{ 0x68E1,␉0x00000000, CHIP_FAMILY_CEDAR,␉"ATI Mobility Radeon HD 5400 Series", kEulemur␉},␊
␉{ 0x68E0,␉0x00000000, CHIP_FAMILY_REDWOOD,␉"ATI Radeon HD 5470 Series", kEulemur␉},␊
␉{ 0x68E1,␉0x00000000, CHIP_FAMILY_CEDAR,␉␉"ATI Mobility Radeon HD 5400", kEulemur␉},␊
␊
␉{ 0x68E4,␉0x00000000, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 6370M Series",␉␉␉kEulemur␉␉},␊
␉{ 0x68E5,␉0x00000000, CHIP_FAMILY_CEDAR,␉␉"ATI Radeon HD 6300M Series",␉␉␉kEulemur␉␉},␊
␊
␉/* Northen Islands */␊
␉{ 0x6718,␉0x00000000, CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6970 Series",␉␉␉kLotus␉␉},␊
␉{ 0x6719,␉0x00000000, CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6950 Series",␉␉␉kGibba␉␉},␊
␉{ 0x6719,␉0x00000000, CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6950 Series",␉␉␉kLotus␉␉},␊
␊
␉{ 0x671C,␉0x00000000, CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6970 Series",␉␉␉kLotus␉␉},␊
␉{ 0x671D,␉0x00000000, CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6950 Series",␉␉␉kLotus␉␉},␊
␊
␉{ 0x671F,␉0x00000000, CHIP_FAMILY_CAYMAN,␉␉"AMD Radeon HD 6930 Series",␉␉␉kLotus␉␉},␊
␊
␉{ 0x6720,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6900M Series",␉␉␉kFanwort␉␉},␊
␉{ 0x6720,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6900M Series",␉␉␉kFanwort␉},␊
␊
␉{ 0x6722,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6900M Series",␉␉␉kFanwort␉␉},␊
␉{ 0x6729,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6900M Series",␉␉␉kFanwort␉␉},␊
␉{ 0x6722,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6900M Series",␉␉␉kFanwort␉},␊
␉{ 0x6729,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6900M Series",␉␉␉kFanwort␉},␊
␉{ 0x6738,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6870 Series",␉␉␉kDuckweed␉},␊
␉{ 0x6739,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6850 Series",␉␉␉kDuckweed␉},␊
␊
␉{ 0x673E,␉0x00000000, CHIP_FAMILY_BARTS,␉␉"AMD Radeon HD 6790 Series",␉␉␉kDuckweed␉␉},␊
␊
␉{ 0x6740,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6770M Series",␉␉␉kCattail␉␉},␊
␉{ 0x6741,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6750M Series",␉␉␉kCattail␉␉},␊
␉{ 0x6741,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6750M",␉␉␉kCattail␉␉},␊
␊
␉{ 0x6745,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6600M Series",␉␉␉kCattail␉␉},␊
␉{ 0x6749,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"ATI Radeon FirePro V4900",␉␉␉kPithecia␉␉},␊
␉{ 0x674A,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6600M Series",␉␉␉kCattail␉␉},␊
␉{ 0x6750,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6600A Series",␉␉␉kPithecia␉␉},␊
␉{ 0x6750,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6670 Series",␉␉␉kPithecia␉␉},␊
␊
␉{ 0x6758,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6670 Series",␉␉␉kPithecia␉},␊
␉{ 0x6759,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6570/7570 Series",␉␉kPithecia␉␉},␊
␊
␉{ 0x675D,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 7570M Series",␉␉␉kCattail␉␉},␊
␊
␉{ 0x675F,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6570 Series",␉␉␉kBulrushes␉␉},␊
␉{ 0x6760,␉0x00000000, CHIP_FAMILY_CAICOS,␉␉"AMD Radeon HD 6400M Series",␉␉␉kHydrilla␉␉},␊
␉{ 0x675F,␉0x00000000, CHIP_FAMILY_TURKS,␉␉"AMD Radeon HD 6570 Series",␉␉␉kPithecia␉␉},␊
␉{ 0x6760,␉0x00000000, CHIP_FAMILY_CAICOS,␉␉"AMD Radeon HD 6470M Series",␉␉␉kHydrilla␉␉},␊
␉{ 0x6761,␉0x00000000, CHIP_FAMILY_CAICOS,␉␉"AMD Radeon HD 6430M Series",␉␉␉kHydrilla␉␉},␊
␉{ 0x6768,␉0x00000000, CHIP_FAMILY_CAICOS,␉␉"AMD Radeon HD 6400M Series",␉␉␉kHydrilla␉},␊
␊
␉{ 0x679E,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7870 XT", kFutomaki␉␉}, // ATI7000Controller.kext␊
␉{ 0x679F,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7950 Series", kFutomaki␉␉},␊
␊
␉{ 0x6800,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7970M", kFutomaki␉}, // ATI7000Controller.kext␊
//␉{ 0x6801,␉0x00000000, CHIP_FAMILY_PITCAIRN,␉"AMD Radeon HD ???M Series", kFutomaki␉␉},␊
␉{ 0x6800,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7970M", kBuri␉}, // ATI7000Controller.kext␊
//␉{ 0x6801,␉0x00000000, CHIP_FAMILY_PITCAIRN,␉"AMD Radeon HD 8970M Series", kFutomaki␉␉},␊
//␉{ 0x6802,␉0x00000000, CHIP_FAMILY_PITCAIRN,␉"AMD Radeon HD ???M Series", kFutomaki␉␉},␊
␊
␉{ 0x6806,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7600 Series", kFutomaki␉}, // ATI7000Controller.kext␊
//␉{ 0x6809,␉0x00000000, CHIP_FAMILY_PITCAIRN,␉"AMD Radeon HD ??? Series", kNull␉␉},␊
//␉{ 0x6810,␉0x00000000, CHIP_FAMILY_PITCAIRN,␉"AMD Radeon HD ??? Series", kNull␉␉},␊
␊
␉{ 0x6818,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7800 Series", kFutomaki␉}, // CHIP_FAMILY_PITCAIRN ??// ATI7000Controller.kext␊
␉{ 0x6818,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7870 Series", kFutomaki␉}, // CHIP_FAMILY_PITCAIRN ??// ATI7000Controller.kext␊
␉{ 0x6819,␉0x00000000, CHIP_FAMILY_TAHITI,␉␉"AMD Radeon HD 7850 Series", kFutomaki␉},// CHIP_FAMILY_PITCAIRN ??␊
␉{ 0x6820,␉0x00000000, CHIP_FAMILY_VERDE,␉␉"AMD Radeon HD 7700 Series", kBuri␉}, // ATI7000Controller.kext␊
␉{ 0x6821,␉0x00000000, CHIP_FAMILY_VERDE,␉␉"AMD Radeon HD 7700 Series", kBuri␉}, // ATI7000Controller.kext␊
//␉{FLAGTRUE,␉true,␉"@0,device_type",␉␉␉NULL,␉␉␉␉␉STRVAL("display")␉␉␉␉},␊
//␉{FLAGTRUE,␉false,␉"@0,display-connect-flags", NULL,␉␉␉␉␉DWRVAL((uint32_t)0)␉␉␉␉},␊
//␉{FLAGTRUE,␉true,␉"@0,display-type",␉␉␉NULL,␉␉␉␉␉STRVAL("NONE")␉␉␉␉␉},␊
␉{FLAGTRUE,␉true,␉"@0,name",␉␉␉␉␉get_name_val,␉␉␉NULVAL␉␉␉␉␉␉␉},␊
␉{FLAGTRUE,␉true,␉"@0,name",␉␉␉␉get_name_val,␉␉␉NULVAL␉␉␉␉␉␉␉},␊
//␉{FLAGTRUE,␉true,␉"@0,VRAM,memsize",␉␉␉get_vrammemsize_val,␉NULVAL␉␉␉␉␉␉␉},␊
␊
//␉{FLAGTRUE,␉false,␉"AAPL,aux-power-connected",␉␉NULL,␉␉␉␉␉DWRVAL((uint32_t)1)␉␉␉␉},␊
bool load_vbios_file(const char *key, uint16_t vendor_id, uint16_t device_id, uint32_t subsys_id)␊
{␊
␉int fd;␊
␉char file_name[24];␊
␉char file_name[64];␊
␉bool do_load = false;␊
␊
␉getBoolForKey(key, &do_load, &bootInfo->chameleonConfig);␊
␉{␊
␉␉// else, match cfg_name with card_configs list and retrive default nr of ports.␊
␉␉for (i = 0; i < kCfgEnd; i++)␊
␉␉{␊
␉␉␉if (strcmp(card->cfg_name, card_configs[i].name) == 0)␊
␉␉␉{␊
␉␉␉␉card->ports = card_configs[i].ports; // default␊
␉␉␉}␊
␉␉}␊
␊
␉␉verbose("# of ports set to framebuffer's default: %d\n", card->ports);␊
␉}␊
␉aty_name.type = kStr;␊
␉aty_name.size = strlen(name) + 1;␊
␉aty_name.data = (uint8_t *)name;␊
␉␊
␊
␉sprintf(name_parent, "ATY,%sParent", card->cfg_name);␊
␉aty_nameparent.type = kStr;␊
␉aty_nameparent.size = strlen(name_parent) + 1;␊
trunk/i386/libsaio/nvidia.h
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␊
bool setup_nvidia_devprop(pci_dt_t *nvda_dev);␊
␊
struct nvidia_pci_info_t;␊
typedef struct {␊
␉uint32_t device; // VendorID + DeviceID␊
␉char *name;␊
} nvidia_pci_info_t;␊
␊
struct nvidia_card_info_t;␊
typedef struct {␊
␉uint32_t device; // VendorID + DeviceID␊
␉uint32_t subdev; // SubdeviceID + SubvendorID␊
trunk/i386/libsaio/ati.h
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......
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......
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␉/* Southern Islands */␊
␉CHIP_FAMILY_TAHITI,␊
␉CHIP_FAMILY_PITCAIRN,␊
␉CHIP_FAMILY_VERDE,␊
␉CHIP_FAMILY_THAMES,␊
␉CHIP_FAMILY_LOMBOK,␊
␉CHIP_FAMILY_VERDE,␊
␉CHIP_FAMILY_THAMES,␊
␉CHIP_FAMILY_LOMBOK,␊
//␉CHIP_FAMILY_NEWZEALAND,␊
␉CHIP_FAMILY_LAST␊
} ati_chip_family_t;␊
␊
//radeon card (includes teh AtiConfig)␊
typedef struct {␊
␉uint16_t␉␉␉␉device_id;␊
␉uint32_t␉␉␉␉subsys_id;␊
␉uint16_t␉␉␉device_id;␊
␉uint32_t␉␉␉subsys_id;␊
␉ati_chip_family_t␉␉chip_family;␊
␉const char␉␉␉␉*model_name;␊
␉const char␉␉␉*model_name;␊
␉ati_config_name_t␉␉cfg_name;␊
} radeon_card_info_t;␊
␊
} dev_prop_t;␊
␊
typedef struct {␊
␉struct DevPropDevice␉*device;␊
␉struct DevPropDevice␉␉*device;␊
␉radeon_card_info_t␉␉*info;␊
␉pci_dt_t␉␉␉␉*pci_dev;␊
␉uint8_t␉␉␉␉␉*fb;␊
␉uint8_t␉␉␉␉␉*mmio;␊
␉uint8_t␉␉␉␉␉*io;␊
␉uint8_t␉␉␉␉␉*rom;␊
␉uint32_t␉␉␉␉rom_size;␊
␉uint32_t␉␉␉␉vram_size;␊
␉const char␉␉␉␉*cfg_name;␊
␉uint8_t␉␉␉␉␉ports;␊
␉uint32_t␉␉␉␉flags;␊
␉bool␉␉␉␉␉posted;␊
␉pci_dt_t␉␉␉*pci_dev;␊
␉uint8_t␉␉␉␉*fb;␊
␉uint8_t␉␉␉␉*mmio;␊
␉uint8_t␉␉␉␉*io;␊
␉uint8_t␉␉␉␉*rom;␊
␉uint64_t␉␉␉rom_size;␊
␉uint64_t␉␉␉vram_size;␊
␉const char␉␉␉*cfg_name;␊
␉uint8_t␉␉␉␉ports;␊
␉uint32_t␉␉␉flags;␊
␉bool␉␉␉␉posted;␊
} card_t;␊
␊
␊
trunk/i386/libsaio/cpu.c
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␉};␊
␊
restart:␊
if (attempts >= 9) // increase to up to 9 attempts.␊
// This will flash-reboot. TODO: Use tscPanic instead.␊
printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
␉if (attempts >= 9) // increase to up to 9 attempts.␊
␉{␊
␉ // This will flash-reboot. TODO: Use tscPanic instead.␊
␉␉printf("Timestamp counter calibation failed with %d attempts\n", attempts);␊
␉}␊
attempts++;␊
enable_PIT2();␉␉// turn on PIT2␊
set_PIT2(0);␉␉// reset timer 2 to be zero␊
␊
␉if (p->CPU.Vendor == CPUID_VENDOR_INTEL &&␊
␉␉p->CPU.Family == 0x06 &&␊
␉␉p->CPU.Model >= CPUID_MODEL_NEHALEM &&␊
␉␉p->CPU.Model != CPUID_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
␉␉p->CPU.Model >= CPU_MODEL_NEHALEM &&␊
␉␉p->CPU.Model != CPU_MODEL_ATOM␉␉// MSR is *NOT* available on the Intel Atom CPU␊
␉␉)␊
␉{␊
␉␉msr = rdmsr64(MSR_CORE_THREAD_COUNT);␉␉␉␉␉// Undocumented MSR in Nehalem and newer CPUs␊
␉␉␉if (p->CPU.Family == 0x06 && (p->CPU.Model == CPU_MODEL_NEHALEM␉␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_FIELDS␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_CLARKDALE␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_DALES_32NM␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_NEHALEM_EX␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_WESTMERE_EX ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_SANDYBRIDGE_XEON ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_JAKETOWN ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_DT ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_MB ||␊
␉␉␉␉␉␉␉␉␉␉ //p->CPU.Model == CPU_MODEL_HASWELL_H ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊
␉␉␉{␊
␉␉␉␉msr = rdmsr64(MSR_PLATFORM_INFO);␊
␉␉␉␉DBG("msr(%d): platform_info %08x\n", __LINE__, bitfield(msr, 31, 0));␊
␉␉␉␉bus_ratio_max = bitfield(msr, 14, 8);␊
␉␉␉␉bus_ratio_min = bitfield(msr, 46, 40); //valv: not sure about this one (Remarq.1)␊
␉␉␉␉bus_ratio_max = bitfield(msr, 15, 8);␊
␉␉␉␉bus_ratio_min = bitfield(msr, 47, 40); //valv: not sure about this one (Remarq.1)␊
␉␉␉␉msr = rdmsr64(MSR_FLEX_RATIO);␊
␉␉␉␉DBG("msr(%d): flex_ratio %08x\n", __LINE__, bitfield(msr, 31, 0));␊
␉␉␉␉if (bitfield(msr, 16, 16)) {␊
␉␉␉␉␉flex_ratio = bitfield(msr, 14, 8);␊
␉␉␉␉␉flex_ratio = bitfield(msr, 15, 8);␊
␉␉␉␉␉/* bcc9: at least on the gigabyte h67ma-ud2h,␊
␉␉␉␉␉ where the cpu multipler can't be changed to␊
␉␉␉␉␉ allow overclocking, the flex_ratio msr has unexpected (to OSX)␊
trunk/i386/libsaio/platform.h
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#define CPU_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊
#define CPU_MODEL_FIELDS␉␉0x1E␉␉␉// Lynnfield, Clarksfield, Jasper Forest␊
#define CPU_MODEL_DALES␉␉␉0x1F␉␉␉// Havendale, Auburndale␊
#define CPU_MODEL_CLARKDALE␉␉0x25␉␉␉// Clarkdale, Arrandale␊
#define CPU_MODEL_DALES_32NM␉␉0x25␉␉␉// Clarkdale, Arrandale␊
#define CPU_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊
#define CPU_MODEL_LINCROFT␉␉0x27␉␉␉// ␊
#define CPU_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊
#define CPU_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊
#define CPU_MODEL_SANDYBRIDGE_XEON␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
#define CPU_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊
#define CPU_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Beckton␊
#define CPU_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX␊
#define CPU_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview␊
#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
#define CPU_MODEL_HASWELL_DT␉␉0x3C␉␉␉// Haswell DT␊
#define CPU_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊
#define CPU_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
#define CPU_MODEL_HASWELL_MB␉␉0x3F␉␉␉// Haswell MB␊
//#define CPU_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
␉} CPU;␊
␉␊
␊
␉struct RAM {␊
␉␉uint64_t␉␉Frequency;␉␉␉␉// Ram Frequency␊
␉␉uint32_t␉␉Divider;␉␉␉␉// Memory divider␊
␉␉uint8_t␉␉␉Type;␉␉␉␉␉// Standard SMBIOS v2.5 Memory Type␊
␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉// Information about each slot␊
␉} RAM;␊
␉␊
␊
␉struct DMI {␊
␉␉int␉␉␉MaxMemorySlots;␉␉␉␉// number of memory slots populated by SMBIOS␊
␉␉int␉␉␉CntMemorySlots;␉␉␉␉// number of memory slots counted␊
␉␉int␉␉␉MemoryModules;␉␉␉␉// number of memory modules installed␊
␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉␉// Information and SPD mapping for each slot␊
␉} DMI;␊
␉␊
␊
␉uint8_t␉␉␉␉Type; // System Type: 1=Desktop, 2=Portable... according ACPI2.0 (FACP: PM_Profile)␊
␉uint8_t␉␉␉␉*UUID;␊
} PlatformInfo_t;␊
trunk/i386/libsaio/cpu.h
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#define CPUID_MODEL_XEON_MP␉␉29 // 0x1D MP 7400␊
#define CPUID_MODEL_FIELDS␉␉30 // 0x1E Intel Core i5, i7, Xeon X34xx LGA1156 (45nm),(Clarksfiled, Lynnfield, Jasper Forest)␊
#define CPUID_MODEL_DALES␉␉31 // 0x1F Havendale, Auburndale␊
#define CPUID_MODEL_CLARKDALE␉␉37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale)␊
#define CPUID_MODEL_DALES_32NM␉␉37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale)␊
#define CPUID_MODEL_ATOM_SAN␉␉38 // 0x26␊
#define CPUID_MODEL_LINCROFT␉␉39 // 0x27 Intel Atom (45nm) Z6xx (single core)␊
#define CPUID_MODEL_SANDYBRIDGE␉␉42 // 0x2A Intel Core i3, i5, i7 LGA1155 (32nm)␊
#define CPUID_MODEL_WESTMERE␉␉44 // 0x2C Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
#define CPUID_MODEL_SANDYBRIDGE_XEON␉45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP␊
#define CPUID_MODEL_JAKETOWN 45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP␊
#define CPUID_MODEL_NEHALEM_EX␉␉46 // 0x2E Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
#define CPUID_MODEL_WESTMERE_EX␉␉47 // 0x2F Intel Xeon E7␊
#define CPUID_MODEL_ATOM_2000␉␉54 // 0x36 Intel Atom (32nm) Cedarview␊
#define CPUID_MODEL_IVYBRIDGE␉␉58 // 0x3A Intel Core i5, i7 LGA1155 (22nm)␊
#define CPUID_MODEL_HASWELL_DT␉␉60 // 0x3C␊
#define CPUID_MODEL_HASWELL␉␉60 // 0x3C Desktop version␊
#define CPUID_MODEL_IVYBRIDGE_XEON␉62 // 0x3E␊
#define CPUID_MODEL_HASWELL_MB␉␉63 // 0x3F␊
#define CPUID_MODEL_HASWELL_MB␉␉63 // 0x3F Mobile/Laptop version␊
//#define CPUID_MODEL_HASWELL_H␉␉?? // 0x??␊
#define CPUID_MODEL_HASWELL_ULT␉␉69 // 0x45␊
#define CPUID_MODEL_HASWELL_ULX␉␉70 // 0x46␊
trunk/i386/libsaio/smbios.c
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␊
␉{kSMBTypeMemoryDevice,␉kSMBString,␉getFieldOffset(SMBMemoryDevice, assetTag),␉␉NULL,␉NULL,␉NULL},␊
␊
␉{kSMBTypeMemoryDevice,␉kSMBWord,␉getFieldOffset(SMBMemoryDevice, errorHandle), NULL, getSMBMemoryDeviceMemoryErrorHandle, NULL},␊
␊
␉{kSMBTypeMemoryDevice,␉kSMBString,␉getFieldOffset(SMBMemoryDevice, partNumber),␉kSMBMemoryDevicePartNumberKey,␉␉␊
␉␉getSMBMemoryDevicePartNumber,␉NULL},␊
␊
␉␉␉␉␉␉{␊
␉␉␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacNehalemBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacNehalem;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.family␉␉= kDefaultiMacFamily;␊
␉␉␉␉␉␉␉␉break;␊
␊
␉␉␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␉␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultiMacSandyBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultiMacSandy;␊
␊
␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉// Intel Xeon E7␊
␉␉␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.version␉␉␉= kDefaultMacProWestmereBIOSVersion;␊
␉␉␉␉␉␉␉␉defaultBIOSInfo.releaseDate␉␉= kDefaulMacProWestmereBIOSReleaseDate;␊
␉␉␉␉␉␉␉␉defaultSystemInfo.productName␉= kDefaultMacProWestmere;␊
␉␉␉{␊
␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPU_MODEL_HASWELL_ULX:␊
␊
␉␉␉␉␉break;␊
␊
␉␉␉␉default:␊
trunk/i386/libsaio/smbios_decode.c
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......
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␉if (minorVersion < 3 || structHeader->header.length < 27)␊
␉␉return;␊
␉DBG("\tmemorySpeed: %dMHz\n", structHeader->memorySpeed);␊
␉DBG("\terrorHandle: %x\n", structHeader->errorHandle);␊
␉DBG("\tmanufacturer: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->manufacturer));␊
␉DBG("\tserialNumber: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->serialNumber));␊
␉DBG("\tassetTag: %s\n", getSMBStringForField((SMBStructHeader *)structHeader, structHeader->assetTag));␊
␉␉for (; ((uint16_t *)ptr)[0] != 0; ptr++);␊
␊
␉␉if (((uint16_t *)ptr)[0] == 0)␊
␉␉{␊
␉␉␉ptr += 2;␊
␉␉}␊
␊
␉␉structHeader = (SMBStructHeader *)ptr;␊
␉}␊
trunk/i386/libsaio/smbios_getters.c
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......
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......
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......
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......
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......
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......
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......
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␉␉␉␉switch (Platform.CPU.Model)␊
␉␉␉␉{␊
␉␉␉␉␉␉// set external clock to 0 for SANDY␊
␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's. ␊
␉␉␉␉␉␉// removes FSB info from system profiler as on real mac's.␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULX:␊
␊
␉␉␉␉␉␉value->word = 0;␊
␉␉␉␉␉␉break;␊
␉␉␉␉␉default:␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␉␉// Intel Core i5, i7, Xeon X34xx LGA1156 (45nm)␊
␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␉// Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_NEHALEM:␉␉␉␉// Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␉␉␉// Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␉␉␉// Intel Xeon E7␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␉␉␉// Intel Core i7, Xeon E5-xxxx LGA2011 (32nm)␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Xeon(R)"))␊
␉␉␉␉␉␉␉value->word = 0x0501;␉␉␉// Xeon ␊
␉␉␉␉␉␉else␊
␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (32nm)␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␉␉␉// Intel Core i3, i5, i7 LGA1155 (22nm)␊
␉␉␉␉␉case CPU_MODEL_CLARKDALE:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␉␉␉// Intel Core i3, i5 LGA1156 (32nm)␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULX:␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3"))␊
␉␉␉␉␉␉␉value->word = 0x0901;␉␉␉// Core i3␊
␉␉␉␉␉␉else␊
//␉return true;␊
}␊
␊
bool getSMBMemoryDeviceMemoryErrorHandle(returnType *value)␊
{␊
␉value->word = 0xFFFF;␊
␉return true;␊
}␊
␊
bool getSMBMemoryDeviceMemorySpeed(returnType *value)␊
{␊
␉static int idx = -1;␊
␉}␊
␊
␉if (!bootInfo->memDetect)␊
␉{␊
␉␉return false;␊
␉}␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
}␊
␉}␊
␊
␉if (!bootInfo->memDetect)␊
␉{␊
␉␉return false;␊
␉}␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
}␊
␉}␊
␊
␉if (!bootInfo->memDetect)␊
␉{␊
␉␉return false;␊
␉}␊
␉value->string = NOT_AVAILABLE;␊
␉return true;␊
}␊
trunk/i386/boot2/drivers.c
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␉required = XMLGetProperty(moduleDict, kPropOSBundleRequired);␊
␊
␉if ( (required != NULL) && (required->type == kTagTypeString) && !strcmp(required->string, "Safe Boot"))␊
␉//if ( (required == 0) || (required->type != kTagTypeString) || !strcmp(required->string, "Safe Boot"))␊
␉{␊
␉␉XMLFreeTag(moduleDict);␊
␉␉return -2;␊
trunk/i386/boot2/modules.c
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......
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␉}␊
␉␊
␉unsigned int moduleSize = file_size(fh);␊
␊
␊
if(moduleSize == 0)␊
{␊
DBG("WARNING: The module %s has a file size of %d, the module will not be loaded.\n", modString, moduleSize);␊
start_function();␊
}␊
␊
#endif
#endif␊
trunk/i386/modules/AcpiCodec/acpi_codec.c
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......
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......
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......
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␊
static bool is_jaketown(void)␊
{␊
return Platform.CPU.Model == CPU_MODEL_SANDYBRIDGE_XEON;␊
return Platform.CPU.Model == CPU_MODEL_JAKETOWN;␊
}␊
␊
static U32 get_bclk(void)␊
␉␉␉␉} ␊
␉␉␉␉case CPU_MODEL_FIELDS:␊
␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉case CPU_MODEL_CLARKDALE:␊
␉␉␉␉case CPU_MODEL_DALES_32NM:␊
␉␉␉␉case CPU_MODEL_NEHALEM: ␊
␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␊
␉␉␉␉{␉␉␊
␉␉␉␉␉␊
␉␉␉␉␉cpu->core_c1_supported = ((sub_Cstates >> 4) & 0xf) ? 1 : 0;␊
␉␉␉␉␉} ␊
␉␉␉␉␉case CPU_MODEL_FIELDS:␊
␉␉␉␉␉case CPU_MODEL_DALES:␊
␉␉␉␉␉case CPU_MODEL_CLARKDALE:␊
␉␉␉␉␉case CPU_MODEL_DALES_32NM:␊
␉␉␉␉␉case CPU_MODEL_NEHALEM: ␊
␉␉␉␉␉case CPU_MODEL_NEHALEM_EX:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE:␊
␉␉␉␉␉case CPU_MODEL_WESTMERE_EX:␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_SANDYBRIDGE_XEON:␊
␉␉␉␉␉case CPU_MODEL_JAKETOWN:␊
␉␉␉␉␉{␉␉␊
␉␉␉␉␉␉␊
␉␉␉␉␉␉maximum.Control = rdmsr64(MSR_IA32_PERF_STATUS) & 0xff; // Seems it always contains maximum multiplier value (with turbo, that's we need)...␊
␉{ ␊
␊
␉␉TagPtr CstateTag = NULL;␊
U32 entry_count = 0;␊
␉␉U32 entry_count = 0;␊
␊
if (bootInfo->chameleonConfig.dictionary) ␊
{␊
CstateTag = XMLCastDict(XMLGetProperty(bootInfo->chameleonConfig.dictionary, (const char*)"C-States"));␊
␉␉CstateTag = XMLCastDict(XMLGetProperty(bootInfo->chameleonConfig.dictionary, (const char*)"C-States"));␊
} ␊
␊
␉␉if (CstateTag)␊
trunk/CHANGES
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- Fix issue booting x86 after rev.2175 (Credits to Mario, Alex and Leon).␊
- ErmaC : Add new CPU Model IDs␊
- Add boot support to 10.9 (thx old napalm)␊
- ErmaC : Update gui Icons OS detection␊
- Update default theme Icon set (thx BlackOsx)␊
- Add Linux GPT Partition Label␊
- Fix menuBVR initialization problem␊
- 2252: revert define processors name to match with xnu kernel name ␊
- 2252: Merge from Enoch the Geoff Seeley patch http://forge.voodooprojects.org/p/chameleon/issues/59/␊
- 2251: bdmesg can show Chameleon and Clover boot logs␊
- 2248: Infos about lack for 32/64 bit (Credits to Pike R. Alpha)␊
- 2248: Fix issue booting x86 after rev.2175 (Credits to Bronxteck, Alex Burma and Leon).␊
- 2245: ErmaC : Add new CPU Model IDs␊
- 2245: Add boot support to 10.9 (thx old napalm)␊
- 2245: ErmaC : Update gui Icons OS detection␊
- 2245: Update default theme Icon set (thx BlackOsx)␊
- 2243: Add Linux GPT Partition Label␊
- 2234: Fix menuBVR initialization problem␊
- Implement ErmaC's HDAEnabler.dylib module␊
- Fix Bug in the loop that look for an ATI card. Credits to Jief Luce␊
- Fix extension without kPropOSBundleRequired property weren't loaded. Credits to Jief Luce␊

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Revision: 2253