Chameleon

Chameleon Commit Details

Date:2014-01-27 15:57:45 (10 years 2 months ago)
Author:ErmaC
Commit:2348
Parents: 2347
Message:match CPU name with xnu source
Changes:
M/trunk/i386/libsaio/cpu.c
M/trunk/i386/libsaio/platform.h
M/trunk/i386/libsaio/smbios_getters.c
M/trunk/i386/libsaio/cpu.h
M/trunk/i386/libsaio/smbios.c

File differences

trunk/i386/libsaio/cpu.c
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␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE_XEON␉||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_IVYBRIDGE ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_MB ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_SVR ||␊
␉␉␉␉␉␉␉␉␉␉ //p->CPU.Model == CPU_MODEL_HASWELL_H ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_HASWELL_ULT ||␊
␉␉␉␉␉␉␉␉␉␉ p->CPU.Model == CPU_MODEL_CRYSTALWELL ))␊
trunk/i386/libsaio/platform.h
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#define CPU_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊
#define CPU_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT␊
#define CPU_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊
#define CPU_MODEL_HASWELL_MB␉␉0x3F␉␉␉// Haswell MB␊
#define CPU_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell MB␊
//#define CPU_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊
#define CPU_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT␊
#define CPU_MODEL_CRYSTALWELL␉␉0x46␉␉␉// Haswell ULX␊
␉␉uint32_t␉␉Vendor;␉␉␉␉␉// Vendor␊
␉␉uint32_t␉␉Signature;␉␉␉␉// Processor Signature␊
␉␉uint32_t␉␉Stepping;␉␉␉␉// Stepping␊
␉␉//uint32_t␉␉Type;␉␉␉␉␉// Type␊
␉␉//uint16_t␉␉Type;␉␉␉␉␉// Type␊
␉␉uint32_t␉␉Model;␉␉␉␉␉// Model␊
␉␉uint32_t␉␉ExtModel;␉␉␉␉// Extended Model␊
␉␉uint32_t␉␉Family;␉␉␉␉␉// Family␊
␉␉uint32_t␉␉NoCores;␉␉␉␉// No Cores per Package␊
␉␉uint32_t␉␉NoThreads;␉␉␉␉// Threads per Package␊
␉␉uint8_t␉␉␉MaxCoef;␉␉␉␉// Max Multiplier␊
␉␉uint8_t␉␉␉MaxDiv;␊
␉␉uint8_t␉␉␉MaxDiv;␉␉␉␉␉// Min Multiplier␊
␉␉uint8_t␉␉␉CurrCoef;␉␉␉␉// Current Multiplier␊
␉␉uint8_t␉␉␉CurrDiv;␊
␉␉uint64_t␉␉TSCFrequency;␉␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉␉// CPU Frequency Hz␊
␉␉uint64_t␉␉TSCFrequency;␉␉␉␉// TSC Frequency Hz␊
␉␉uint64_t␉␉FSBFrequency;␉␉␉␉// FSB Frequency Hz␊
␉␉uint64_t␉␉CPUFrequency;␉␉␉␉// CPU Frequency Hz␊
␉␉uint32_t␉␉MaxRatio;␉␉␉␉// Max Bus Ratio␊
␉␉uint32_t␉␉MinRatio;␉␉␉␉// Min Bus Ratio␊
␉␉char␉␉␉BrandString[48];␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊
␉␉char␉␉␉BrandString[48];␉␉␉// 48 Byte Branding String␊
␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉␉␉// CPUID 0..4, 80..81 Raw Values␊
␉} CPU;␊
␊
␉struct RAM {␊
trunk/i386/libsaio/cpu.h
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␊
#define␉MSR_IA32_PERF_STATUS␉0x00000198␊
#define MSR_IA32_PERF_CONTROL␉0x199␊
#define MSR_IA32_EXT_CONFIG␉␉0x00EE␊
#define MSR_FLEX_RATIO␉␉␉0x194␊
#define MSR_IA32_EXT_CONFIG␉0x00EE␊
#define MSR_FLEX_RATIO␉␉0x194␊
#define MSR_TURBO_RATIO_LIMIT␉0x1AD␊
#define␉MSR_PLATFORM_INFO␉␉0xCE␊
#define␉MSR_PLATFORM_INFO␉0xCE␊
#define MSR_CORE_THREAD_COUNT␉0x35␉␉␉// Undocumented␊
#define MSR_IA32_PLATFORM_ID␉0x17␊
␊
#define CALIBRATE_TIME_MSEC␉30␉␉/* 30 msecs */␊
#define CALIBRATE_LATCH␉␉((CLKNUM * CALIBRATE_TIME_MSEC + 1000/2)/1000)␊
␊
// CPUID Values␊
/*␊
#define CPUID_MODEL_PRESCOTT␉␉3 // 0x03 Celeron D, Pentium 4 (90nm)␊
#define CPUID_MODEL_NOCONA␉␉4 // 0x04 Xeon Nocona, Irwindale (90nm)␊
#define CPUID_MODEL_PRESLER␉␉6 // 0x06 Pentium 4, Pentium D (65nm)␊
#define CPUID_MODEL_PENTIUM_M␉␉9 // 0x09␊
#define CPUID_MODEL_DOTHAN␉␉13 // 0x0D Dothan␊
#define CPUID_MODEL_YONAH␉␉14 // 0x0E Intel Mobile Core Solo, Duo␊
#define CPUID_MODEL_MEROM␉␉15 // 0x0F Intel Mobile Core 2 Solo, Duo, Xeon 30xx, Xeon 51xx, Xeon X53xx, Xeon E53xx, Xeon X32xx␊
#define CPUID_MODEL_CONROE␉␉15 // 0x0F␊
#define CPUID_MODEL_CELERON␉␉22 // 0x16␊
#define CPUID_MODEL_PENRYN␉␉23 // 0x17 Intel Core 2 Solo, Duo, Quad, Extreme, Xeon X54xx, Xeon X33xx␊
#define CPUID_MODEL_WOLFDALE␉␉23 // 0x17␊
#define CPUID_MODEL_NEHALEM␉␉26 // 0x1A Intel Core i7, Xeon W35xx, Xeon X55xx, Xeon E55xx LGA1366 (45nm)␊
#define CPUID_MODEL_ATOM␉␉28 // 0x1C Intel Atom (45nm) Pineview, Silverthorne␊
#define CPUID_MODEL_XEON_MP␉␉29 // 0x1D MP 7400␊
#define CPUID_MODEL_FIELDS␉␉30 // 0x1E Intel Core i5, i7, Xeon X34xx LGA1156 (45nm),(Clarksfiled, Lynnfield, Jasper Forest)␊
#define CPUID_MODEL_DALES␉␉31 // 0x1F Havendale, Auburndale␊
#define CPUID_MODEL_DALES_32NM␉␉37 // 0x25 Intel Core i3, i5 LGA1156 (32nm), (Arrandale, Clarksdale)␊
#define CPUID_MODEL_ATOM_SAN␉␉38 // 0x26␊
#define CPUID_MODEL_LINCROFT␉␉39 // 0x27 Intel Atom (45nm) Z6xx (single core)␊
#define CPUID_MODEL_SANDYBRIDGE␉␉42 // 0x2A Intel Core i3, i5, i7 LGA1155 (32nm)␊
#define CPUID_MODEL_WESTMERE␉␉44 // 0x2C Intel Core i7, Xeon X56xx, Xeon E56xx, Xeon W36xx LGA1366 (32nm) 6 Core␊
#define CPUID_MODEL_JAKETOWN 45 // 0x2D Intel Xeon E5 LGA2011 (32nm), SandyBridge-E, SandyBridge-EN, SandyBridge-EP␊
#define CPUID_MODEL_NEHALEM_EX␉␉46 // 0x2E Intel Xeon X75xx, Xeon X65xx, Xeon E75xx, Xeon E65x␊
#define CPUID_MODEL_WESTMERE_EX␉␉47 // 0x2F Intel Xeon E7␊
#define CPUID_MODEL_ATOM_2000␉␉54 // 0x36 Intel Atom (32nm) Cedarview␊
#define CPUID_MODEL_IVYBRIDGE␉␉58 // 0x3A Intel Core i5, i7 LGA1155 (22nm)␊
#define CPUID_MODEL_HASWELL␉␉60 // 0x3C Desktop version␊
#define CPUID_MODEL_IVYBRIDGE_XEON␉62 // 0x3E␊
#define CPUID_MODEL_HASWELL_MB␉␉63 // 0x3F Mobile/Laptop version␊
//#define CPUID_MODEL_HASWELL_H␉␉?? // 0x??␊
#define CPUID_MODEL_HASWELL_ULT␉␉69 // 0x45␊
#define CPUID_MODEL_CRYSTALWELL␉␉70 // 0x46␊
*/␊
/* HASWELL-DT HASWELL-MB HASWELL-H HASWELL-ULT HASWELL ULX*/␊
␊
//BROADWELL-ROCKWELL␊
␊
static inline uint64_t rdtsc64(void)␊
{␊
␉uint64_t ret;␊
trunk/i386/libsaio/smbios.c
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␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉case CPU_MODEL_JAKETOWN:␉// Intel Core i7, Xeon E5 LGA2011 (32nm)␊
␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␊
trunk/i386/libsaio/smbios_getters.c
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␉␉␉␉␉case CPU_MODEL_IVYBRIDGE_XEON:␊
␉␉␉␉␉case CPU_MODEL_IVYBRIDGE:␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␊
␊
␉␉␉␉␉␉return true;␊
␊
␉␉␉␉␉case CPU_MODEL_HASWELL:␉␉␉␉// 0x3C -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_MB:␉␉␉// 0x3F -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_SVR:␉␉␉// 0x3F -␊
␉␉␉␉␉case CPU_MODEL_HASWELL_ULT:␉␉␉// 0x45 -␊
␉␉␉␉␉case CPU_MODEL_CRYSTALWELL:␉␉␉// 0x46␊
␉␉␉␉␉␉if (strstr(Platform.CPU.BrandString, "Core(TM) i3")) {␊

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Revision: 2348