Chameleon Commit Details - 528 - Chameleon open source boot loader project.

Date:

2010-09-14 14:58:32 (13 years 7 months ago)

Author:

Azimutz

Commit:

528

Parents:

527

Message:

Trunk rev 517.

Changes:

M	/branches/azimutz/Chazi/i386/modules/Memory/dram_controllers.c
M	/branches/azimutz/CleanCut/i386/libsaio/dram_controllers.c

File differences

-469
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+␉␊
␉// RAS-To-CAS (tRCD)␊
␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
␉␊
␊
␉// RAS Precharge (tRP)␊
␉Platform.RAM.CAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
␉␊
␉// RAS Active to precharge (tRAS)␊
␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F;␊
␉␊
␉// Single , Dual or Triple Channels␊
␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊
 ␉␊
 ␉// RAS-To-CAS (tRCD)␊
 ␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
-␉␊
+␊
 ␉// RAS Precharge (tRP)␊
-␉Platform.RAM.CAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
+␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
 ␉␊
 ␉// RAS Active to precharge (tRAS)␊
-␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
+␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F;␊
 ␉␊
 ␉// Single , Dual or Triple Channels␊
 ␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊

-471
472 472
473 473
474 
474
475 475
476 476
477 
477
478 478
479 479
480 480
+␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
␉␊
␉// RAS Precharge (tRP)␊
␉Platform.RAM.CAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
␉␊
␉// RAS Active to precharge (tRAS)␊
␉Platform.RAM.RAS = mc_channel_bank_timing & 0xF;␊
␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F;␊
␉␊
␉// Single , Dual or Triple Channels␊
␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊
 ␉Platform.RAM.TRC = (mc_channel_bank_timing >> 9) & 0xF; ␊
 ␉␊
 ␉// RAS Precharge (tRP)␊
-␉Platform.RAM.CAS = (mc_channel_bank_timing >> 4) & 0x1F; ␊
+␉Platform.RAM.TRP = mc_channel_bank_timing & 0xF;␊
 ␉␊
 ␉// RAS Active to precharge (tRAS)␊
-␉Platform.RAM.RAS = mc_channel_bank_timing & 0xF;␊
+␉Platform.RAM.RAS = (mc_channel_bank_timing >> 4) & 0x1F;␊
 ␉␊
 ␉// Single , Dual or Triple Channels␊
 ␉if (mc_control == 1 || mc_control == 2 || mc_control == 4 )␊