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Root/branches/meklort/i386/libsaio/resolution.c

Source at commit 148 created 8 years 2 months ago.
By meklort, 915resolution code
1/*
2 * resolution.h
3 *
4 *NOTE: I don't beleive this code is production ready / should be in trunk
5 * Atleast, not in it's current state.
6 *
7 * Created by Evan Lojewski on 3/4/10.
8 * Copyright 2009. All rights reserved.
9 *
10 */
11#ifndef _RESOLUTION_H_
12#define _RESOLUTION_H_
13
14#include "libsaio.h"
15#include "edid.h"
16#include "resolution.h"
17
18
19void patchVideoBios()
20{
21UInt32 x = 0, y = 0, bp = 0;
22
23getResolution(&x, &y, &bp);
24
25
26if (x != 0 &&
27y != 0 &&
28bp != 0)
29{
30vbios_map * map;
31
32map = open_vbios(CT_UNKWN);
33if(map)
34{
35unlock_vbios(map);
36
37set_mode(map, x, y, bp, 0, 0);
38
39relock_vbios(map);
40
41close_vbios(map);
42}
43}
44
45}
46
47
48/* Copied from 915 resolution created by steve tomljenovic
49 *
50 * This code is based on the techniques used in :
51 *
52 * - 855patch. Many thanks to Christian Zietz (czietz gmx net)
53 * for demonstrating how to shadow the VBIOS into system RAM
54 * and then modify it.
55 *
56 * - 1280patch by Andrew Tipton (andrewtipton null li).
57 *
58 * - 855resolution by Alain Poirier
59 *
60 * This source code is into the public domain.
61 */
62
63/**
64 **
65 **/
66
67#define CONFIG_MECH_ONE_ADDR0xCF8
68#define CONFIG_MECH_ONE_DATA0xCFC
69
70int freqs[] = { 60, 75, 85 };
71
72UInt32 get_chipset_id(void)
73{
74outl(CONFIG_MECH_ONE_ADDR, 0x80000000);
75return inl(CONFIG_MECH_ONE_DATA);
76}
77
78chipset_type get_chipset(UInt32 id)
79{
80chipset_type type;
81
82switch (id) {
83case 0x35758086:
84type = CT_830;
85break;
86
87case 0x25608086:
88type = CT_845G;
89break;
90
91case 0x35808086:
92type = CT_855GM;
93break;
94
95case 0x25708086:
96type = CT_865G;
97break;
98
99case 0x25808086:
100type = CT_915G;
101break;
102
103case 0x25908086:
104type = CT_915GM;
105break;
106
107case 0x27708086:
108type = CT_945G;
109break;
110
111case 0x27a08086:
112type = CT_945GM;
113break;
114
115case 0x27ac8086:
116type = CT_945GME;
117break;
118
119case 0x29708086:
120type = CT_946GZ;
121break;
122
123case 0x27748086:
124type = CT_955X;
125break;
126
127case 0x277c8086:
128type = CT_975X;
129break;
130
131case 0x29a08086:
132type = CT_G965;
133break;
134
135case 0x29908086:
136type = CT_Q965;
137break;
138
139case 0x81008086:
140type = CT_500;
141break;
142
143case 0x2e108086:
144case 0X2e908086:
145type = CT_B43;
146break;
147
148case 0x2e208086:
149type = CT_P45;
150break;
151
152case 0x2e308086:
153type = CT_G41;
154break;
155
156case 0x29c08086:
157type = CT_G31;
158break;
159
160case 0x29208086:
161type = CT_G45;
162break;
163
164case 0xA0108086:
165type = CT_3150;
166break;
167
168case 0x2a008086:
169type = CT_965GM;
170break;
171
172case 0x29e08086:
173type = CT_X48;
174break;
175
176case 0x2a408086:
177type = CT_GM45;
178break;
179
180
181default:
182if((id & 0x0000FFFF) == 0x00008086) // Intel chipset
183{
184//printf("Unknown chipset 0x%llX, please email id to meklort@gmail.com", id);
185//getc();
186type = CT_UNKWN_INTEL;
187
188}
189type = CT_UNKWN;
190break;
191}
192return type;
193}
194
195vbios_resolution_type1 * map_type1_resolution(vbios_map * map, UInt16 res)
196{
197vbios_resolution_type1 * ptr = ((vbios_resolution_type1*)(map->bios_ptr + res));
198return ptr;
199}
200
201vbios_resolution_type2 * map_type2_resolution(vbios_map * map, UInt16 res)
202{
203vbios_resolution_type2 * ptr = ((vbios_resolution_type2*)(map->bios_ptr + res));
204return ptr;
205}
206
207vbios_resolution_type3 * map_type3_resolution(vbios_map * map, UInt16 res)
208{
209vbios_resolution_type3 * ptr = ((vbios_resolution_type3*)(map->bios_ptr + res));
210return ptr;
211}
212
213char detect_bios_type(vbios_map * map, char modeline, int entry_size)
214{
215UInt32 i;
216UInt16 r1, r2;
217
218r1 = r2 = 32000;
219
220for (i=0; i < map->mode_table_size; i++)
221{
222if (map->mode_table[i].resolution <= r1)
223{
224r1 = map->mode_table[i].resolution;
225}
226else
227{
228if (map->mode_table[i].resolution <= r2)
229{
230r2 = map->mode_table[i].resolution;
231}
232}
233
234/*printf("r1 = %d r2 = %d\n", r1, r2);*/
235}
236
237return (r2-r1-6) % entry_size == 0;
238}
239
240void close_vbios(vbios_map * map);
241
242char detect_ati_bios_type(vbios_map * map)
243{
244return map->mode_table_size % sizeof(ATOM_MODE_TIMING) == 0;
245}
246
247
248vbios_map * open_vbios(chipset_type forced_chipset)
249{
250UInt32 z;
251vbios_map * map = malloc(sizeof(vbios_map));
252for(z=0; z<sizeof(vbios_map); z++) ((char*)map)[z]=0;
253/*
254 * Determine chipset
255 */
256
257if (forced_chipset == CT_UNKWN)
258{
259map->chipset_id = get_chipset_id();
260map->chipset = get_chipset(map->chipset_id);
261}
262else if (forced_chipset != CT_UNKWN)
263{
264map->chipset = forced_chipset;
265}
266
267
268if (map->chipset == CT_UNKWN)
269{
270//verbose("Unknown chipset type.\n");
271//verbose("915resolution only works with Intel 800/900 series graphic chipsets.\n");
272//verbose("Chipset Id: %x\n", map->chipset_id);
273close_vbios(map);
274return 0;
275}
276
277
278/*
279 * Map the video bios to memory
280 */
281map->bios_ptr=(char*)VBIOS_START;
282
283/*
284 * check if we have ATI Radeon
285 */
286map->ati_tables.base = map->bios_ptr;
287map->ati_tables.AtomRomHeader = (ATOM_ROM_HEADER *) (map->bios_ptr + *(unsigned short *) (map->bios_ptr + OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER));
288if (strcmp ((char *) map->ati_tables.AtomRomHeader->uaFirmWareSignature, "ATOM") == 0)
289{
290// ATI Radeon Card
291map->bios = BT_ATI_1;
292
293map->ati_tables.MasterDataTables = (unsigned short *) &((ATOM_MASTER_DATA_TABLE *) (map->bios_ptr + map->ati_tables.AtomRomHeader->usMasterDataTableOffset))->ListOfDataTables;
294unsigned short std_vesa_offset = (unsigned short) ((ATOM_MASTER_LIST_OF_DATA_TABLES *)map->ati_tables.MasterDataTables)->StandardVESA_Timing;
295ATOM_STANDARD_VESA_TIMING * std_vesa = (ATOM_STANDARD_VESA_TIMING *) (map->bios_ptr + std_vesa_offset);
296
297map->ati_mode_table = (char *) &std_vesa->aModeTimings;
298if (map->ati_mode_table == 0)
299{
300printf("Unable to locate the mode table.\n");
301printf("Please run the program 'dump_bios' as root and\n");
302printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");
303printf("Chipset: %d\n", map->chipset);
304close_vbios(map);
305return 0;
306}
307map->mode_table_size = std_vesa->sHeader.usStructureSize - sizeof(ATOM_COMMON_TABLE_HEADER);
308
309if (!detect_ati_bios_type(map)) map->bios = BT_ATI_2;
310
311}
312else {
313
314/*
315 * check if we have NVIDIA
316 */
317
318int i = 0;
319while (i < 512)
320{ // we don't need to look through the whole bios, just the firs 512 bytes
321if ((map->bios_ptr[i] == 'N')
322&& (map->bios_ptr[i+1] == 'V')
323&& (map->bios_ptr[i+2] == 'I')
324&& (map->bios_ptr[i+3] == 'D'))
325{
326map->bios = BT_NVDA;
327unsigned short nv_data_table_offset = 0;
328unsigned short * nv_data_table;
329NV_VESA_TABLE * std_vesa;
330
331int i = 0;
332
333while (i < 0x300)
334{ //We don't need to look for the table in the whole bios, the 768 first bytes only
335if ((map->bios_ptr[i] == 0x44)
336&& (map->bios_ptr[i+1] == 0x01)
337&& (map->bios_ptr[i+2] == 0x04)
338&& (map->bios_ptr[i+3] == 0x00))
339{
340nv_data_table_offset = (unsigned short) (map->bios_ptr[i+4] | (map->bios_ptr[i+5] << 8));
341break;
342}
343i++;
344}
345
346nv_data_table = (unsigned short *) (map->bios_ptr + (nv_data_table_offset + OFFSET_TO_VESA_TABLE_INDEX));
347std_vesa = (NV_VESA_TABLE *) (map->bios_ptr + *nv_data_table);
348
349map->nv_mode_table = (char *) std_vesa->sModelines;
350if (map->nv_mode_table == 0)
351{
352printf("Unable to locate the mode table.\n");
353printf("Please run the program 'dump_bios' as root and\n");
354printf("email the file 'vbios.dmp' to stomljen@yahoo.com.\n");
355printf("Chipset: %s\n", map->chipset);
356close_vbios(map);
357return 0;
358}
359map->mode_table_size = std_vesa->sHeader.usTable_Size;
360
361break;
362}
363i++;
364}
365}
366
367
368/*
369 * check if we have Intel
370 */
371
372/*if (map->chipset == CT_UNKWN && memmem(map->bios_ptr, VBIOS_SIZE, INTEL_SIGNATURE, strlen(INTEL_SIGNATURE))) {
373 printf( "Intel chipset detected. However, 915resolution was unable to determine the chipset type.\n");
374
375 printf("Chipset Id: %x\n", map->chipset_id);
376
377 printf("Please report this problem to stomljen@yahoo.com\n");
378
379 close_vbios(map);
380 return 0;
381 }*/
382
383/*
384 * check for others
385 */
386
387
388
389/*
390 * Figure out where the mode table is
391 */
392if ((map->bios != BT_ATI_1) && (map->bios != BT_NVDA))
393{
394char* p = map->bios_ptr + 16;
395char* limit = map->bios_ptr + VBIOS_SIZE - (3 * sizeof(vbios_mode));
396
397while (p < limit && map->mode_table == 0)
398{
399vbios_mode * mode_ptr = (vbios_mode *) p;
400
401if (((mode_ptr[0].mode & 0xf0) == 0x30) && ((mode_ptr[1].mode & 0xf0) == 0x30) &&
402((mode_ptr[2].mode & 0xf0) == 0x30) && ((mode_ptr[3].mode & 0xf0) == 0x30))
403{
404map->mode_table = mode_ptr;
405}
406
407p++;
408}
409
410if (map->mode_table == 0)
411{
412close_vbios(map);
413return 0;
414}
415}
416
417
418/*
419 * Determine size of mode table
420 */
421if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))
422{
423vbios_mode * mode_ptr = map->mode_table;
424
425while (mode_ptr->mode != 0xff)
426{
427map->mode_table_size++;
428mode_ptr++;
429}
430}
431
432/*
433 * Figure out what type of bios we have
434 * order of detection is important
435 */
436if ((map->bios != BT_ATI_1) && (map->bios != BT_ATI_2) && (map->bios != BT_NVDA))
437{
438if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type3)))
439{
440map->bios = BT_3;
441}
442else if (detect_bios_type(map, TRUE, sizeof(vbios_modeline_type2)))
443{
444map->bios = BT_2;
445}
446else if (detect_bios_type(map, FALSE, sizeof(vbios_resolution_type1)))
447{
448map->bios = BT_1;
449}
450else {
451return 0;
452}
453}
454
455return map;
456}
457
458void close_vbios(vbios_map * map)
459{
460free(map);
461}
462
463void unlock_vbios(vbios_map * map)
464{
465
466map->unlocked = TRUE;
467
468switch (map->chipset) {
469case CT_UNKWN:
470break;
471case CT_830:
472case CT_855GM:
473outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);
474map->b1 = inb(CONFIG_MECH_ONE_DATA + 2);
475
476outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);
477outb(CONFIG_MECH_ONE_DATA + 2, 0x33);
478break;
479case CT_845G:
480case CT_865G:
481case CT_915G:
482case CT_915GM:
483case CT_945G:
484case CT_945GM:
485case CT_945GME:
486case CT_946GZ:
487case CT_G965:
488case CT_Q965:
489case CT_965GM:
490case CT_975X:
491case CT_P35:
492case CT_955X:
493case CT_X48:
494case CT_B43:
495case CT_Q45:
496case CT_P45:
497case CT_GM45:
498case CT_G45:
499case CT_G41:
500case CT_G31:
501case CT_500:
502case CT_3150:
503case CT_UNKWN_INTEL:// Assume newer intel chipset is the same as before
504outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
505map->b1 = inb(CONFIG_MECH_ONE_DATA + 1);
506map->b2 = inb(CONFIG_MECH_ONE_DATA + 2);
507outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
508outb(CONFIG_MECH_ONE_DATA + 1, 0x33);
509outb(CONFIG_MECH_ONE_DATA + 2, 0x33);
510break;
511}
512
513#if DEBUG
514{
515UInt32 t = inl(CONFIG_MECH_ONE_DATA);
516verbose("unlock PAM: (0x%08x)\n", t);
517}
518#endif
519}
520
521void relock_vbios(vbios_map * map)
522{
523
524map->unlocked = FALSE;
525
526switch (map->chipset)
527{
528case CT_UNKWN:
529break;
530case CT_830:
531case CT_855GM:
532outl(CONFIG_MECH_ONE_ADDR, 0x8000005a);
533outb(CONFIG_MECH_ONE_DATA + 2, map->b1);
534break;
535case CT_845G:
536case CT_865G:
537case CT_915G:
538case CT_915GM:
539case CT_945G:
540case CT_945GM:
541case CT_945GME:
542case CT_946GZ:
543case CT_G965:
544case CT_955X:
545case CT_G45:
546case CT_Q965:
547case CT_965GM:
548case CT_975X:
549case CT_P35:
550case CT_X48:
551case CT_B43:
552case CT_Q45:
553case CT_P45:
554case CT_GM45:
555case CT_G41:
556case CT_G31:
557case CT_500:
558case CT_3150:
559case CT_UNKWN_INTEL:
560outl(CONFIG_MECH_ONE_ADDR, 0x80000090);
561outb(CONFIG_MECH_ONE_DATA + 1, map->b1);
562outb(CONFIG_MECH_ONE_DATA + 2, map->b2);
563break;
564}
565
566#if DEBUG
567{
568 UInt32 t = inl(CONFIG_MECH_ONE_DATA);
569verbose("relock PAM: (0x%08x)\n", t);
570}
571#endif
572}
573
574
575int getMode(edid_mode *mode)
576{
577char* edidInfo = readEDID();
578
579if(!edidInfo) return 1;
580
581mode->pixel_clock = (edidInfo[55] << 8) | edidInfo[54];
582mode->h_active = edidInfo[56] | ((edidInfo[58] & 0xF0) << 4);
583mode->h_blanking = ((edidInfo[58] & 0x0F) << 8) | edidInfo[57];
584mode->v_active = edidInfo[59] | ((edidInfo[61] & 0xF0) << 4);
585mode->v_blanking = ((edidInfo[61] & 0x0F) << 8) | edidInfo[60];
586mode->h_sync_offset = ((edidInfo[65] & 0xC0) >> 2) | edidInfo[62];
587mode->h_sync_width = (edidInfo[65] & 0x30) | edidInfo[63];
588mode->v_sync_offset = (edidInfo[65] & 0x0C) | ((edidInfo[64] & 0x0C) >> 2);
589mode->v_sync_width = ((edidInfo[65] & 0x3) << 2) | (edidInfo[64] & 0x03);
590
591
592free( edidInfo );
593
594if(!mode->h_active) return 1;
595
596return 0;
597
598}
599
600
601static void gtf_timings(UInt32 x, UInt32 y, UInt32 freq,
602unsigned long *clock,
603UInt16 *hsyncstart, UInt16 *hsyncend, UInt16 *hblank,
604UInt16 *vsyncstart, UInt16 *vsyncend, UInt16 *vblank)
605{
606UInt32 hbl, vbl, vfreq;
607
608vbl = y + (y+1)/(20000.0/(11*freq) - 1) + 1.5;
609vfreq = vbl * freq;
610hbl = 16 * (int)(x * (30.0 - 300000.0 / vfreq) /
611 + (70.0 + 300000.0 / vfreq) / 16.0 + 0.5);
612
613*vsyncstart = y;
614*vsyncend = y + 3;
615*vblank = vbl - 1;
616*hsyncstart = x + hbl / 2 - (x + hbl + 50) / 100 * 8 - 1;
617*hsyncend = x + hbl / 2 - 1;
618*hblank = x + hbl - 1;
619*clock = (x + hbl) * vfreq / 1000;
620}
621
622void set_mode(vbios_map * map, /*UInt32 mode,*/ UInt32 x, UInt32 y, UInt32 bp, UInt32 htotal, UInt32 vtotal) {
623UInt32 xprev, yprev;
624UInt32 i = 0, j;
625// patch first available mode
626
627//for (i=0; i < map->mode_table_size; i++) {
628//if (map->mode_table[0].mode == mode) {
629switch(map->bios) {
630case BT_1:
631{
632vbios_resolution_type1 * res = map_type1_resolution(map, map->mode_table[i].resolution);
633
634if (bp) {
635map->mode_table[i].bits_per_pixel = bp;
636}
637
638res->x2 = (htotal?(((htotal-x) >> 8) & 0x0f) : (res->x2 & 0x0f)) | ((x >> 4) & 0xf0);
639res->x1 = (x & 0xff);
640
641res->y2 = (vtotal?(((vtotal-y) >> 8) & 0x0f) : (res->y2 & 0x0f)) | ((y >> 4) & 0xf0);
642res->y1 = (y & 0xff);
643if (htotal)
644res->x_total = ((htotal-x) & 0xff);
645
646if (vtotal)
647res->y_total = ((vtotal-y) & 0xff);
648
649break;
650}
651case BT_2:
652{
653vbios_resolution_type2 * res = map_type2_resolution(map, map->mode_table[i].resolution);
654
655res->xchars = x / 8;
656res->ychars = y / 16 - 1;
657xprev = res->modelines[0].x1;
658yprev = res->modelines[0].y1;
659
660for(j=0; j < 3; j++) {
661vbios_modeline_type2 * modeline = &res->modelines[j];
662
663if (modeline->x1 == xprev && modeline->y1 == yprev) {
664modeline->x1 = modeline->x2 = x-1;
665modeline->y1 = modeline->y2 = y-1;
666
667gtf_timings(x, y, freqs[j], &modeline->clock,
668&modeline->hsyncstart, &modeline->hsyncend,
669&modeline->hblank, &modeline->vsyncstart,
670&modeline->vsyncend, &modeline->vblank);
671
672if (htotal)
673modeline->htotal = htotal;
674else
675modeline->htotal = modeline->hblank;
676
677if (vtotal)
678modeline->vtotal = vtotal;
679else
680modeline->vtotal = modeline->vblank;
681}
682}
683break;
684}
685case BT_3:
686{
687vbios_resolution_type3 * res = map_type3_resolution(map, map->mode_table[i].resolution);
688
689xprev = res->modelines[0].x1;
690yprev = res->modelines[0].y1;
691
692for (j=0; j < 3; j++) {
693vbios_modeline_type3 * modeline = &res->modelines[j];
694
695if (modeline->x1 == xprev && modeline->y1 == yprev) {
696modeline->x1 = modeline->x2 = x-1;
697modeline->y1 = modeline->y2 = y-1;
698
699gtf_timings(x, y, freqs[j], &modeline->clock,
700&modeline->hsyncstart, &modeline->hsyncend,
701&modeline->hblank, &modeline->vsyncstart,
702&modeline->vsyncend, &modeline->vblank);
703if (htotal)
704modeline->htotal = htotal;
705else
706modeline->htotal = modeline->hblank;
707if (vtotal)
708modeline->vtotal = vtotal;
709else
710modeline->vtotal = modeline->vblank;
711
712modeline->timing_h = y-1;
713modeline->timing_v = x-1;
714}
715}
716break;
717}
718case BT_ATI_1:
719{
720edid_mode mode;
721
722ATOM_MODE_TIMING *mode_timing = (ATOM_MODE_TIMING *) map->ati_mode_table;
723
724//if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {
725if (!getMode(&mode)) {
726mode_timing->usCRTC_H_Total = mode.h_active + mode.h_blanking;
727mode_timing->usCRTC_H_Disp = mode.h_active;
728mode_timing->usCRTC_H_SyncStart = mode.h_active + mode.h_sync_offset;
729mode_timing->usCRTC_H_SyncWidth = mode.h_sync_width;
730
731mode_timing->usCRTC_V_Total = mode.v_active + mode.v_blanking;
732mode_timing->usCRTC_V_Disp = mode.v_active;
733mode_timing->usCRTC_V_SyncStart = mode.v_active + mode.v_sync_offset;
734mode_timing->usCRTC_V_SyncWidth = mode.v_sync_width;
735
736mode_timing->usPixelClock = mode.pixel_clock;
737}
738/*else
739{
740vbios_modeline_type2 modeline;
741
742cvt_timings(x, y, freqs[0], &modeline.clock,
743&modeline.hsyncstart, &modeline.hsyncend,
744&modeline.hblank, &modeline.vsyncstart,
745&modeline.vsyncend, &modeline.vblank, 0);
746
747mode_timing->usCRTC_H_Total = x + modeline.hblank;
748mode_timing->usCRTC_H_Disp = x;
749mode_timing->usCRTC_H_SyncStart = modeline.hsyncstart;
750mode_timing->usCRTC_H_SyncWidth = modeline.hsyncend - modeline.hsyncstart;
751
752mode_timing->usCRTC_V_Total = y + modeline.vblank;
753mode_timing->usCRTC_V_Disp = y;
754mode_timing->usCRTC_V_SyncStart = modeline.vsyncstart;
755mode_timing->usCRTC_V_SyncWidth = modeline.vsyncend - modeline.vsyncstart;
756
757mode_timing->usPixelClock = modeline.clock;
758 }*/
759
760break;
761}
762case BT_ATI_2:
763{
764edid_mode mode;
765
766ATOM_DTD_FORMAT *mode_timing = (ATOM_DTD_FORMAT *) map->ati_mode_table;
767
768/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/
769if (!getMode(&mode)) {
770mode_timing->usHBlanking_Time = mode.h_blanking;
771mode_timing->usHActive = mode.h_active;
772mode_timing->usHSyncOffset = mode.h_sync_offset;
773mode_timing->usHSyncWidth = mode.h_sync_width;
774
775mode_timing->usVBlanking_Time = mode.v_blanking;
776mode_timing->usVActive = mode.v_active;
777mode_timing->usVSyncOffset = mode.v_sync_offset;
778mode_timing->usVSyncWidth = mode.v_sync_width;
779
780mode_timing->usPixClk = mode.pixel_clock;
781}
782/*else
783{
784vbios_modeline_type2 modeline;
785
786cvt_timings(x, y, freqs[0], &modeline.clock,
787&modeline.hsyncstart, &modeline.hsyncend,
788&modeline.hblank, &modeline.vsyncstart,
789&modeline.vsyncend, &modeline.vblank, 0);
790
791mode_timing->usHBlanking_Time = modeline.hblank;
792 +mode_timing->usHActive = x;
793 +mode_timing->usHSyncOffset = modeline.hsyncstart - x;
794 +mode_timing->usHSyncWidth = modeline.hsyncend - modeline.hsyncstart;
795 +
796 +mode_timing->usVBlanking_Time = modeline.vblank;
797 +mode_timing->usVActive = y;
798 +mode_timing->usVSyncOffset = modeline.vsyncstart - y;
799 +mode_timing->usVSyncWidth = modeline.hsyncend - modeline.hsyncstart;
800 +
801 +mode_timing->usPixClk = modeline.clock;
802 +}*/
803
804
805break;
806}
807case BT_NVDA:
808{
809edid_mode mode;
810
811NV_MODELINE *mode_timing = (NV_MODELINE *) map->nv_mode_table;
812
813/*if (mode.pixel_clock && (mode.h_active == x) && (mode.v_active == y) && !force) {*/
814if (!getMode(&mode)) {
815mode_timing[i].usH_Total = mode.h_active + mode.h_blanking;
816mode_timing[i].usH_Active = mode.h_active;
817mode_timing[i].usH_SyncStart = mode.h_active + mode.h_sync_offset;
818mode_timing[i].usH_SyncEnd = mode.h_active + mode.h_sync_offset + mode.h_sync_width;
819
820mode_timing[i].usV_Total = mode.v_active + mode.v_blanking;
821mode_timing[i].usV_Active = mode.v_active;
822mode_timing[i].usV_SyncStart = mode.v_active + mode.v_sync_offset;
823mode_timing[i].usV_SyncEnd = mode.v_active + mode.v_sync_offset + mode.v_sync_width;
824
825mode_timing[i].usPixel_Clock = mode.pixel_clock;
826}
827/*else
828 {
829 vbios_modeline_type2 modeline;
830
831 cvt_timings(x, y, freqs[0], &modeline.clock,
832 &modeline.hsyncstart, &modeline.hsyncend,
833 &modeline.hblank, &modeline.vsyncstart,
834 &modeline.vsyncend, &modeline.vblank, 0);
835
836 mode_timing[i].usH_Total = x + modeline.hblank - 1;
837 mode_timing[i].usH_Active = x;
838 mode_timing[i].usH_SyncStart = modeline.hsyncstart - 1;
839 mode_timing[i].usH_SyncEnd = modeline.hsyncend - 1;
840
841 mode_timing[i].usV_Total = y + modeline.vblank - 1;
842 mode_timing[i].usV_Active = y;
843 mode_timing[i].usV_SyncStart = modeline.vsyncstart - 1;
844 mode_timing[i].usV_SyncEnd = modeline.vsyncend - 1;
845
846 mode_timing[i].usPixel_Clock = modeline.clock;
847 }*/
848break;
849}
850case BT_UNKWN:
851{
852break;
853}
854}
855//}
856//}
857}
858
859#endif // _RESOLUTION_H_

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