| 1 | /*␊ |
| 2 | *␉HDA injector / Audio Enabler␊ |
| 3 | *␊ |
| 4 | *␉Copyright (C) 2012␉Chameleon Team␊ |
| 5 | *␉Edit by Fabio (ErmaC)␊ |
| 6 | *␊ |
| 7 | *␉HDA injector is free software: you can redistribute it and/or modify␊ |
| 8 | *␉it under the terms of the GNU General Public License as published by␊ |
| 9 | *␉the Free Software Foundation, either version 3 of the License, or␊ |
| 10 | *␉(at your option) any later version.␊ |
| 11 | *␊ |
| 12 | *␉HDA injector is distributed in the hope that it will be useful,␊ |
| 13 | *␉but WITHOUT ANY WARRANTY; without even the implied warranty of␊ |
| 14 | *␉MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the␊ |
| 15 | *␉GNU General Public License for more details.␊ |
| 16 | *␊ |
| 17 | *␉Alternatively you can choose to comply with APSL␊ |
| 18 | *␊ |
| 19 | *␉Permission is hereby granted, free of charge, to any person obtaining a␊ |
| 20 | *␉copy of this software and associated documentation files (the "Software"),␊ |
| 21 | *␉to deal in the Software without restriction, including without limitation␊ |
| 22 | *␉the rights to use, copy, modify, merge, publish, distribute, sublicense,␊ |
| 23 | *␉and/or sell copies of the Software, and to permit persons to whom the␊ |
| 24 | *␉Software is furnished to do so, subject to the following conditions:␊ |
| 25 | *␊ |
| 26 | *␉The above copyright notice and this permission notice shall be included in␊ |
| 27 | *␉all copies or substantial portions of the Software.␊ |
| 28 | *␊ |
| 29 | ******************************************************************************␊ |
| 30 | * http://www.leidinger.net/FreeBSD/dox/dev_sound/html/df/d54/hdac_8c_source.html␊ |
| 31 | *␊ |
| 32 | * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>␊ |
| 33 | * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>␊ |
| 34 | * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>␊ |
| 35 | * All rights reserved.␊ |
| 36 | *␊ |
| 37 | * Redistribution and use in source and binary forms, with or without␊ |
| 38 | * modification, are permitted provided that the following conditions␊ |
| 39 | * are met:␊ |
| 40 | * 1. Redistributions of source code must retain the above copyright␊ |
| 41 | * notice, this list of conditions and the following disclaimer.␊ |
| 42 | * 2. Redistributions in binary form must reproduce the above copyright␊ |
| 43 | * notice, this list of conditions and the following disclaimer in the␊ |
| 44 | * documentation and/or other materials provided with the distribution.␊ |
| 45 | *␊ |
| 46 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND␊ |
| 47 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE␊ |
| 48 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE␊ |
| 49 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE␊ |
| 50 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL␊ |
| 51 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS␊ |
| 52 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)␊ |
| 53 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT␊ |
| 54 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY␊ |
| 55 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF␊ |
| 56 | * SUCH DAMAGE.␊ |
| 57 | *␊ |
| 58 | * Intel High Definition Audio (Controller) driver for FreeBSD.␊ |
| 59 | *␊ |
| 60 | ******************************************************************************/␊ |
| 61 | ␊ |
| 62 | #ifndef __LIBSAIO_HDA_H␊ |
| 63 | #define __LIBSAIO_HDA_H␊ |
| 64 | ␊ |
| 65 | static char *get_hda_controller_name( uint16_t controller_device_id, uint16_t controller_vendor_id );␊ |
| 66 | static char *get_hda_codec_name( uint16_t codec_vendor_id, uint16_t codec_device_id, uint8_t codec_revision_id, uint8_t codec_stepping_id );␊ |
| 67 | bool setup_hda_devprop( pci_dt_t *hda_dev );␊ |
| 68 | static int immediate_command(uint32_t command, uint32_t* response);␊ |
| 69 | static uint32_t get_parameter(uint8_t codec_id, uint8_t node_id, uint8_t parameter_id);␊ |
| 70 | static int getHDABar(uint32_t pci_addr, uint32_t* bar_phys_addr);␊ |
| 71 | void probe_hda_bus(uint32_t pci_addr);␊ |
| 72 | ␊ |
| 73 | struct hda_controller_devices;␊ |
| 74 | typedef struct␊ |
| 75 | {␊ |
| 76 | ␉uint32_t␉model;␊ |
| 77 | ␉char␉␉*desc;␊ |
| 78 | ␉// char␉␉quirks_on;␊ |
| 79 | ␉// char␉␉quirks_off;␊ |
| 80 | } hda_controller_devices;␊ |
| 81 | ␊ |
| 82 | struct hdacc_codecs;␊ |
| 83 | typedef struct␊ |
| 84 | {␊ |
| 85 | ␉uint32_t id;␊ |
| 86 | ␉uint32_t rev;␊ |
| 87 | ␉const char *name;␊ |
| 88 | } hdacc_codecs;␊ |
| 89 | ␊ |
| 90 | /****************************************************************************␊ |
| 91 | * Miscellanious defines␊ |
| 92 | ****************************************************************************/␊ |
| 93 | ␊ |
| 94 | /* Controller models */␊ |
| 95 | #define HDA_MODEL_CONSTRUCT(vendor, model) (((uint32_t)(model) << 16) | ((vendor##_VENDORID) & 0xffff))␊ |
| 96 | ␊ |
| 97 | /* Intel */␊ |
| 98 | #define INTEL_VENDORID␉␉PCI_VENDOR_ID_INTEL␊ |
| 99 | #define HDA_INTEL_OAK␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x080a) /* Oaktrail */␊ |
| 100 | #define HDA_INTEL_BAY␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0f04) /* BayTrail */␊ |
| 101 | #define HDA_INTEL_HSW1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0a0c) /* Haswell */␊ |
| 102 | #define HDA_INTEL_SER8HDMI␉HDA_MODEL_CONSTRUCT(INTEL, 0x0c0c) /* Haswell */␊ |
| 103 | #define HDA_INTEL_HSW3␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x0d0c) /* Haswell */␊ |
| 104 | #define HDA_INTEL_BDW␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x160c) /* Broadwell */␊ |
| 105 | #define HDA_INTEL_BROXTON_T␉HDA_MODEL_CONSTRUCT(INTEL, 0x1a98) /* Broxton-T */␊ |
| 106 | #define HDA_INTEL_CPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1c20) /* CPT */␊ |
| 107 | #define HDA_INTEL_PATSBURG␉HDA_MODEL_CONSTRUCT(INTEL, 0x1d20) /* PBG */␊ |
| 108 | #define HDA_INTEL_PPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x1e20) /* Panther Point */␊ |
| 109 | #define HDA_INTEL_BRASWELL ␉HDA_MODEL_CONSTRUCT(INTEL, 0x2284) /* Braswell */␊ |
| 110 | #define HDA_INTEL_82801F␉HDA_MODEL_CONSTRUCT(INTEL, 0x2668) /* ICH6 */␊ |
| 111 | #define HDA_INTEL_63XXESB␉HDA_MODEL_CONSTRUCT(INTEL, 0x269a) /* ESB2 */␊ |
| 112 | #define HDA_INTEL_82801G␉HDA_MODEL_CONSTRUCT(INTEL, 0x27d8) /* ICH7 */␊ |
| 113 | #define HDA_INTEL_82801H␉HDA_MODEL_CONSTRUCT(INTEL, 0x284b) /* ICH8 */␊ |
| 114 | #define HDA_INTEL_82801I␉HDA_MODEL_CONSTRUCT(INTEL, 0x293e) /* ICH9 */␊ |
| 115 | #define HDA_INTEL_ICH9␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x293f) /* ICH9 */␊ |
| 116 | #define HDA_INTEL_82801JI␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a3e) /* ICH10 */␊ |
| 117 | #define HDA_INTEL_82801JD␉HDA_MODEL_CONSTRUCT(INTEL, 0x3a6e) /* ICH10 */␊ |
| 118 | #define HDA_INTEL_PCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b56) /* 5 Series/3400 */␊ |
| 119 | #define HDA_INTEL_PCH2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x3b57) /* 5 Series/3400 */␊ |
| 120 | #define HDA_INTEL_BROXTON_P␉HDA_MODEL_CONSTRUCT(INTEL, 0x5a98) /* Broxton-P(Apollolake) */␊ |
| 121 | #define HDA_INTEL_MACBOOKPRO92␉HDA_MODEL_CONSTRUCT(INTEL, 0x7270)␊ |
| 122 | #define HDA_INTEL_SCH␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x811b) /* Poulsbo */␊ |
| 123 | #define HDA_INTEL_LPT1␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c20) /* Lynx Point */␊ |
| 124 | #define HDA_INTEL_LPT2␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8c21) /* Lynx Point */␊ |
| 125 | #define HDA_INTEL_WCPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0x8ca0) /* 9 Series */␊ |
| 126 | #define HDA_INTEL_WELLS1␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d20) /* Wellsburg */␊ |
| 127 | #define HDA_INTEL_WELLS2␉HDA_MODEL_CONSTRUCT(INTEL, 0x8d21) /* Wellsburg */␊ |
| 128 | #define HDA_INTEL_WCPTLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9ca0) /* Wildcat Point-LP */␊ |
| 129 | #define HDA_INTEL_LPTLP1␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c20) /* Lynx Point-LP */␊ |
| 130 | #define HDA_INTEL_LPTLP2␉HDA_MODEL_CONSTRUCT(INTEL, 0x9c21) /* Lynx Point-LP */␊ |
| 131 | #define HDA_INTEL_SRSPLP ␉HDA_MODEL_CONSTRUCT(INTEL, 0x9d70) /* Sunrise Point-LP */␊ |
| 132 | #define HDA_INTEL_KABYLAKE_LP␉HDA_MODEL_CONSTRUCT(INTEL, 0x9d71) /* Kabylake-LP */␊ |
| 133 | #define HDA_INTEL_SRSP␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xa170) /* Sunrise Point */␊ |
| 134 | #define HDA_INTEL_KABYLAKE␉HDA_MODEL_CONSTRUCT(INTEL, 0xa171) /* Kabylake */␊ |
| 135 | #define HDA_INTEL_LEWISBURG1␉HDA_MODEL_CONSTRUCT(INTEL, 0xa1f0) /* Lewisburg */␊ |
| 136 | #define HDA_INTEL_LEWISBURG2␉HDA_MODEL_CONSTRUCT(INTEL, 0xa270) /* Lewisburg */␊ |
| 137 | #define HDA_INTEL_UNPT␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xa2f0) /* Kabylake-H */␊ |
| 138 | #define HDA_INTEL_ALL␉␉HDA_MODEL_CONSTRUCT(INTEL, 0xffff)␊ |
| 139 | ␊ |
| 140 | /* Nvidia */␊ |
| 141 | #define NVIDIA_VENDORID␉␉PCI_VENDOR_ID_NVIDIA␊ |
| 142 | #define HDA_NVIDIA_MCP51␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x026c)␊ |
| 143 | #define HDA_NVIDIA_MCP55␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0371)␊ |
| 144 | #define HDA_NVIDIA_MCP61_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x03e4)␊ |
| 145 | #define HDA_NVIDIA_MCP61_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x03f0)␊ |
| 146 | #define HDA_NVIDIA_MCP65_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x044a)␊ |
| 147 | #define HDA_NVIDIA_MCP65_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x044b)␊ |
| 148 | #define HDA_NVIDIA_MCP67_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x055c)␊ |
| 149 | #define HDA_NVIDIA_MCP67_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x055d)␊ |
| 150 | #define HDA_NVIDIA_MCP78_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0774)␊ |
| 151 | #define HDA_NVIDIA_MCP78_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0775)␊ |
| 152 | #define HDA_NVIDIA_MCP78_3␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0776)␊ |
| 153 | #define HDA_NVIDIA_MCP78_4␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0777)␊ |
| 154 | #define HDA_NVIDIA_MCP73_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fc)␊ |
| 155 | #define HDA_NVIDIA_MCP73_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x07fd)␊ |
| 156 | #define HDA_NVIDIA_MCP79_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac0)␊ |
| 157 | #define HDA_NVIDIA_MCP79_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac1)␊ |
| 158 | #define HDA_NVIDIA_MCP79_3␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac2)␊ |
| 159 | #define HDA_NVIDIA_MCP79_4␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0ac3)␊ |
| 160 | #define HDA_NVIDIA_0BE2␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be2)␊ |
| 161 | #define HDA_NVIDIA_0BE3␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be3) // [GeForce 210] HDAcodec␊ |
| 162 | #define HDA_NVIDIA_0BE4␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be4) // [GeForge GT 240] HDACodec 10de000d (0d00de10)␊ |
| 163 | #define HDA_NVIDIA_GT100␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be5) // [GeForge GTX 470] HDACodec 10de0010 (1000de10)␊ |
| 164 | #define HDA_NVIDIA_GT106␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0be9)␊ |
| 165 | #define HDA_NVIDIA_GT108␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bea) // HDACodec␊ |
| 166 | #define HDA_NVIDIA_GT104␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0beb)␊ |
| 167 | #define HDA_NVIDIA_GT116␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0bee)␊ |
| 168 | #define HDA_NVIDIA_MCP89_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d94)␊ |
| 169 | #define HDA_NVIDIA_MCP89_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d95)␊ |
| 170 | #define HDA_NVIDIA_MCP89_3␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d96)␊ |
| 171 | #define HDA_NVIDIA_MCP89_4␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0d97)␊ |
| 172 | #define HDA_NVIDIA_GF119␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e08)␊ |
| 173 | #define HDA_NVIDIA_GF110_1␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e09)␊ |
| 174 | #define HDA_NVIDIA_GF110_2␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0c) // HDACodec de101600 (10de0016), Controller Binary de100c0e x2␊ |
| 175 | #define HDA_NVIDIA_GK104␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0a)␊ |
| 176 | #define HDA_NVIDIA_GK106␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e0b)␊ |
| 177 | #define HDA_NVIDIA_GK110␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1a)␊ |
| 178 | #define HDA_NVIDIA_GK107␉HDA_MODEL_CONSTRUCT(NVIDIA, 0x0e1b) // HDACodec de104200 (10de0042)␊ |
| 179 | #define HDA_NVIDIA_GP104_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x10f0) // GeForce GTX 1070␊ |
| 180 | #define HDA_NVIDIA_GM204_2 HDA_MODEL_CONSTRUCT(NVIDIA, 0x0fbb) // GeForce GTX 970␊ |
| 181 | #define HDA_NVIDIA_ALL␉␉HDA_MODEL_CONSTRUCT(NVIDIA, 0xffff)␊ |
| 182 | ␊ |
| 183 | /* ATI */␊ |
| 184 | #define ATI_VENDORID␉␉PCI_VENDOR_ID_ATI␊ |
| 185 | //#define HDA_ATI_0002␉␉HDA_MODEL_CONSTRUCT(ATI, 0x0002) /* ATI HDMI */␊ |
| 186 | //#define HDA_ATI_1308␉␉HDA_MODEL_CONSTRUCT(ATI, 0x1308) /* ATI HDMI */␊ |
| 187 | //#define HDA_ATI_177A␉␉HDA_MODEL_CONSTRUCT(ATI, 0x157a) /* ATI HDMI */␊ |
| 188 | //#define HDA_ATI_15B3␉␉HDA_MODEL_CONSTRUCT(ATI, 0x15b3) /* ATI HDMI */␊ |
| 189 | #define HDA_ATI_SB450␉␉HDA_MODEL_CONSTRUCT(ATI, 0x437b) /* ATI SB 450/600/700/800/900 */␊ |
| 190 | #define HDA_ATI_SB600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x4383) /* ATI SB 450/600/700/800/900 */␊ |
| 191 | #define HDA_ATI_HUDSON␉␉HDA_MODEL_CONSTRUCT(ATI, 0x780d) /* PCI_DEVICE(0x1022, 0x780d) */␊ |
| 192 | #define HDA_ATI_RS600␉␉HDA_MODEL_CONSTRUCT(ATI, 0x793b) /* ATI HDMI */␊ |
| 193 | #define HDA_ATI_RS690␉␉HDA_MODEL_CONSTRUCT(ATI, 0x7919) /* ATI HDMI */␊ |
| 194 | #define HDA_ATI_RS780␉␉HDA_MODEL_CONSTRUCT(ATI, 0x960f)␊ |
| 195 | #define HDA_ATI_RS880␉␉HDA_MODEL_CONSTRUCT(ATI, 0x970f) /* ATI HDMI */␊ |
| 196 | //#define HDA_ATI_9840␉␉HDA_MODEL_CONSTRUCT(ATI, 0x9840) /* ATI HDMI */␊ |
| 197 | #define HDA_ATI_TRINITY␉␉HDA_MODEL_CONSTRUCT(ATI, 0x9902) /* ATI HDMI */␊ |
| 198 | #define HDA_ATI_R600␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa00) /* ATI HDMI */␊ |
| 199 | #define HDA_ATI_RV630␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa08) /* ATI HDMI */␊ |
| 200 | #define HDA_ATI_RV610␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa10) /* ATI HDMI */␊ |
| 201 | #define HDA_ATI_RV670␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa18) /* ATI HDMI */␊ |
| 202 | #define HDA_ATI_RV635␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa20) /* ATI HDMI */␊ |
| 203 | #define HDA_ATI_RV620␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa28) /* ATI HDMI */␊ |
| 204 | #define HDA_ATI_RV770␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa30) /* ATI HDMI */␊ |
| 205 | #define HDA_ATI_RV730␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa38) /* ATI HDMI */␊ |
| 206 | #define HDA_ATI_RV710␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa40) /* ATI HDMI */␊ |
| 207 | #define HDA_ATI_RV740␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa48) /* ATI HDMI */␊ |
| 208 | #define HDA_ATI_RV870␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa50) /* ATI HDMI */␊ |
| 209 | #define HDA_ATI_RV840␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa58) /* ATI HDMI */␊ |
| 210 | #define HDA_ATI_RV830␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa60) /* ATI HDMI */␊ |
| 211 | #define HDA_ATI_RV810␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa68) /* ATI HDMI */␊ |
| 212 | #define HDA_ATI_RV970␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa80) /* ATI HDMI */␊ |
| 213 | #define HDA_ATI_RV940␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa88) /* ATI HDMI */␊ |
| 214 | #define HDA_ATI_RV930␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa90) /* ATI HDMI */␊ |
| 215 | #define HDA_ATI_RV910␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaa98) /* ATI HDMI */␊ |
| 216 | #define HDA_ATI_R1000␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa0) /* ATI HDMI */␊ |
| 217 | #define HDA_ATI_SI␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaa8) /* ATI HDMI */␊ |
| 218 | #define HDA_ATI_OLAND␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaab0) /* ATI HDMI */␊ |
| 219 | #define HDA_ATI_TAHITI␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaac0) /* ATI HDMI */␊ |
| 220 | #define HDA_ATI_HAWAII␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaac8) /* ATI HDMI */␊ |
| 221 | //#define HDA_ATI_AAD8␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaad8) /* ATI HDMI */␊ |
| 222 | //#define HDA_ATI_AAE8␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaae8) /* ATI HDMI */␊ |
| 223 | //#define HDA_ATI_AAE0␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaae0) /* ATI HDMI */␊ |
| 224 | //#define HDA_ATI_AAF0␉␉HDA_MODEL_CONSTRUCT(ATI, 0xaaf0) /* ATI HDMI */␊ |
| 225 | #define HDA_ATI_ALL␉␉HDA_MODEL_CONSTRUCT(ATI, 0xffff)␊ |
| 226 | ␊ |
| 227 | /* RDC */␊ |
| 228 | #define RDC_VENDORID␉␉0x17f3␊ |
| 229 | #define HDA_RDC_M3010␉␉HDA_MODEL_CONSTRUCT(RDC, 0x3010) /* Vortex86MX */␊ |
| 230 | ␊ |
| 231 | /* VIA */␊ |
| 232 | #define VIA_VENDORID␉␉0x1106␊ |
| 233 | #define HDA_VIA_VT82XX␉␉HDA_MODEL_CONSTRUCT(VIA, 0x3288) /* VIA VT8251/VT8237A */␊ |
| 234 | //#define HDA_VIA_VT71XX␉HDA_MODEL_CONSTRUCT(VIA, 0x9170) /* VIA GFX VT7122/VX900 */␊ |
| 235 | //#define HDA_VIA_VT61XX␉HDA_MODEL_CONSTRUCT(VIA, 0x9140) /* VIA GFX VT6122/VX11 */␊ |
| 236 | #define HDA_VIA_ALL␉␉HDA_MODEL_CONSTRUCT(VIA, 0xffff)␊ |
| 237 | ␊ |
| 238 | /* SiS */␊ |
| 239 | #define SIS_VENDORID␉␉0x1039␊ |
| 240 | #define HDA_SIS_966␉␉HDA_MODEL_CONSTRUCT(SIS, 0x7502) /* SIS966 */␊ |
| 241 | #define HDA_SIS_ALL␉␉HDA_MODEL_CONSTRUCT(SIS, 0xffff)␊ |
| 242 | ␊ |
| 243 | /* ULI */␊ |
| 244 | #define ULI_VENDORID␉␉0x10b9␊ |
| 245 | #define HDA_ULI_M5461␉␉HDA_MODEL_CONSTRUCT(ULI, 0x5461) /* ULI M5461 */␊ |
| 246 | #define HDA_ULI_ALL␉␉HDA_MODEL_CONSTRUCT(ULI, 0xffff)␊ |
| 247 | ␊ |
| 248 | /* Teradici */␊ |
| 249 | //{ PCI_DEVICE(0x6549, 0x1200),␊ |
| 250 | //{ PCI_DEVICE(0x6549, 0x2200}␊ |
| 251 | ␊ |
| 252 | /* CTHDA chips */␊ |
| 253 | //{ PCI_DEVICE(0x1102, 0x0010),␊ |
| 254 | //{ PCI_DEVICE(0x1102, 0x0012),␊ |
| 255 | ␊ |
| 256 | /* this entry seems still valid -- i.e. without emu20kx chip */␊ |
| 257 | //{ PCI_DEVICE(0x1102, 0x0009␊ |
| 258 | ␊ |
| 259 | /* CM8888 */␊ |
| 260 | //{ PCI_DEVICE(0x13f6, 0x5011),␊ |
| 261 | ␊ |
| 262 | /* VMware HDAudio */␊ |
| 263 | //{ PCI_DEVICE(0x15ad, 0x1977),␊ |
| 264 | ␊ |
| 265 | //#define HDEF_PATH "PciRoot(0x0)/Pci(0x1b,0x0)"␊ |
| 266 | //#define PINCONF_LEN ( sizeof(default_PinConfiguration) / sizeof(uint8_t) )␊ |
| 267 | #define HDA0_LEN ( sizeof(default_HDEF_layout_id) / sizeof(uint8_t) )␊ |
| 268 | #define HDA1_LEN ( sizeof(default_HDAU_layout_id) / sizeof(uint8_t) )␊ |
| 269 | ␊ |
| 270 | /* =================== C O D E C I N F O R M A T I O N ===================== */␊ |
| 271 | ␊ |
| 272 | #define HDA_CODEC_CONSTRUCT(vendor, id) (((uint32_t)(vendor##_VENDORID) << 16) | ((id) & 0xffff))␊ |
| 273 | ␊ |
| 274 | /* Cirrus Logic */␊ |
| 275 | #define CIRRUSLOGIC_VENDORID 0x1013␊ |
| 276 | #define HDA_CODEC_CS4206 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4206)␊ |
| 277 | #define HDA_CODEC_CS4207 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4207)␊ |
| 278 | #define HDA_CODEC_CS4208 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4208)␊ |
| 279 | #define HDA_CODEC_CS4210 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4210)␊ |
| 280 | #define HDA_CODEC_CS4213 HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0x4213)␊ |
| 281 | #define HDA_CODEC_CSXXXX HDA_CODEC_CONSTRUCT(CIRRUSLOGIC, 0xffff)␊ |
| 282 | ␊ |
| 283 | /* Realtek */␊ |
| 284 | #define REALTEK_VENDORID PCI_VENDOR_ID_REALTEK␊ |
| 285 | #define HDA_CODEC_ALC221 HDA_CODEC_CONSTRUCT(REALTEK, 0x0221)␊ |
| 286 | #define HDA_CODEC_ALC231 HDA_CODEC_CONSTRUCT(REALTEK, 0x0231)␊ |
| 287 | #define HDA_CODEC_ALC233 HDA_CODEC_CONSTRUCT(REALTEK, 0x0233)␊ |
| 288 | #define HDA_CODEC_ALC235 HDA_CODEC_CONSTRUCT(REALTEK, 0x0235)␊ |
| 289 | #define HDA_CODEC_ALC255 HDA_CODEC_CONSTRUCT(REALTEK, 0x0255)␊ |
| 290 | #define HDA_CODEC_ALC256 HDA_CODEC_CONSTRUCT(REALTEK, 0x0256)␊ |
| 291 | #define HDA_CODEC_ALC260 HDA_CODEC_CONSTRUCT(REALTEK, 0x0260)␊ |
| 292 | #define HDA_CODEC_ALC262 HDA_CODEC_CONSTRUCT(REALTEK, 0x0262)␊ |
| 293 | #define HDA_CODEC_ALC267 HDA_CODEC_CONSTRUCT(REALTEK, 0x0267)␊ |
| 294 | #define HDA_CODEC_ALC268 HDA_CODEC_CONSTRUCT(REALTEK, 0x0268)␊ |
| 295 | #define HDA_CODEC_ALC269 HDA_CODEC_CONSTRUCT(REALTEK, 0x0269)␊ |
| 296 | #define HDA_CODEC_ALC270 HDA_CODEC_CONSTRUCT(REALTEK, 0x0270)␊ |
| 297 | #define HDA_CODEC_ALC272 HDA_CODEC_CONSTRUCT(REALTEK, 0x0272)␊ |
| 298 | #define HDA_CODEC_ALC273 HDA_CODEC_CONSTRUCT(REALTEK, 0x0273)␊ |
| 299 | #define HDA_CODEC_ALC275 HDA_CODEC_CONSTRUCT(REALTEK, 0x0275)␊ |
| 300 | #define HDA_CODEC_ALC276 HDA_CODEC_CONSTRUCT(REALTEK, 0x0276)␊ |
| 301 | #define HDA_CODEC_ALC280␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0280)␊ |
| 302 | #define HDA_CODEC_ALC282␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0282)␊ |
| 303 | #define HDA_CODEC_ALC283␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0283)␊ |
| 304 | #define HDA_CODEC_ALC284␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0284)␊ |
| 305 | #define HDA_CODEC_ALC285␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0285)␊ |
| 306 | #define HDA_CODEC_ALC286␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0286)␊ |
| 307 | #define HDA_CODEC_ALC288␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0288)␊ |
| 308 | #define HDA_CODEC_ALC290␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0290)␊ |
| 309 | #define HDA_CODEC_ALC292␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0292)␊ |
| 310 | #define HDA_CODEC_ALC293␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0293)␊ |
| 311 | #define HDA_CODEC_ALC298␉HDA_CODEC_CONSTRUCT(REALTEK, 0x0298)␊ |
| 312 | #define HDA_CODEC_ALC660 HDA_CODEC_CONSTRUCT(REALTEK, 0x0660)␊ |
| 313 | #define HDA_CODEC_ALC662 HDA_CODEC_CONSTRUCT(REALTEK, 0x0662)␊ |
| 314 | #define HDA_CODEC_ALC663 HDA_CODEC_CONSTRUCT(REALTEK, 0x0663)␊ |
| 315 | #define HDA_CODEC_ALC665 HDA_CODEC_CONSTRUCT(REALTEK, 0x0665)␊ |
| 316 | #define HDA_CODEC_ALC667 HDA_CODEC_CONSTRUCT(REALTEK, 0x0667)␊ |
| 317 | #define HDA_CODEC_ALC668 HDA_CODEC_CONSTRUCT(REALTEK, 0x0668)␊ |
| 318 | #define HDA_CODEC_ALC670 HDA_CODEC_CONSTRUCT(REALTEK, 0x0670)␊ |
| 319 | #define HDA_CODEC_ALC671 HDA_CODEC_CONSTRUCT(REALTEK, 0x0671)␊ |
| 320 | #define HDA_CODEC_ALC680 HDA_CODEC_CONSTRUCT(REALTEK, 0x0680)␊ |
| 321 | #define HDA_CODEC_ALC861 HDA_CODEC_CONSTRUCT(REALTEK, 0x0861)␊ |
| 322 | #define HDA_CODEC_ALC861VD HDA_CODEC_CONSTRUCT(REALTEK, 0x0862)␊ |
| 323 | #define HDA_CODEC_ALC867 HDA_CODEC_CONSTRUCT(REALTEK, 0x0867)␊ |
| 324 | #define HDA_CODEC_ALC880 HDA_CODEC_CONSTRUCT(REALTEK, 0x0880)␊ |
| 325 | #define HDA_CODEC_ALC882 HDA_CODEC_CONSTRUCT(REALTEK, 0x0882)␊ |
| 326 | #define HDA_CODEC_ALC883 HDA_CODEC_CONSTRUCT(REALTEK, 0x0883)␊ |
| 327 | #define HDA_CODEC_ALC885 HDA_CODEC_CONSTRUCT(REALTEK, 0x0885)␊ |
| 328 | #define HDA_CODEC_ALC886 HDA_CODEC_CONSTRUCT(REALTEK, 0x0886)␊ |
| 329 | #define HDA_CODEC_ALC887 HDA_CODEC_CONSTRUCT(REALTEK, 0x0887)␊ |
| 330 | #define HDA_CODEC_ALC888 HDA_CODEC_CONSTRUCT(REALTEK, 0x0888)␊ |
| 331 | #define HDA_CODEC_ALC889 HDA_CODEC_CONSTRUCT(REALTEK, 0x0889)␊ |
| 332 | #define HDA_CODEC_ALC892 HDA_CODEC_CONSTRUCT(REALTEK, 0x0892)␊ |
| 333 | #define HDA_CODEC_ALC898 HDA_CODEC_CONSTRUCT(REALTEK, 0x0899)␊ |
| 334 | //#define HDA_CODEC_ALC898 HDA_CODEC_CONSTRUCT(REALTEK, 0x0898)␊ |
| 335 | //#define HDA_CODEC_ALC899 HDA_CODEC_CONSTRUCT(REALTEK, 0x0899)␊ |
| 336 | #define HDA_CODEC_ALC900 HDA_CODEC_CONSTRUCT(REALTEK, 0x0900)␊ |
| 337 | #define HDA_CODEC_ALCS1220A␉HDA_CODEC_CONSTRUCT(REALTEK, 0x1168)␊ |
| 338 | #define HDA_CODEC_ALC1220 HDA_CODEC_CONSTRUCT(REALTEK, 0x1220)␊ |
| 339 | #define HDA_CODEC_ALCXXXX HDA_CODEC_CONSTRUCT(REALTEK, 0xffff)␊ |
| 340 | ␊ |
| 341 | /* Motorola */␊ |
| 342 | #define MOTO_VENDORID PCI_VENDOR_ID_MOTOROLA␊ |
| 343 | #define HDA_CODEC_MOTOXXXX HDA_CODEC_CONSTRUCT(MOTO, 0xffff)␊ |
| 344 | ␊ |
| 345 | /* Creative */␊ |
| 346 | #define CREATIVE_VENDORID 0x1102␊ |
| 347 | #define HDA_CODEC_XFIEA HDA_CODEC_CONSTRUCT(CREATIVE, 0x000a)␊ |
| 348 | #define HDA_CODEC_XFIED HDA_CODEC_CONSTRUCT(CREATIVE, 0x000b)␊ |
| 349 | #define HDA_CODEC_SB0880 HDA_CODEC_CONSTRUCT(CREATIVE, 0x000d)␊ |
| 350 | #define HDA_CODEC_CA0132 HDA_CODEC_CONSTRUCT(CREATIVE, 0x0011)␊ |
| 351 | #define HDA_CODEC_CAXXXX HDA_CODEC_CONSTRUCT(CREATIVE, 0xffff)␊ |
| 352 | ␊ |
| 353 | /* Analog Devices */␊ |
| 354 | #define ANALOGDEVICES_VENDORID 0x11d4␊ |
| 355 | #define HDA_CODEC_AD1884A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x184a)␊ |
| 356 | #define HDA_CODEC_AD1882 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1882)␊ |
| 357 | #define HDA_CODEC_AD1883 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1883)␊ |
| 358 | #define HDA_CODEC_AD1884 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1884)␊ |
| 359 | #define HDA_CODEC_AD1984A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194a)␊ |
| 360 | #define HDA_CODEC_AD1984B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x194b)␊ |
| 361 | #define HDA_CODEC_AD1981HD HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1981)␊ |
| 362 | #define HDA_CODEC_AD1983 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1983)␊ |
| 363 | #define HDA_CODEC_AD1984 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1984)␊ |
| 364 | #define HDA_CODEC_AD1986A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1986)␊ |
| 365 | #define HDA_CODEC_AD1987 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1987)␊ |
| 366 | #define HDA_CODEC_AD1988 HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x1988)␊ |
| 367 | #define HDA_CODEC_AD1988B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x198b)␊ |
| 368 | #define HDA_CODEC_AD1882A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x882a)␊ |
| 369 | #define HDA_CODEC_AD1989A HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989a)␊ |
| 370 | #define HDA_CODEC_AD1989B HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0x989b)␊ |
| 371 | #define HDA_CODEC_ADXXXX HDA_CODEC_CONSTRUCT(ANALOGDEVICES, 0xffff)␊ |
| 372 | ␊ |
| 373 | /* CMedia */␊ |
| 374 | #define CMEDIA_VENDORID 0x13f6␊ |
| 375 | #define HDA_CODEC_CMI8880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x8880)␊ |
| 376 | #define HDA_CODEC_CMI9880 HDA_CODEC_CONSTRUCT(CMEDIA, 0x9880)␊ |
| 377 | #define HDA_CODEC_CMIXXXX HDA_CODEC_CONSTRUCT(CMEDIA, 0xffff)␊ |
| 378 | ␊ |
| 379 | /* CMedia */␊ |
| 380 | #define CMEDIA2_VENDORID 0x434d␊ |
| 381 | #define HDA_CODEC_CMI98802 HDA_CODEC_CONSTRUCT(CMEDIA2, 0x4980)␊ |
| 382 | #define HDA_CODEC_CMIXXXX2 HDA_CODEC_CONSTRUCT(CMEDIA2, 0xffff)␊ |
| 383 | ␊ |
| 384 | /* Sigmatel */␊ |
| 385 | #define SIGMATEL_VENDORID 0x8384␊ |
| 386 | #define HDA_CODEC_STAC9230X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7612)␊ |
| 387 | #define HDA_CODEC_STAC9230D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7613)␊ |
| 388 | #define HDA_CODEC_STAC9229X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7614)␊ |
| 389 | #define HDA_CODEC_STAC9229D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7615)␊ |
| 390 | #define HDA_CODEC_STAC9228X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7616)␊ |
| 391 | #define HDA_CODEC_STAC9228D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7617)␊ |
| 392 | #define HDA_CODEC_STAC9227X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7618)␊ |
| 393 | #define HDA_CODEC_STAC9227D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7619)␊ |
| 394 | #define HDA_CODEC_STAC9274 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7620)␊ |
| 395 | #define HDA_CODEC_STAC9274D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7621)␊ |
| 396 | #define HDA_CODEC_STAC9273X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7622)␊ |
| 397 | #define HDA_CODEC_STAC9273D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7623)␊ |
| 398 | #define HDA_CODEC_STAC9272X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7624)␊ |
| 399 | #define HDA_CODEC_STAC9272D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7625)␊ |
| 400 | #define HDA_CODEC_STAC9271X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7626)␊ |
| 401 | #define HDA_CODEC_STAC9271D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7627)␊ |
| 402 | #define HDA_CODEC_STAC9274X5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7628)␊ |
| 403 | #define HDA_CODEC_STAC9274D5NH HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7629)␊ |
| 404 | #define HDA_CODEC_STAC9202 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7632)␊ |
| 405 | #define HDA_CODEC_STAC9202D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7633)␊ |
| 406 | #define HDA_CODEC_STAC9250 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7634)␊ |
| 407 | #define HDA_CODEC_STAC9250D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7635)␊ |
| 408 | #define HDA_CODEC_STAC9251 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7636)␊ |
| 409 | #define HDA_CODEC_STAC9250D_1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7637)␊ |
| 410 | #define HDA_CODEC_IDT92HD700X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7638)␊ |
| 411 | #define HDA_CODEC_IDT92HD700D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7639)␊ |
| 412 | #define HDA_CODEC_IDT92HD206X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7645)␊ |
| 413 | #define HDA_CODEC_IDT92HD206D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7646)␊ |
| 414 | #define HDA_CODEC_CXD9872RDK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7661)␊ |
| 415 | #define HDA_CODEC_STAC9872AK HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7662)␊ |
| 416 | #define HDA_CODEC_CXD9872AKD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7664)␊ |
| 417 | #define HDA_CODEC_STAC9221 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7680)␊ |
| 418 | #define HDA_CODEC_STAC922XD HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7681)␊ |
| 419 | #define HDA_CODEC_STAC9221_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7682)␊ |
| 420 | #define HDA_CODEC_STAC9221D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7683)␊ |
| 421 | #define HDA_CODEC_STAC9220 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7690)␊ |
| 422 | #define HDA_CODEC_STAC9200D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7691)␊ |
| 423 | #define HDA_CODEC_IDT92HD005 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7698)␊ |
| 424 | #define HDA_CODEC_IDT92HD005D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7699)␊ |
| 425 | #define HDA_CODEC_STAC9205X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a0)␊ |
| 426 | #define HDA_CODEC_STAC9205D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a1)␊ |
| 427 | #define HDA_CODEC_STAC9204X HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a2)␊ |
| 428 | #define HDA_CODEC_STAC9204D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a3)␊ |
| 429 | #define HDA_CODEC_STAC9255 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a4)␊ |
| 430 | #define HDA_CODEC_STAC9255D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a5)␊ |
| 431 | #define HDA_CODEC_STAC9254 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a6)␊ |
| 432 | #define HDA_CODEC_STAC9254D HDA_CODEC_CONSTRUCT(SIGMATEL, 0x76a7)␊ |
| 433 | #define HDA_CODEC_STAC9220_A2 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7880)␊ |
| 434 | #define HDA_CODEC_STAC9220_A1 HDA_CODEC_CONSTRUCT(SIGMATEL, 0x7882)␊ |
| 435 | #define HDA_CODEC_STACXXXX HDA_CODEC_CONSTRUCT(SIGMATEL, 0xffff)␊ |
| 436 | ␊ |
| 437 | /* IDT */␊ |
| 438 | #define IDT_VENDORID 0x111d␊ |
| 439 | #define HDA_CODEC_IDT92HD75BX HDA_CODEC_CONSTRUCT(IDT, 0x7603)␊ |
| 440 | #define HDA_CODEC_IDT92HD83C1X HDA_CODEC_CONSTRUCT(IDT, 0x7604)␊ |
| 441 | #define HDA_CODEC_IDT92HD81B1X HDA_CODEC_CONSTRUCT(IDT, 0x7605)␊ |
| 442 | #define HDA_CODEC_IDT92HD75B3 HDA_CODEC_CONSTRUCT(IDT, 0x7608)␊ |
| 443 | #define HDA_CODEC_IDT92HD88B3 HDA_CODEC_CONSTRUCT(IDT, 0x7666)␊ |
| 444 | #define HDA_CODEC_IDT92HD88B1 HDA_CODEC_CONSTRUCT(IDT, 0x7667)␊ |
| 445 | #define HDA_CODEC_IDT92HD88B2 HDA_CODEC_CONSTRUCT(IDT, 0x7668)␊ |
| 446 | #define HDA_CODEC_IDT92HD88B4 HDA_CODEC_CONSTRUCT(IDT, 0x7669)␊ |
| 447 | #define HDA_CODEC_IDT92HD73D1 HDA_CODEC_CONSTRUCT(IDT, 0x7674)␊ |
| 448 | #define HDA_CODEC_IDT92HD73C1 HDA_CODEC_CONSTRUCT(IDT, 0x7675)␊ |
| 449 | #define HDA_CODEC_IDT92HD73E1 HDA_CODEC_CONSTRUCT(IDT, 0x7676)␊ |
| 450 | #define HDA_CODEC_IDT92HD95 HDA_CODEC_CONSTRUCT(IDT, 0x7695)␊ |
| 451 | #define HDA_CODEC_IDT92HD71B8 HDA_CODEC_CONSTRUCT(IDT, 0x76b0)␊ |
| 452 | #define HDA_CODEC_IDT92HD71B8_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b1)␊ |
| 453 | #define HDA_CODEC_IDT92HD71B7 HDA_CODEC_CONSTRUCT(IDT, 0x76b2)␊ |
| 454 | #define HDA_CODEC_IDT92HD71B7_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b3)␊ |
| 455 | #define HDA_CODEC_IDT92HD71B6 HDA_CODEC_CONSTRUCT(IDT, 0x76b4)␊ |
| 456 | #define HDA_CODEC_IDT92HD71B6_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b5)␊ |
| 457 | #define HDA_CODEC_IDT92HD71B5 HDA_CODEC_CONSTRUCT(IDT, 0x76b6)␊ |
| 458 | #define HDA_CODEC_IDT92HD71B5_2 HDA_CODEC_CONSTRUCT(IDT, 0x76b7)␊ |
| 459 | #define HDA_CODEC_IDT92HD89C3 HDA_CODEC_CONSTRUCT(IDT, 0x76c0)␊ |
| 460 | #define HDA_CODEC_IDT92HD89C2 HDA_CODEC_CONSTRUCT(IDT, 0x76c1)␊ |
| 461 | #define HDA_CODEC_IDT92HD89C1 HDA_CODEC_CONSTRUCT(IDT, 0x76c2)␊ |
| 462 | #define HDA_CODEC_IDT92HD89B3 HDA_CODEC_CONSTRUCT(IDT, 0x76c3)␊ |
| 463 | #define HDA_CODEC_IDT92HD89B2 HDA_CODEC_CONSTRUCT(IDT, 0x76c4)␊ |
| 464 | #define HDA_CODEC_IDT92HD89B1 HDA_CODEC_CONSTRUCT(IDT, 0x76c5)␊ |
| 465 | #define HDA_CODEC_IDT92HD89E3 HDA_CODEC_CONSTRUCT(IDT, 0x76c6)␊ |
| 466 | #define HDA_CODEC_IDT92HD89E2 HDA_CODEC_CONSTRUCT(IDT, 0x76c7)␊ |
| 467 | #define HDA_CODEC_IDT92HD89E1 HDA_CODEC_CONSTRUCT(IDT, 0x76c8)␊ |
| 468 | #define HDA_CODEC_IDT92HD89D3 HDA_CODEC_CONSTRUCT(IDT, 0x76c9)␊ |
| 469 | #define HDA_CODEC_IDT92HD89D2 HDA_CODEC_CONSTRUCT(IDT, 0x76ca)␊ |
| 470 | #define HDA_CODEC_IDT92HD89D1 HDA_CODEC_CONSTRUCT(IDT, 0x76cb)␊ |
| 471 | #define HDA_CODEC_IDT92HD89F3 HDA_CODEC_CONSTRUCT(IDT, 0x76cc)␊ |
| 472 | #define HDA_CODEC_IDT92HD89F2 HDA_CODEC_CONSTRUCT(IDT, 0x76cd)␊ |
| 473 | #define HDA_CODEC_IDT92HD89F1 HDA_CODEC_CONSTRUCT(IDT, 0x76ce)␊ |
| 474 | #define HDA_CODEC_IDT92HD87B1_3 HDA_CODEC_CONSTRUCT(IDT, 0x76d1)␊ |
| 475 | #define HDA_CODEC_IDT92HD83C1C HDA_CODEC_CONSTRUCT(IDT, 0x76d4)␊ |
| 476 | #define HDA_CODEC_IDT92HD81B1C HDA_CODEC_CONSTRUCT(IDT, 0x76d5)␊ |
| 477 | #define HDA_CODEC_IDT92HD87B2_4 HDA_CODEC_CONSTRUCT(IDT, 0x76d9)␊ |
| 478 | #define HDA_CODEC_IDT92HD93BXX HDA_CODEC_CONSTRUCT(IDT, 0x76df)␊ |
| 479 | #define HDA_CODEC_IDT92HD91BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e0)␊ |
| 480 | #define HDA_CODEC_IDT92HD98BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e3)␊ |
| 481 | #define HDA_CODEC_IDT92HD99BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e5)␊ |
| 482 | #define HDA_CODEC_IDT92HD90BXX HDA_CODEC_CONSTRUCT(IDT, 0x76e7)␊ |
| 483 | #define HDA_CODEC_IDT92HD66B1X5 HDA_CODEC_CONSTRUCT(IDT, 0x76e8)␊ |
| 484 | #define HDA_CODEC_IDT92HD66B2X5 HDA_CODEC_CONSTRUCT(IDT, 0x76e9)␊ |
| 485 | #define HDA_CODEC_IDT92HD66B3X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ea)␊ |
| 486 | #define HDA_CODEC_IDT92HD66C1X5 HDA_CODEC_CONSTRUCT(IDT, 0x76eb)␊ |
| 487 | #define HDA_CODEC_IDT92HD66C2X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ec)␊ |
| 488 | #define HDA_CODEC_IDT92HD66C3X5 HDA_CODEC_CONSTRUCT(IDT, 0x76ed)␊ |
| 489 | #define HDA_CODEC_IDT92HD66B1X3 HDA_CODEC_CONSTRUCT(IDT, 0x76ee)␊ |
| 490 | #define HDA_CODEC_IDT92HD66B2X3 HDA_CODEC_CONSTRUCT(IDT, 0x76ef)␊ |
| 491 | #define HDA_CODEC_IDT92HD66B3X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f0)␊ |
| 492 | #define HDA_CODEC_IDT92HD66C1X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f1)␊ |
| 493 | #define HDA_CODEC_IDT92HD66C2X3 HDA_CODEC_CONSTRUCT(IDT, 0x76f2)␊ |
| 494 | #define HDA_CODEC_IDT92HD66C3_65 HDA_CODEC_CONSTRUCT(IDT, 0x76f3)␊ |
| 495 | #define HDA_CODEC_IDTXXXX HDA_CODEC_CONSTRUCT(IDT, 0xffff)␊ |
| 496 | ␊ |
| 497 | /* Silicon Image */␊ |
| 498 | #define SII_VENDORID 0x1095␊ |
| 499 | #define HDA_CODEC_SII1390 HDA_CODEC_CONSTRUCT(SII, 0x1390)␊ |
| 500 | #define HDA_CODEC_SII1392 HDA_CODEC_CONSTRUCT(SII, 0x1392)␊ |
| 501 | #define HDA_CODEC_SIIXXXX HDA_CODEC_CONSTRUCT(SII, 0xffff)␊ |
| 502 | ␊ |
| 503 | /* LSI - Lucent/Agere */␊ |
| 504 | #define AGERE_VENDORID 0x11c1␊ |
| 505 | #define HDA_CODEC_AGEREXXXX HDA_CODEC_CONSTRUCT(AGERE, 0xffff)␊ |
| 506 | ␊ |
| 507 | /* Conexant */␊ |
| 508 | #define CONEXANT_VENDORID 0x14f1␊ |
| 509 | #define HDA_CODEC_CX20549 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5045)␊ |
| 510 | #define HDA_CODEC_CX20551 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5047)␊ |
| 511 | #define HDA_CODEC_CX20561 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5051)␊ |
| 512 | #define HDA_CODEC_CX20582 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5066)␊ |
| 513 | #define HDA_CODEC_CX20583 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5067)␊ |
| 514 | #define HDA_CODEC_CX20584 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5068)␊ |
| 515 | #define HDA_CODEC_CX20585 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5069)␊ |
| 516 | #define HDA_CODEC_CX20588 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506c)␊ |
| 517 | #define HDA_CODEC_CX20590 HDA_CODEC_CONSTRUCT(CONEXANT, 0x506e)␊ |
| 518 | #define HDA_CODEC_CX20631 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5097)␊ |
| 519 | #define HDA_CODEC_CX20632 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5098)␊ |
| 520 | #define HDA_CODEC_CX20641 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a1)␊ |
| 521 | #define HDA_CODEC_CX20642 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50a2)␊ |
| 522 | #define HDA_CODEC_CX20651 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ab)␊ |
| 523 | #define HDA_CODEC_CX20652 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50ac)␊ |
| 524 | #define HDA_CODEC_CX20664 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b8)␊ |
| 525 | #define HDA_CODEC_CX20665 HDA_CODEC_CONSTRUCT(CONEXANT, 0x50b9)␊ |
| 526 | #define HDA_CODEC_CX20751 HDA_CODEC_CONSTRUCT(CONEXANT, 0x510f)␊ |
| 527 | #define HDA_CODEC_CX20751_2␉HDA_CODEC_CONSTRUCT(CONEXANT, 0x5110)␊ |
| 528 | #define HDA_CODEC_CX20751_4␉HDA_CODEC_CONSTRUCT(CONEXANT, 0x5111)␊ |
| 529 | #define HDA_CODEC_CX20755 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5113)␊ |
| 530 | #define HDA_CODEC_CX20756 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5114)␊ |
| 531 | #define HDA_CODEC_CX20757 HDA_CODEC_CONSTRUCT(CONEXANT, 0x5115)␊ |
| 532 | #define HDA_CODEC_CX20952 HDA_CODEC_CONSTRUCT(CONEXANT, 0x51d7)␊ |
| 533 | #define HDA_CODEC_CXXXXX HDA_CODEC_CONSTRUCT(CONEXANT, 0xffff)␊ |
| 534 | ␊ |
| 535 | /* VIA */␊ |
| 536 | #define HDA_CODEC_VT1708_8 HDA_CODEC_CONSTRUCT(VIA, 0x1708)␊ |
| 537 | #define HDA_CODEC_VT1708_9 HDA_CODEC_CONSTRUCT(VIA, 0x1709)␊ |
| 538 | #define HDA_CODEC_VT1708_A HDA_CODEC_CONSTRUCT(VIA, 0x170a)␊ |
| 539 | #define HDA_CODEC_VT1708_B HDA_CODEC_CONSTRUCT(VIA, 0x170b)␊ |
| 540 | #define HDA_CODEC_VT1709_0 HDA_CODEC_CONSTRUCT(VIA, 0xe710)␊ |
| 541 | #define HDA_CODEC_VT1709_1 HDA_CODEC_CONSTRUCT(VIA, 0xe711)␊ |
| 542 | #define HDA_CODEC_VT1709_2 HDA_CODEC_CONSTRUCT(VIA, 0xe712)␊ |
| 543 | #define HDA_CODEC_VT1709_3 HDA_CODEC_CONSTRUCT(VIA, 0xe713)␊ |
| 544 | #define HDA_CODEC_VT1709_4 HDA_CODEC_CONSTRUCT(VIA, 0xe714)␊ |
| 545 | #define HDA_CODEC_VT1709_5 HDA_CODEC_CONSTRUCT(VIA, 0xe715)␊ |
| 546 | #define HDA_CODEC_VT1709_6 HDA_CODEC_CONSTRUCT(VIA, 0xe716)␊ |
| 547 | #define HDA_CODEC_VT1709_7 HDA_CODEC_CONSTRUCT(VIA, 0xe717)␊ |
| 548 | #define HDA_CODEC_VT1708B_0 HDA_CODEC_CONSTRUCT(VIA, 0xe720)␊ |
| 549 | #define HDA_CODEC_VT1708B_1 HDA_CODEC_CONSTRUCT(VIA, 0xe721)␊ |
| 550 | #define HDA_CODEC_VT1708B_2 HDA_CODEC_CONSTRUCT(VIA, 0xe722)␊ |
| 551 | #define HDA_CODEC_VT1708B_3 HDA_CODEC_CONSTRUCT(VIA, 0xe723)␊ |
| 552 | #define HDA_CODEC_VT1708B_4 HDA_CODEC_CONSTRUCT(VIA, 0xe724)␊ |
| 553 | #define HDA_CODEC_VT1708B_5 HDA_CODEC_CONSTRUCT(VIA, 0xe725)␊ |
| 554 | #define HDA_CODEC_VT1708B_6 HDA_CODEC_CONSTRUCT(VIA, 0xe726)␊ |
| 555 | #define HDA_CODEC_VT1708B_7 HDA_CODEC_CONSTRUCT(VIA, 0xe727)␊ |
| 556 | #define HDA_CODEC_VT1708S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0397)␊ |
| 557 | #define HDA_CODEC_VT1708S_1 HDA_CODEC_CONSTRUCT(VIA, 0x1397)␊ |
| 558 | #define HDA_CODEC_VT1708S_2 HDA_CODEC_CONSTRUCT(VIA, 0x2397)␊ |
| 559 | #define HDA_CODEC_VT1708S_3 HDA_CODEC_CONSTRUCT(VIA, 0x3397)␊ |
| 560 | #define HDA_CODEC_VT1708S_4 HDA_CODEC_CONSTRUCT(VIA, 0x4397)␊ |
| 561 | #define HDA_CODEC_VT1708S_5 HDA_CODEC_CONSTRUCT(VIA, 0x5397)␊ |
| 562 | #define HDA_CODEC_VT1708S_6 HDA_CODEC_CONSTRUCT(VIA, 0x6397)␊ |
| 563 | #define HDA_CODEC_VT1708S_7 HDA_CODEC_CONSTRUCT(VIA, 0x7397)␊ |
| 564 | #define HDA_CODEC_VT1702_0 HDA_CODEC_CONSTRUCT(VIA, 0x0398)␊ |
| 565 | #define HDA_CODEC_VT1702_1 HDA_CODEC_CONSTRUCT(VIA, 0x1398)␊ |
| 566 | #define HDA_CODEC_VT1702_2 HDA_CODEC_CONSTRUCT(VIA, 0x2398)␊ |
| 567 | #define HDA_CODEC_VT1702_3 HDA_CODEC_CONSTRUCT(VIA, 0x3398)␊ |
| 568 | #define HDA_CODEC_VT1702_4 HDA_CODEC_CONSTRUCT(VIA, 0x4398)␊ |
| 569 | #define HDA_CODEC_VT1702_5 HDA_CODEC_CONSTRUCT(VIA, 0x5398)␊ |
| 570 | #define HDA_CODEC_VT1702_6 HDA_CODEC_CONSTRUCT(VIA, 0x6398)␊ |
| 571 | #define HDA_CODEC_VT1702_7 HDA_CODEC_CONSTRUCT(VIA, 0x7398)␊ |
| 572 | #define HDA_CODEC_VT1716S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0433)␊ |
| 573 | #define HDA_CODEC_VT1716S_1 HDA_CODEC_CONSTRUCT(VIA, 0xa721)␊ |
| 574 | #define HDA_CODEC_VT1718S_0 HDA_CODEC_CONSTRUCT(VIA, 0x0428)␊ |
| 575 | #define HDA_CODEC_VT1718S_1 HDA_CODEC_CONSTRUCT(VIA, 0x4428)␊ |
| 576 | #define HDA_CODEC_VT1802_0 HDA_CODEC_CONSTRUCT(VIA, 0x0446)␊ |
| 577 | #define HDA_CODEC_VT1802_1 HDA_CODEC_CONSTRUCT(VIA, 0x8446)␊ |
| 578 | #define HDA_CODEC_VT1812 HDA_CODEC_CONSTRUCT(VIA, 0x0448)␊ |
| 579 | #define HDA_CODEC_VT1818S HDA_CODEC_CONSTRUCT(VIA, 0x0440)␊ |
| 580 | #define HDA_CODEC_VT1828S HDA_CODEC_CONSTRUCT(VIA, 0x4441)␊ |
| 581 | #define HDA_CODEC_VT2002P_0 HDA_CODEC_CONSTRUCT(VIA, 0x0438)␊ |
| 582 | #define HDA_CODEC_VT2002P_1 HDA_CODEC_CONSTRUCT(VIA, 0x4438)␊ |
| 583 | #define HDA_CODEC_VT2020 HDA_CODEC_CONSTRUCT(VIA, 0x0441)␊ |
| 584 | #define HDA_CODEC_VTXXXX HDA_CODEC_CONSTRUCT(VIA, 0xffff)␊ |
| 585 | ␊ |
| 586 | /* ATI */␊ |
| 587 | #define HDA_CODEC_ATIRS600_1 HDA_CODEC_CONSTRUCT(ATI, 0x793c)␊ |
| 588 | #define HDA_CODEC_ATIRS600_2 HDA_CODEC_CONSTRUCT(ATI, 0x7919)␊ |
| 589 | #define HDA_CODEC_ATIRS690 HDA_CODEC_CONSTRUCT(ATI, 0x791a)␊ |
| 590 | #define HDA_CODEC_ATIR6XX HDA_CODEC_CONSTRUCT(ATI, 0xaa01)␊ |
| 591 | #define HDA_CODEC_ATIXXXX HDA_CODEC_CONSTRUCT(ATI, 0xffff)␊ |
| 592 | ␊ |
| 593 | /* NVIDIA */␊ |
| 594 | #define HDA_CODEC_NVIDIAMCP78 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0002)␊ |
| 595 | #define HDA_CODEC_NVIDIAMCP78_2 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0003)␊ |
| 596 | #define HDA_CODEC_NVIDIAMCP78_3 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0005)␊ |
| 597 | #define HDA_CODEC_NVIDIAMCP78_4 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0006)␊ |
| 598 | #define HDA_CODEC_NVIDIAMCP7A HDA_CODEC_CONSTRUCT(NVIDIA, 0x0007)␊ |
| 599 | #define HDA_CODEC_NVIDIAGT220 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000a)␊ |
| 600 | #define HDA_CODEC_NVIDIAGT21X HDA_CODEC_CONSTRUCT(NVIDIA, 0x000b)␊ |
| 601 | #define HDA_CODEC_NVIDIAMCP89 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000c)␊ |
| 602 | #define HDA_CODEC_NVIDIAGT240 HDA_CODEC_CONSTRUCT(NVIDIA, 0x000d)␊ |
| 603 | #define HDA_CODEC_NVIDIAGTX470 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0010)␊ |
| 604 | #define HDA_CODEC_NVIDIAGTS450 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0011)␊ |
| 605 | #define HDA_CODEC_NVIDIAGT440 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0014)␊ |
| 606 | #define HDA_CODEC_NVIDIAGTX550 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0015)␊ |
| 607 | #define HDA_CODEC_NVIDIAGTX570 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0018)␊ |
| 608 | #define HDA_CODEC_NVIDIAGT610␉HDA_CODEC_CONSTRUCT(NVIDIA, 0x001c)␊ |
| 609 | #define HDA_CODEC_NVIDIATEGRA30␉HDA_CODEC_CONSTRUCT(NVIDIA, 0x0020)␊ |
| 610 | #define HDA_CODEC_NVIDIATEGRA114␉HDA_CODEC_CONSTRUCT(NVIDIA, 0x0022)␊ |
| 611 | #define HDA_CODEC_NVIDIATEGRA124␉HDA_CODEC_CONSTRUCT(NVIDIA, 0x0028)␊ |
| 612 | #define HDA_CODEC_NVIDIATEGRA210␉HDA_CODEC_CONSTRUCT(NVIDIA, 0x0029)␊ |
| 613 | #define HDA_CODEC_NVIDIAMCP67 HDA_CODEC_CONSTRUCT(NVIDIA, 0x0067)␊ |
| 614 | #define HDA_CODEC_NVIDIAMCP73 HDA_CODEC_CONSTRUCT(NVIDIA, 0x8001)␊ |
| 615 | #define HDA_CODEC_NVIDIAXXXX HDA_CODEC_CONSTRUCT(NVIDIA, 0xffff)␊ |
| 616 | ␊ |
| 617 | /* Chrontel */␊ |
| 618 | #define CHRONTEL_VENDORID 0x17e8␊ |
| 619 | #define HDA_CODEC_CHXXXX HDA_CODEC_CONSTRUCT(CHRONTEL, 0xffff)␊ |
| 620 | ␊ |
| 621 | /* LG */␊ |
| 622 | #define LG_VENDORID 0x1854␊ |
| 623 | #define HDA_CODEC_LGXXXX HDA_CODEC_CONSTRUCT(LG, 0xffff)␊ |
| 624 | ␊ |
| 625 | /* Wolfson Microelectronics */␊ |
| 626 | #define WOLFSON_VENDORID 0x14ec␊ |
| 627 | #define HDA_CODEC_WMXXXX HDA_CODEC_CONSTRUCT(WOLFSON, 0xffff)␊ |
| 628 | ␊ |
| 629 | /* QEMU */␊ |
| 630 | #define QEMU_VENDORID 0x1af4␊ |
| 631 | #define HDA_CODEC_QEMUXXXX HDA_CODEC_CONSTRUCT(QEMU, 0xffff)␊ |
| 632 | ␊ |
| 633 | /* INTEL */␊ |
| 634 | #define HDA_CODEC_INTELIP␉HDA_CODEC_CONSTRUCT(INTEL, 0x0054)␊ |
| 635 | #define HDA_CODEC_INTELWB␉HDA_CODEC_CONSTRUCT(INTEL, 0x0a0c)␊ |
| 636 | #define HDA_CODEC_INTELBL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2801)␊ |
| 637 | #define HDA_CODEC_INTELCA␉HDA_CODEC_CONSTRUCT(INTEL, 0x2802)␊ |
| 638 | #define HDA_CODEC_INTELEL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2803)␊ |
| 639 | #define HDA_CODEC_INTELIP2␉HDA_CODEC_CONSTRUCT(INTEL, 0x2804)␊ |
| 640 | #define HDA_CODEC_INTELCPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2805)␊ |
| 641 | #define HDA_CODEC_INTELPPT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2806) // Panther Point HDMI␊ |
| 642 | #define HDA_CODEC_INTELLLP␉HDA_CODEC_CONSTRUCT(INTEL, 0x2807) // Haswell HDMI␊ |
| 643 | #define HDA_CODEC_INTELBRW␉HDA_CODEC_CONSTRUCT(INTEL, 0x2808) // Broadwell HDMI␊ |
| 644 | #define HDA_CODEC_INTELSKL␉HDA_CODEC_CONSTRUCT(INTEL, 0x2809) // Skylake HDMI␊ |
| 645 | #define HDA_CODEC_INTELBRO␉HDA_CODEC_CONSTRUCT(INTEL, 0x280a) // Broxton HDMI␊ |
| 646 | #define HDA_CODEC_INTELKAB␉HDA_CODEC_CONSTRUCT(INTEL, 0x280b) // Kabylake HDMI␊ |
| 647 | #define HDA_CODEC_INTELCDT␉HDA_CODEC_CONSTRUCT(INTEL, 0x2880) // CedarTrail HDMI␊ |
| 648 | #define HDA_CODEC_INTELVLV␉HDA_CODEC_CONSTRUCT(INTEL, 0x2882) // Valleyview2 HDMI␊ |
| 649 | #define HDA_CODEC_INTELBSW␉HDA_CODEC_CONSTRUCT(INTEL, 0x2883) // Braswell HDMI␊ |
| 650 | #define HDA_CODEC_INTELCL␉HDA_CODEC_CONSTRUCT(INTEL, 0x29fb) // Crestline HDMI␊ |
| 651 | #define HDA_CODEC_INTELXXXX␉HDA_CODEC_CONSTRUCT(INTEL, 0xffff)␊ |
| 652 | ␊ |
| 653 | /****************************************************************************␊ |
| 654 | * HDA Controller Register Set␊ |
| 655 | ****************************************************************************/␊ |
| 656 | #define HDAC_GCAP␉0x00␉/* 2 - Global Capabilities*/␊ |
| 657 | #define HDAC_VMIN␉0x02␉/* 1 - Minor Version */␊ |
| 658 | #define HDAC_VMAJ␉0x03␉/* 1 - Major Version */␊ |
| 659 | #define␉HDAC_OUTPAY␉0x04␉/* 2 - Output Payload Capability */␊ |
| 660 | #define HDAC_INPAY␉0x06␉/* 2 - Input Payload Capability */␊ |
| 661 | #define HDAC_GCTL␉0x08␉/* 4 - Global Control */␊ |
| 662 | #define HDAC_WAKEEN␉0x0c␉/* 2 - Wake Enable */␊ |
| 663 | #define HDAC_STATESTS␉0x0e␉/* 2 - State Change Status */␊ |
| 664 | #define HDAC_GSTS␉0x10␉/* 2 - Global Status */␊ |
| 665 | #define HDAC_OUTSTRMPAY␉0x18␉/* 2 - Output Stream Payload Capability */␊ |
| 666 | #define HDAC_INSTRMPAY␉0x1a␉/* 2 - Input Stream Payload Capability */␊ |
| 667 | #define HDAC_INTCTL␉0x20␉/* 4 - Interrupt Control */␊ |
| 668 | #define HDAC_INTSTS␉0x24␉/* 4 - Interrupt Status */␊ |
| 669 | #define HDAC_WALCLK␉0x30␉/* 4 - Wall Clock Counter */␊ |
| 670 | #define HDAC_SSYNC␉0x38␉/* 4 - Stream Synchronization */␊ |
| 671 | #define HDAC_CORBLBASE␉0x40␉/* 4 - CORB Lower Base Address */␊ |
| 672 | #define HDAC_CORBUBASE␉0x44␉/* 4 - CORB Upper Base Address */␊ |
| 673 | #define HDAC_CORBWP␉0x48␉/* 2 - CORB Write Pointer */␊ |
| 674 | #define HDAC_CORBRP␉0x4a␉/* 2 - CORB Read Pointer */␊ |
| 675 | #define HDAC_CORBCTL␉0x4c␉/* 1 - CORB Control */␊ |
| 676 | #define HDAC_CORBSTS␉0x4d␉/* 1 - CORB Status */␊ |
| 677 | #define HDAC_CORBSIZE␉0x4e␉/* 1 - CORB Size */␊ |
| 678 | #define HDAC_RIRBLBASE␉0x50␉/* 4 - RIRB Lower Base Address */␊ |
| 679 | #define HDAC_RIRBUBASE␉0x54␉/* 4 - RIRB Upper Base Address */␊ |
| 680 | #define HDAC_RIRBWP␉0x58␉/* 2 - RIRB Write Pointer */␊ |
| 681 | #define HDAC_RINTCNT␉0x5a␉/* 2 - Response Interrupt Count */␊ |
| 682 | #define HDAC_RIRBCTL␉0x5c␉/* 1 - RIRB Control */␊ |
| 683 | #define HDAC_RIRBSTS␉0x5d␉/* 1 - RIRB Status */␊ |
| 684 | #define HDAC_RIRBSIZE␉0x5e␉/* 1 - RIRB Size */␊ |
| 685 | #define HDAC_ICOI␉0x60␉/* 4 - Immediate Command Output Interface */␊ |
| 686 | #define HDAC_ICII␉0x64␉/* 4 - Immediate Command Input Interface */␊ |
| 687 | #define HDAC_ICIS␉0x68␉/* 2 - Immediate Command Status */␊ |
| 688 | #define HDAC_DPIBLBASE␉0x70␉/* 4 - DMA Position Buffer Lower Base */␊ |
| 689 | #define HDAC_DPIBUBASE␉0x74␉/* 4 - DMA Position Buffer Upper Base */␊ |
| 690 | #define HDAC_SDCTL0␉0x80␉/* 3 - Stream Descriptor Control */␊ |
| 691 | #define HDAC_SDCTL1␉0x81␉/* 3 - Stream Descriptor Control */␊ |
| 692 | #define HDAC_SDCTL2␉0x82␉/* 3 - Stream Descriptor Control */␊ |
| 693 | #define HDAC_SDSTS␉0x83␉/* 1 - Stream Descriptor Status */␊ |
| 694 | #define HDAC_SDLPIB␉0x84␉/* 4 - Link Position in Buffer */␊ |
| 695 | #define HDAC_SDCBL␉0x88␉/* 4 - Cyclic Buffer Length */␊ |
| 696 | #define HDAC_SDLVI␉0x8C␉/* 2 - Last Valid Index */␊ |
| 697 | #define HDAC_SDFIFOS␉0x90␉/* 2 - FIFOS */␊ |
| 698 | #define HDAC_SDFMT␉0x92␉/* 2 - fmt */␊ |
| 699 | #define HDAC_SDBDPL␉0x98␉/* 4 - Buffer Descriptor Pointer Lower Base */␊ |
| 700 | #define HDAC_SDBDPU␉0x9C␉/* 4 - Buffer Descriptor Pointer Upper Base */␊ |
| 701 | ␊ |
| 702 | #define _HDAC_ISDOFFSET(n, iss, oss)␉(0x80 + ((n) * 0x20))␊ |
| 703 | #define _HDAC_ISDCTL(n, iss, oss)␉(0x00 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 704 | #define _HDAC_ISDSTS(n, iss, oss)␉(0x03 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 705 | #define _HDAC_ISDPICB(n, iss, oss)␉(0x04 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 706 | #define _HDAC_ISDCBL(n, iss, oss)␉(0x08 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 707 | #define _HDAC_ISDLVI(n, iss, oss)␉(0x0c + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 708 | #define _HDAC_ISDFIFOD(n, iss, oss)␉(0x10 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 709 | #define _HDAC_ISDFMT(n, iss, oss)␉(0x12 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 710 | #define _HDAC_ISDBDPL(n, iss, oss)␉(0x18 + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 711 | #define _HDAC_ISDBDPU(n, iss, oss)␉(0x1c + _HDAC_ISDOFFSET(n, iss, oss))␊ |
| 712 | ␊ |
| 713 | #define _HDAC_OSDOFFSET(n, iss, oss)␉(0x80 + ((iss) * 0x20) + ((n) * 0x20))␊ |
| 714 | #define _HDAC_OSDCTL(n, iss, oss)␉(0x00 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 715 | #define _HDAC_OSDSTS(n, iss, oss)␉(0x03 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 716 | #define _HDAC_OSDPICB(n, iss, oss)␉(0x04 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 717 | #define _HDAC_OSDCBL(n, iss, oss)␉(0x08 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 718 | #define _HDAC_OSDLVI(n, iss, oss)␉(0x0c + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 719 | #define _HDAC_OSDFIFOD(n, iss, oss)␉(0x10 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 720 | #define _HDAC_OSDFMT(n, iss, oss)␉(0x12 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 721 | #define _HDAC_OSDBDPL(n, iss, oss)␉(0x18 + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 722 | #define _HDAC_OSDBDPU(n, iss, oss)␉(0x1c + _HDAC_OSDOFFSET(n, iss, oss))␊ |
| 723 | ␊ |
| 724 | #define _HDAC_BSDOFFSET(n, iss, oss)␉(0x80 + ((iss) * 0x20) + ((oss) * 0x20) + ((n) * 0x20))␊ |
| 725 | #define _HDAC_BSDCTL(n, iss, oss)␉(0x00 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 726 | #define _HDAC_BSDSTS(n, iss, oss)␉(0x03 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 727 | #define _HDAC_BSDPICB(n, iss, oss)␉(0x04 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 728 | #define _HDAC_BSDCBL(n, iss, oss)␉(0x08 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 729 | #define _HDAC_BSDLVI(n, iss, oss)␉(0x0c + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 730 | #define _HDAC_BSDFIFOD(n, iss, oss)␉(0x10 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 731 | #define _HDAC_BSDFMT(n, iss, oss)␉(0x12 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 732 | #define _HDAC_BSDBDPL(n, iss, oss)␉(0x18 + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 733 | #define _HDAC_BSDBDBU(n, iss, oss)␉(0x1c + _HDAC_BSDOFFSET(n, iss, oss))␊ |
| 734 | ␊ |
| 735 | /****************************************************************************␊ |
| 736 | * HDA Controller Register Fields␊ |
| 737 | ****************************************************************************/␊ |
| 738 | ␊ |
| 739 | /* GCAP - Global Capabilities */␊ |
| 740 | #define HDAC_GCAP_64OK␉␉␉0x0001␊ |
| 741 | #define HDAC_GCAP_NSDO_MASK␉␉0x0006␊ |
| 742 | #define HDAC_GCAP_NSDO_SHIFT␉␉1␊ |
| 743 | #define HDAC_GCAP_BSS_MASK␉␉0x00f8␊ |
| 744 | #define HDAC_GCAP_BSS_SHIFT␉␉3␊ |
| 745 | #define HDAC_GCAP_ISS_MASK␉␉0x0f00␊ |
| 746 | #define HDAC_GCAP_ISS_SHIFT␉␉8␊ |
| 747 | #define HDAC_GCAP_OSS_MASK␉␉0xf000␊ |
| 748 | #define HDAC_GCAP_OSS_SHIFT␉␉12␊ |
| 749 | ␊ |
| 750 | #define HDAC_GCAP_NSDO_1SDO␉␉0x00␊ |
| 751 | #define HDAC_GCAP_NSDO_2SDO␉␉0x02␊ |
| 752 | #define HDAC_GCAP_NSDO_4SDO␉␉0x04␊ |
| 753 | ␊ |
| 754 | #define HDAC_GCAP_BSS(gcap)␉␉␉␉␉␉\␊ |
| 755 | (((gcap) & HDAC_GCAP_BSS_MASK) >> HDAC_GCAP_BSS_SHIFT)␊ |
| 756 | #define HDAC_GCAP_ISS(gcap)␉␉␉␉␉␉\␊ |
| 757 | (((gcap) & HDAC_GCAP_ISS_MASK) >> HDAC_GCAP_ISS_SHIFT)␊ |
| 758 | #define HDAC_GCAP_OSS(gcap)␉␉␉␉␉␉\␊ |
| 759 | (((gcap) & HDAC_GCAP_OSS_MASK) >> HDAC_GCAP_OSS_SHIFT)␊ |
| 760 | #define HDAC_GCAP_NSDO(gcap)␉␉␉␉␉␉\␊ |
| 761 | (((gcap) & HDAC_GCAP_NSDO_MASK) >> HDAC_GCAP_NSDO_SHIFT)␊ |
| 762 | ␊ |
| 763 | /* GCTL - Global Control */␊ |
| 764 | #define HDAC_GCTL_CRST␉␉␉0x00000001␊ |
| 765 | #define HDAC_GCTL_FCNTRL␉␉0x00000002␊ |
| 766 | #define HDAC_GCTL_UNSOL␉␉␉0x00000100␊ |
| 767 | ␊ |
| 768 | /* WAKEEN - Wake Enable */␊ |
| 769 | #define HDAC_WAKEEN_SDIWEN_MASK␉␉0x7fff␊ |
| 770 | #define HDAC_WAKEEN_SDIWEN_SHIFT␉0␊ |
| 771 | ␊ |
| 772 | /* STATESTS - State Change Status */␊ |
| 773 | #define HDAC_STATESTS_SDIWAKE_MASK␉0x7fff␊ |
| 774 | #define HDAC_STATESTS_SDIWAKE_SHIFT␉0␊ |
| 775 | ␊ |
| 776 | #define HDAC_STATESTS_SDIWAKE(statests, n)␉␉␉␉\␊ |
| 777 | (((((statests) & HDAC_STATESTS_SDIWAKE_MASK) >>␉␉␉\␊ |
| 778 | HDAC_STATESTS_SDIWAKE_SHIFT) >> (n)) & 0x0001)␊ |
| 779 | ␊ |
| 780 | /* GSTS - Global Status */␊ |
| 781 | #define HDAC_GSTS_FSTS␉␉␉0x0002␊ |
| 782 | ␊ |
| 783 | /* INTCTL - Interrut Control */␊ |
| 784 | #define HDAC_INTCTL_SIE_MASK␉␉0x3fffffff␊ |
| 785 | #define HDAC_INTCTL_SIE_SHIFT␉␉0␊ |
| 786 | #define HDAC_INTCTL_CIE␉␉␉0x40000000␊ |
| 787 | #define HDAC_INTCTL_GIE␉␉␉0x80000000␊ |
| 788 | ␊ |
| 789 | /* INTSTS - Interrupt Status */␊ |
| 790 | #define HDAC_INTSTS_SIS_MASK␉␉0x3fffffff␊ |
| 791 | #define HDAC_INTSTS_SIS_SHIFT␉␉0␊ |
| 792 | #define HDAC_INTSTS_CIS␉␉␉0x40000000␊ |
| 793 | #define HDAC_INTSTS_GIS␉␉␉0x80000000␊ |
| 794 | ␊ |
| 795 | /* SSYNC - Stream Synchronization */␊ |
| 796 | #define HDAC_SSYNC_SSYNC_MASK␉␉0x3fffffff␊ |
| 797 | #define HDAC_SSYNC_SSYNC_SHIFT␉␉0␊ |
| 798 | ␊ |
| 799 | /* CORBWP - CORB Write Pointer */␊ |
| 800 | #define HDAC_CORBWP_CORBWP_MASK␉␉0x00ff␊ |
| 801 | #define HDAC_CORBWP_CORBWP_SHIFT␉0␊ |
| 802 | ␊ |
| 803 | /* CORBRP - CORB Read Pointer */␊ |
| 804 | #define HDAC_CORBRP_CORBRP_MASK␉␉0x00ff␊ |
| 805 | #define HDAC_CORBRP_CORBRP_SHIFT␉0␊ |
| 806 | #define HDAC_CORBRP_CORBRPRST␉␉0x8000␊ |
| 807 | ␊ |
| 808 | /* CORBCTL - CORB Control */␊ |
| 809 | #define HDAC_CORBCTL_CMEIE␉␉0x01␊ |
| 810 | #define HDAC_CORBCTL_CORBRUN␉␉0x02␊ |
| 811 | ␊ |
| 812 | /* CORBSTS - CORB Status */␊ |
| 813 | #define HDAC_CORBSTS_CMEI␉␉0x01␊ |
| 814 | ␊ |
| 815 | /* CORBSIZE - CORB Size */␊ |
| 816 | #define HDAC_CORBSIZE_CORBSIZE_MASK␉0x03␊ |
| 817 | #define HDAC_CORBSIZE_CORBSIZE_SHIFT␉0␊ |
| 818 | #define HDAC_CORBSIZE_CORBSZCAP_MASK␉0xf0␊ |
| 819 | #define HDAC_CORBSIZE_CORBSZCAP_SHIFT␉4␊ |
| 820 | ␊ |
| 821 | #define HDAC_CORBSIZE_CORBSIZE_2␉0x00␊ |
| 822 | #define HDAC_CORBSIZE_CORBSIZE_16␉0x01␊ |
| 823 | #define HDAC_CORBSIZE_CORBSIZE_256␉0x02␊ |
| 824 | ␊ |
| 825 | #define HDAC_CORBSIZE_CORBSZCAP_2␉0x10␊ |
| 826 | #define HDAC_CORBSIZE_CORBSZCAP_16␉0x20␊ |
| 827 | #define HDAC_CORBSIZE_CORBSZCAP_256␉0x40␊ |
| 828 | ␊ |
| 829 | #define HDAC_CORBSIZE_CORBSIZE(corbsize)␉␉␉␉\␊ |
| 830 | (((corbsize) & HDAC_CORBSIZE_CORBSIZE_MASK) >> HDAC_CORBSIZE_CORBSIZE_SHIFT)␊ |
| 831 | ␊ |
| 832 | /* RIRBWP - RIRB Write Pointer */␊ |
| 833 | #define HDAC_RIRBWP_RIRBWP_MASK␉␉0x00ff␊ |
| 834 | #define HDAC_RIRBWP_RIRBWP_SHIFT␉0␊ |
| 835 | #define HDAC_RIRBWP_RIRBWPRST␉␉0x8000␊ |
| 836 | ␊ |
| 837 | /* RINTCTN - Response Interrupt Count */␊ |
| 838 | #define HDAC_RINTCNT_MASK␉␉0x00ff␊ |
| 839 | #define HDAC_RINTCNT_SHIFT␉␉0␊ |
| 840 | ␊ |
| 841 | /* RIRBCTL - RIRB Control */␊ |
| 842 | #define HDAC_RIRBCTL_RINTCTL␉␉0x01␊ |
| 843 | #define HDAC_RIRBCTL_RIRBDMAEN␉␉0x02␊ |
| 844 | #define HDAC_RIRBCTL_RIRBOIC␉␉0x04␊ |
| 845 | ␊ |
| 846 | /* RIRBSTS - RIRB Status */␊ |
| 847 | #define HDAC_RIRBSTS_RINTFL␉␉0x01␊ |
| 848 | #define HDAC_RIRBSTS_RIRBOIS␉␉0x04␊ |
| 849 | ␊ |
| 850 | /* RIRBSIZE - RIRB Size */␊ |
| 851 | #define HDAC_RIRBSIZE_RIRBSIZE_MASK␉0x03␊ |
| 852 | #define HDAC_RIRBSIZE_RIRBSIZE_SHIFT␉0␊ |
| 853 | #define HDAC_RIRBSIZE_RIRBSZCAP_MASK␉0xf0␊ |
| 854 | #define HDAC_RIRBSIZE_RIRBSZCAP_SHIFT␉4␊ |
| 855 | ␊ |
| 856 | #define HDAC_RIRBSIZE_RIRBSIZE_2␉0x00␊ |
| 857 | #define HDAC_RIRBSIZE_RIRBSIZE_16␉0x01␊ |
| 858 | #define HDAC_RIRBSIZE_RIRBSIZE_256␉0x02␊ |
| 859 | ␊ |
| 860 | #define HDAC_RIRBSIZE_RIRBSZCAP_2␉0x10␊ |
| 861 | #define HDAC_RIRBSIZE_RIRBSZCAP_16␉0x20␊ |
| 862 | #define HDAC_RIRBSIZE_RIRBSZCAP_256␉0x40␊ |
| 863 | ␊ |
| 864 | #define HDAC_RIRBSIZE_RIRBSIZE(rirbsize)␉␉␉␉\␊ |
| 865 | (((rirbsize) & HDAC_RIRBSIZE_RIRBSIZE_MASK) >> HDAC_RIRBSIZE_RIRBSIZE_SHIFT)␊ |
| 866 | ␊ |
| 867 | /* DPLBASE - DMA Position Lower Base Address */␊ |
| 868 | #define HDAC_DPLBASE_DPLBASE_MASK␉0xffffff80␊ |
| 869 | #define HDAC_DPLBASE_DPLBASE_SHIFT␉7␊ |
| 870 | #define HDAC_DPLBASE_DPLBASE_DMAPBE␉0x00000001␊ |
| 871 | ␊ |
| 872 | /* SDCTL - Stream Descriptor Control */␊ |
| 873 | #define HDAC_SDCTL_SRST␉␉␉0x000001␊ |
| 874 | #define HDAC_SDCTL_RUN␉␉␉0x000002␊ |
| 875 | #define HDAC_SDCTL_IOCE␉␉␉0x000004␊ |
| 876 | #define HDAC_SDCTL_FEIE␉␉␉0x000008␊ |
| 877 | #define HDAC_SDCTL_DEIE␉␉␉0x000010␊ |
| 878 | #define HDAC_SDCTL2_STRIPE_MASK␉␉0x03␊ |
| 879 | #define HDAC_SDCTL2_STRIPE_SHIFT␉0␊ |
| 880 | #define HDAC_SDCTL2_TP␉␉␉0x04␊ |
| 881 | #define HDAC_SDCTL2_DIR␉␉␉0x08␊ |
| 882 | #define HDAC_SDCTL2_STRM_MASK␉␉0xf0␊ |
| 883 | #define HDAC_SDCTL2_STRM_SHIFT␉␉4␊ |
| 884 | ␊ |
| 885 | #define HDAC_SDSTS_DESE␉␉␉(1 << 4)␊ |
| 886 | #define HDAC_SDSTS_FIFOE␉␉(1 << 3)␊ |
| 887 | #define HDAC_SDSTS_BCIS␉␉␉(1 << 2)␊ |
| 888 | ␊ |
| 889 | /****************************************************************************␊ |
| 890 | * Helper Macros␊ |
| 891 | ****************************************************************************/␊ |
| 892 | ␊ |
| 893 | #define HDA_DMA_ALIGNMENT 128␊ |
| 894 | ␊ |
| 895 | #define HDA_BDL_MIN 2␊ |
| 896 | #define HDA_BDL_MAX 256␊ |
| 897 | #define HDA_BDL_DEFAULT HDA_BDL_MIN␊ |
| 898 | ␊ |
| 899 | #define HDA_BLK_MIN HDA_DMA_ALIGNMENT␊ |
| 900 | #define HDA_BLK_ALIGN (~(HDA_BLK_MIN - 1))␊ |
| 901 | ␊ |
| 902 | #define HDA_BUFSZ_MIN (HDA_BDL_MIN * HDA_BLK_MIN)␊ |
| 903 | #define HDA_BUFSZ_MAX 262144␊ |
| 904 | #define HDA_BUFSZ_DEFAULT 65536␊ |
| 905 | ␊ |
| 906 | #define HDA_GPIO_MAX 8␊ |
| 907 | ␊ |
| 908 | #define HDA_DEV_MATCH(fl, v) ((fl) == (v) || \␊ |
| 909 | (fl) == 0xffffffff || \␊ |
| 910 | (((fl) & 0xffff0000) == 0xffff0000 && \␊ |
| 911 | ((fl) & 0x0000ffff) == ((v) & 0x0000ffff)) || \␊ |
| 912 | (((fl) & 0x0000ffff) == 0x0000ffff && \␊ |
| 913 | ((fl) & 0xffff0000) == ((v) & 0xffff0000)))␊ |
| 914 | ␊ |
| 915 | #define HDA_MATCH_ALL 0xffffffff␊ |
| 916 | #define HDA_INVALID 0xffffffff␊ |
| 917 | ␊ |
| 918 | #define HDA_BOOTVERBOSE(stmt) do { \␊ |
| 919 | if (bootverbose != 0 || snd_verbose > 3) { \␊ |
| 920 | stmt \␊ |
| 921 | } \␊ |
| 922 | } while (0)␊ |
| 923 | ␊ |
| 924 | #define HDA_BOOTHVERBOSE(stmt) do { \␊ |
| 925 | if (snd_verbose > 3) { \␊ |
| 926 | stmt \␊ |
| 927 | } \␊ |
| 928 | } while (0)␊ |
| 929 | ␊ |
| 930 | #define hda_command(dev, verb) \␊ |
| 931 | HDAC_CODEC_COMMAND(device_get_parent(dev), (dev), (verb))␊ |
| 932 | ␊ |
| 933 | extern void probe_hda_bus(uint32_t pci_addr);␊ |
| 934 | ␊ |
| 935 | #endif /* !__LIBSAIO_HDA_H */␊ |
| 936 | |
