Chameleon

Chameleon Svn Source Tree

Root/trunk/i386/libsaio/nvidia.c

1/*
2 *NVidia injector
3 *
4 *Copyright (C) 2009Jasmin Fazlic, iNDi
5 *
6 *NVidia injector modified by Fabio (ErmaC) on May 2012,
7 *for allow the cosmetics injection also based on SubVendorID and SubDeviceID.
8 *
9 *NVidia injector is free software: you can redistribute it and/or modify
10 *it under the terms of the GNU General Public License as published by
11 *the Free Software Foundation, either version 3 of the License, or
12 *(at your option) any later version.
13 *
14 *NVidia driver and injector is distributed in the hope that it will be useful,
15 *but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 *GNU General Public License for more details.
18 *
19 *You should have received a copy of the GNU General Public License
20 *along with NVidia injector. If not, see <http://www.gnu.org/licenses/>.
21 *
22 *Alternatively you can choose to comply with APSL
23 *
24 *DCB-Table parsing is based on software (nouveau driver) originally distributed under following license:
25 *
26 *
27 *Copyright 2005-2006 Erik Waling
28 *Copyright 2006 Stephane Marchesin
29 *Copyright 2007-2009 Stuart Bennett
30 *
31 *Permission is hereby granted, free of charge, to any person obtaining a
32 *copy of this software and associated documentation files (the "Software"),
33 *to deal in the Software without restriction, including without limitation
34 *the rights to use, copy, modify, merge, publish, distribute, sublicense,
35 *and/or sell copies of the Software, and to permit persons to whom the
36 *Software is furnished to do so, subject to the following conditions:
37 *
38 *The above copyright notice and this permission notice shall be included in
39 *all copies or substantial portions of the Software.
40 *
41 *THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
42 *IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43 *FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
44 *THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
45 *WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
46 *OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
47 *SOFTWARE.
48 */
49
50#include "boot.h"
51#include "bootstruct.h"
52#include "pci.h"
53#include "platform.h"
54#include "device_inject.h"
55#include "nvidia.h"
56#include "nvidia_helper.h"
57
58#ifndef DEBUG_NVIDIA
59#define DEBUG_NVIDIA 0
60#endif
61
62#if DEBUG_NVIDIA
63#define DBG(x...)printf(x)
64#else
65#define DBG(x...)
66#endif
67
68#define NVIDIA_ROM_SIZE0x20000
69#define PATCH_ROM_SUCCESS1
70#define PATCH_ROM_SUCCESS_HAS_LVDS2
71#define PATCH_ROM_FAILED0
72#define MAX_NUM_DCB_ENTRIES16
73#define TYPE_GROUPED0xff
74#define READ_BYTE(rom, offset) (*(u_char *)(rom + offset))
75#define READ_LE_SHORT(rom, offset) (READ_BYTE(rom, offset+1) << 8 | READ_BYTE(rom, offset))
76#define READ_LE_INT(rom, offset) (READ_LE_SHORT(rom, offset+2) << 16 | READ_LE_SHORT(rom, offset))
77#define WRITE_LE_SHORT(data) (((data) << 8 & 0xff00) | ((data) >> 8 & 0x00ff ))
78#define WRITE_LE_INT(data) (WRITE_LE_SHORT(data) << 16 | WRITE_LE_SHORT(data >> 16))
79
80static bool showGeneric = false;
81char generic_name[128];
82extern uint32_t devices_number;
83
84const char *nvidia_compatible_0[] ={ "@0,compatible","NVDA,NVMac" };
85const char *nvidia_compatible_1[] ={ "@1,compatible","NVDA,NVMac" };
86const char *nvidia_device_type_0[] ={ "@0,device_type","display" };
87const char *nvidia_device_type_1[] ={ "@1,device_type","display" };
88const char *nvidia_device_type_parent[] ={ "device_type","NVDA,Parent" };
89const char *nvidia_device_type_child[]={ "device_type","NVDA,Child" };
90const char *nvidia_name_0[] ={ "@0,name","NVDA,Display-A" };
91const char *nvidia_name_1[] ={ "@1,name","NVDA,Display-B" };
92const char *nvidia_slot_name[] ={ "AAPL,slot-name", "Slot-1" };
93
94static uint8_t default_NVCAP[]= {
950x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
960x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
970x00, 0x00, 0x00, 0x00
98};
99
100#define NVCAP_LEN ( sizeof(default_NVCAP) / sizeof(uint8_t) )
101
102static uint8_t default_dcfg_0[]={0x03, 0x01, 0x03, 0x00};
103static uint8_t default_dcfg_1[]={0xff, 0xff, 0x00, 0x01};
104
105#define DCFG0_LEN ( sizeof(default_dcfg_0) / sizeof(uint8_t) )
106#define DCFG1_LEN ( sizeof(default_dcfg_1) / sizeof(uint8_t) )
107
108static uint8_t default_NVPM[]= {
1090x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1100x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1110x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1120x00, 0x00, 0x00, 0x00
113};
114
115#define NVPM_LEN ( sizeof(default_NVPM) / sizeof(uint8_t) )
116
117static nvidia_pci_info_t nvidia_card_vendors[] = {
118{ 0x10190000,"Elitegroup" },
119{ 0x10250000,"Acer" },
120{ 0x10280000,"Dell" },
121{ 0x10330000,"NEC" },
122{ 0x103C0000,"HP" },
123{ 0x10430000,"Asus" },
124{ 0x104D0000,"Sony" },
125{ 0x105B0000,"Foxconn" },
126{ 0x106B0000,"Apple" },
127{ 0x10710000,"Mitac" },
128{ 0x107B0000,"Gateway" },
129{ 0x107D0000,"Leadtek" },
130{ 0x109F0000,"Trigem" },
131{ 0x10B00000,"Gainward" },
132{ 0x10CF0000,"Fujitsu" },
133{ 0x10DE0000,"nVidia" },
134{ 0x11790000,"Toshiba" },
135{ 0x12970000,"Shuttle" },
136{ 0x13DC0000,"Netbost" },
137{ 0x144D0000,"Samsung" },
138{ 0x14580000,"Gigabyte" },
139{ 0x14620000,"MSi" },
140{ 0x14C00000,"Compal" },
141{ 0x152D0000,"Quanta" },
142{ 0x15540000,"Prolink" },
143{ 0x15580000,"Clevo" },
144{ 0x15690000,"Palit" },
145{ 0x161F0000,"Arima" },
146 { 0x16310000,"NEC" },
147{ 0x16420000,"Bitland" },
148{ 0x16820000,"XFX" },
149{ 0x17340000,"Fujitsu" },
150{ 0x174B0000,"PC Partner" },
151{ 0x17AA0000,"Lenovo" },
152 { 0x17C00000,"Wistron" },
153{ 0x17FF0000,"Benq" },
154{ 0x18490000,"ASRock" },
155{ 0x18540000,"LG" },
156{ 0x18640000,"LG" },
157{ 0x18940000,"LG" },
158{ 0x19610000,"ESS" },
159{ 0x196E0000,"PNY" },
160{ 0x19910000,"Topstar" },
161{ 0x19DA0000,"Zotac" },
162{ 0x19F10000,"BFG" },
163{ 0x1ACC0000,"Point of View" },
164{ 0x1B0A0000,"Pegatron" },
165{ 0x1B130000,"Jaton" },
166{ 0x34420000,"Bihl" },
167{ 0x38420000,"EVGA" },
168{ 0x73770000,"Colorful" },
169};
170
171static nvidia_pci_info_t nvidia_card_generic[] = {
172// 0000 - 0040
173{ 0x10DE0000,"Unknown" },
174// 0040 - 004F
175{ 0x10DE0040,"GeForce 6800 Ultra" },
176{ 0x10DE0041,"GeForce 6800" },
177{ 0x10DE0042,"GeForce 6800 LE" },
178{ 0x10DE0043,"GeForce 6800 XE" },
179{ 0x10DE0044,"GeForce 6800 XT" },
180{ 0x10DE0045,"GeForce 6800 GT" },
181{ 0x10DE0046,"GeForce 6800 GT" },
182{ 0x10DE0047,"GeForce 6800 GS" },
183{ 0x10DE0048,"GeForce 6800 XT" },
184{ 0x10DE004D,"Quadro FX 3400" },
185{ 0x10DE004E,"Quadro FX 4000" },
186// 0050 - 005F
187// 0060 - 006F
188// 0070 - 007F
189// 0080 - 008F
190// 0090 - 009F
191{ 0x10DE0090,"GeForce 7800 GTX" },
192{ 0x10DE0091,"GeForce 7800 GTX" },
193{ 0x10DE0092,"GeForce 7800 GT" },
194{ 0x10DE0093,"GeForce 7800 GS" },
195{ 0x10DE0095,"GeForce 7800 SLI" },
196{ 0x10DE0098,"GeForce Go 7800" },
197{ 0x10DE0099,"GeForce Go 7800 GTX" },
198{ 0x10DE009D,"Quadro FX 4500" },
199// 00A0 - 00AF
200// 00B0 - 00BF
201// 00C0 - 00CF
202{ 0x10DE00C0,"GeForce 6800 GS" },
203{ 0x10DE00C1,"GeForce 6800" },
204{ 0x10DE00C2,"GeForce 6800 LE" },
205{ 0x10DE00C3,"GeForce 6800 XT" },
206{ 0x10DE00C8,"GeForce Go 6800" },
207{ 0x10DE00C9,"GeForce Go 6800 Ultra" },
208{ 0x10DE00CC,"Quadro FX Go1400" },
209{ 0x10DE00CD,"Quadro FX 3450/4000 SDI" },
210{ 0x10DE00CE,"Quadro FX 1400" },
211// 00D0 - 00DF
212// 00E0 - 00EF
213// 00F0 - 00FF
214{ 0x10DE00F1,"GeForce 6600 GT" },
215{ 0x10DE00F2,"GeForce 6600" },
216{ 0x10DE00F3,"GeForce 6200" },
217{ 0x10DE00F4,"GeForce 6600 LE" },
218{ 0x10DE00F5,"GeForce 7800 GS" },
219{ 0x10DE00F6,"GeForce 6800 GS/XT" },
220{ 0x10DE00F8,"Quadro FX 3400/4400" },
221{ 0x10DE00F9,"GeForce 6800 Series GPU" },
222// 0100 - 010F
223// 0110 - 011F
224// 0120 - 012F
225// 0130 - 013F
226// 0140 - 014F
227{ 0x10DE0140,"GeForce 6600 GT" },
228{ 0x10DE0141,"GeForce 6600" },
229{ 0x10DE0142,"GeForce 6600 LE" },
230{ 0x10DE0143,"GeForce 6600 VE" },
231{ 0x10DE0144,"GeForce Go 6600" },
232{ 0x10DE0145,"GeForce 6610 XL" },
233{ 0x10DE0146,"GeForce Go 6600 TE/6200 TE" },
234{ 0x10DE0147,"GeForce 6700 XL" },
235{ 0x10DE0148,"GeForce Go 6600" },
236{ 0x10DE0149,"GeForce Go 6600 GT" },
237{ 0x10DE014A,"Quadro NVS 440" },
238{ 0x10DE014C,"Quadro FX 550" },
239{ 0x10DE014D,"Quadro FX 550" },
240{ 0x10DE014E,"Quadro FX 540" },
241{ 0x10DE014F,"GeForce 6200" },
242// 0150 - 015F
243// 0160 - 016F
244{ 0x10DE0160,"GeForce 6500" },
245{ 0x10DE0161,"GeForce 6200 TurboCache(TM)" },
246{ 0x10DE0162,"GeForce 6200SE TurboCache(TM)" },
247{ 0x10DE0163,"GeForce 6200 LE" },
248{ 0x10DE0164,"GeForce Go 6200" },
249{ 0x10DE0165,"Quadro NVS 285" },
250{ 0x10DE0166,"GeForce Go 6400" },
251{ 0x10DE0167,"GeForce Go 6200" },
252{ 0x10DE0168,"GeForce Go 6400" },
253{ 0x10DE0169,"GeForce 6250" },
254{ 0x10DE016A,"GeForce 7100 GS" },
255{ 0x10DE016C,"NVIDIA NV44GLM" },
256{ 0x10DE016D,"NVIDIA NV44GLM" },
257// 0170 - 017F
258// 0180 - 018F
259// 0190 - 019F
260{ 0x10DE0191,"GeForce 8800 GTX" },
261{ 0x10DE0193,"GeForce 8800 GTS" },
262{ 0x10DE0194,"GeForce 8800 Ultra" },
263{ 0x10DE0197,"Tesla C870" },
264{ 0x10DE019D,"Quadro FX 5600" },
265{ 0x10DE019E,"Quadro FX 4600" },
266// 01A0 - 01AF
267// 01B0 - 01BF
268// 01C0 - 01CF
269// 01D0 - 01DF
270{ 0x10DE01D0,"GeForce 7350 LE" },
271{ 0x10DE01D1,"GeForce 7300 LE" },
272{ 0x10DE01D2,"GeForce 7550 LE" },
273{ 0x10DE01D3,"GeForce 7300 SE/7200 GS" },
274{ 0x10DE01D6,"GeForce Go 7200" },
275{ 0x10DE01D7,"GeForce Go 7300" },
276{ 0x10DE01D8,"GeForce Go 7400" },
277{ 0x10DE01D9,"GeForce Go 7450" },
278{ 0x10DE01DA,"Quadro NVS 110M" },
279{ 0x10DE01DB,"Quadro NVS 120M" },
280{ 0x10DE01DC,"Quadro FX 350M" },
281{ 0x10DE01DD,"GeForce 7500 LE" },
282{ 0x10DE01DE,"Quadro FX 350" },
283{ 0x10DE01DF,"GeForce 7300 GS" },
284// 01E0 - 01EF
285// 01F0 - 01FF
286{ 0x10DE01F0,"GeForce4 MX" },
287// 0200 - 020F
288// 0210 - 021F
289{ 0x10DE0211,"GeForce 6800" },
290{ 0x10DE0212,"GeForce 6800 LE" },
291{ 0x10DE0215,"GeForce 6800 GT" },
292{ 0x10DE0218,"GeForce 6800 XT" },
293// 0220 - 022F
294{ 0x10DE0221,"GeForce 6200" },
295{ 0x10DE0222,"GeForce 6200 A-LE" },
296{ 0x10DE0228,"NVIDIA NV44M" },
297// 0230 - 023F
298// 0240 - 024F
299{ 0x10DE0240,"GeForce 6150" },
300{ 0x10DE0241,"GeForce 6150 LE" },
301{ 0x10DE0242,"GeForce 6100" },
302{ 0x10DE0243,"NVIDIA C51" },
303{ 0x10DE0244,"GeForce Go 6150" },
304{ 0x10DE0245,"Quadro NVS 210S / GeForce 6150LE" },
305{ 0x10DE0247,"GeForce Go 6100" },
306// 0250 - 025F
307{ 0x10DE025B,"Quadro4 700 XGL" },
308// 0260 - 026F
309// 0270 - 027F
310// 0280 - 028F
311// 0290 - 029F
312{ 0x10DE0290,"GeForce 7900 GTX" },
313{ 0x10DE0291,"GeForce 7900 GT/GTO" },
314{ 0x10DE0292,"GeForce 7900 GS" },
315{ 0x10DE0293,"GeForce 7950 GX2" },
316{ 0x10DE0294,"GeForce 7950 GX2" },
317{ 0x10DE0295,"GeForce 7950 GT" },
318{ 0x10DE0298,"GeForce Go 7900 GS" },
319{ 0x10DE0299,"GeForce Go 7900 GTX" },
320{ 0x10DE029A,"Quadro FX 2500M" },
321{ 0x10DE029B,"Quadro FX 1500M" },
322{ 0x10DE029C,"Quadro FX 5500" },
323{ 0x10DE029D,"Quadro FX 3500" },
324{ 0x10DE029E,"Quadro FX 1500" },
325{ 0x10DE029F,"Quadro FX 4500 X2" },
326// 02A0 - 02AF
327// 02B0 - 02BF
328// 02C0 - 02CF
329// 02D0 - 02DF
330// 02E0 - 02EF
331{ 0x10DE02E0,"GeForce 7600 GT" },
332{ 0x10DE02E1,"GeForce 7600 GS" },
333{ 0x10DE02E2,"GeForce 7300 GT" },
334{ 0x10DE02E3,"GeForce 7900 GS" },
335{ 0x10DE02E4,"GeForce 7950 GT" },
336// 02F0 - 02FF
337// 0300 - 030F
338{ 0x10DE0301,"GeForce FX 5800 Ultra" },
339{ 0x10DE0302,"GeForce FX 5800" },
340{ 0x10DE0308,"Quadro FX 2000" },
341{ 0x10DE0309,"Quadro FX 1000" },
342// 0310 - 031F
343{ 0x10DE0311,"GeForce FX 5600 Ultra" },
344{ 0x10DE0312,"GeForce FX 5600" },
345{ 0x10DE0314,"GeForce FX 5600XT" },
346{ 0x10DE031A,"GeForce FX Go5600" },
347{ 0x10DE031B,"GeForce FX Go5650" },
348{ 0x10DE031C,"Quadro FX Go700" },
349// 0320 - 032F
350{ 0x10DE0320,"GeForce FX 5200" },
351{ 0x10DE0321,"GeForce FX 5200 Ultra" },
352{ 0x10DE0322,"GeForce FX 5200" },
353{ 0x10DE0323,"GeForce FX 5200 LE" },
354{ 0x10DE0324,"GeForce FX Go5200" },
355{ 0x10DE0325,"GeForce FX Go5250" },
356{ 0x10DE0326,"GeForce FX 5500" },
357{ 0x10DE0328,"GeForce FX Go5200 32M/64M" },
358{ 0x10DE0329,"GeForce FX Go5200" },
359{ 0x10DE032A,"Quadro NVS 55/280 PCI" },
360{ 0x10DE032B,"Quadro FX 500/600 PCI" },
361{ 0x10DE032C,"GeForce FX Go53xx Series" },
362{ 0x10DE032D,"GeForce FX Go5100" },
363{ 0x10DE032F,"NV34GL" },
364// 0330 - 033F
365{ 0x10DE0330,"GeForce FX 5900 Ultra" },
366{ 0x10DE0331,"GeForce FX 5900" },
367{ 0x10DE0332,"GeForce FX 5900XT" },
368{ 0x10DE0333,"GeForce FX 5950 Ultra" },
369{ 0x10DE0334,"GeForce FX 5900ZT" },
370{ 0x10DE0338,"Quadro FX 3000" },
371{ 0x10DE033F,"Quadro FX 700" },
372// 0340 - 034F
373{ 0x10DE0341,"GeForce FX 5700 Ultra" },
374{ 0x10DE0342,"GeForce FX 5700" },
375{ 0x10DE0343,"GeForce FX 5700LE" },
376{ 0x10DE0344,"GeForce FX 5700VE" },
377{ 0x10DE0345,"NV36.5" },
378{ 0x10DE0347,"GeForce FX Go5700" },
379{ 0x10DE0348,"GeForce FX Go5700" },
380{ 0x10DE0349,"NV36M Pro" },
381{ 0x10DE034B,"NV36MAP" },
382{ 0x10DE034C,"Quadro FX Go1000" },
383{ 0x10DE034E,"Quadro FX 1100" },
384{ 0x10DE034F,"NV36GL" },
385// 0350 - 035F
386// 0360 - 036F
387// 0370 - 037F
388// 0380 - 038F
389{ 0x10DE038B,"GeForce 7650 GS" },
390// 0390 - 039F
391{ 0x10DE0390,"GeForce 7650 GS" },
392{ 0x10DE0391,"GeForce 7600 GT" },
393{ 0x10DE0392,"GeForce 7600 GS" },
394{ 0x10DE0393,"GeForce 7300 GT" },
395{ 0x10DE0394,"GeForce 7600 LE" },
396{ 0x10DE0395,"GeForce 7300 GT" },
397{ 0x10DE0397,"GeForce Go 7700" },
398{ 0x10DE0398,"GeForce Go 7600" },
399{ 0x10DE0399,"GeForce Go 7600 GT"},
400{ 0x10DE039A,"Quadro NVS 300M" },
401{ 0x10DE039B,"GeForce Go 7900 SE" },
402{ 0x10DE039C,"Quadro FX 560M" },
403{ 0x10DE039E,"Quadro FX 560" },
404// 03A0 - 03AF
405// 03B0 - 03BF
406// 03C0 - 03CF
407// 03D0 - 03DF
408{ 0x10DE03D0,"GeForce 6150SE nForce 430" },
409{ 0x10DE03D1,"GeForce 6100 nForce 405" },
410{ 0x10DE03D2,"GeForce 6100 nForce 400" },
411{ 0x10DE03D5,"GeForce 6100 nForce 420" },
412{ 0x10DE03D6,"GeForce 7025 / nForce 630a" },
413// 03E0 - 03EF
414// 03F0 - 03FF
415// 0400 - 040F
416{ 0x10DE0400,"GeForce 8600 GTS" },
417{ 0x10DE0401,"GeForce 8600 GT" },
418{ 0x10DE0402,"GeForce 8600 GT" },
419{ 0x10DE0403,"GeForce 8600 GS" },
420{ 0x10DE0404,"GeForce 8400 GS" },
421{ 0x10DE0405,"GeForce 9500M GS" },
422{ 0x10DE0406,"GeForce 8300 GS" },
423{ 0x10DE0407,"GeForce 8600M GT" },
424{ 0x10DE0408,"GeForce 9650M GS" },
425{ 0x10DE0409,"GeForce 8700M GT" },
426{ 0x10DE040A,"Quadro FX 370" },
427{ 0x10DE040B,"Quadro NVS 320M" },
428{ 0x10DE040C,"Quadro FX 570M" },
429{ 0x10DE040D,"Quadro FX 1600M" },
430{ 0x10DE040E,"Quadro FX 570" },
431{ 0x10DE040F,"Quadro FX 1700" },
432// 0410 - 041F
433{ 0x10DE0410,"GeForce GT 330" },
434// 0420 - 042F
435{ 0x10DE0420,"GeForce 8400 SE" },
436{ 0x10DE0421,"GeForce 8500 GT" },
437{ 0x10DE0422,"GeForce 8400 GS" },
438{ 0x10DE0423,"GeForce 8300 GS" },
439{ 0x10DE0424,"GeForce 8400 GS" },
440{ 0x10DE0425,"GeForce 8600M GS" },
441{ 0x10DE0426,"GeForce 8400M GT" },
442{ 0x10DE0427,"GeForce 8400M GS" },
443{ 0x10DE0428,"GeForce 8400M G" },
444{ 0x10DE0429,"Quadro NVS 140M" },
445{ 0x10DE042A,"Quadro NVS 130M" },
446{ 0x10DE042B,"Quadro NVS 135M" },
447{ 0x10DE042C,"GeForce 9400 GT" },
448{ 0x10DE042D,"Quadro FX 360M" },
449{ 0x10DE042E,"GeForce 9300M G" },
450{ 0x10DE042F,"Quadro NVS 290" },
451// 0430 - 043F
452// 0440 - 044F
453// 0450 - 045F
454// 0460 - 046F
455// 0470 - 047F
456// 0480 - 048F
457// 0490 - 049F
458// 04A0 - 04AF
459// 04B0 - 04BF
460// 04C0 - 04CF
461{ 0x10DE04C0,"NVIDIA G78" },
462{ 0x10DE04C1,"NVIDIA G78" },
463{ 0x10DE04C2,"NVIDIA G78" },
464{ 0x10DE04C3,"NVIDIA G78" },
465{ 0x10DE04C4,"NVIDIA G78" },
466{ 0x10DE04C5,"NVIDIA G78" },
467{ 0x10DE04C6,"NVIDIA G78" },
468{ 0x10DE04C7,"NVIDIA G78" },
469{ 0x10DE04C8,"NVIDIA G78" },
470{ 0x10DE04C9,"NVIDIA G78" },
471{ 0x10DE04CA,"NVIDIA G78" },
472{ 0x10DE04CB,"NVIDIA G78" },
473{ 0x10DE04CC,"NVIDIA G78" },
474{ 0x10DE04CD,"NVIDIA G78" },
475{ 0x10DE04CE,"NVIDIA G78" },
476{ 0x10DE04CF,"NVIDIA G78" },
477// 04D0 - 04DF
478// 04E0 - 04EF
479// 04F0 - 04FF
480// 0500 - 050F
481// 0510 - 051F
482// 0520 - 052F
483// 0530 - 053F
484{ 0x10DE0530,"GeForce 7190M / nForce 650M" },
485{ 0x10DE0531,"GeForce 7150M / nForce 630M" },
486{ 0x10DE0533,"GeForce 7000M / nForce 610M" },
487{ 0x10DE053A,"GeForce 7050 PV / nForce 630a" },
488{ 0x10DE053B,"GeForce 7050 PV / nForce 630a" },
489{ 0x10DE053E,"GeForce 7025 / nForce 630a" },
490// 0540 - 054F
491// 0550 - 055F
492// 0560 - 056F
493// 0570 - 057F
494// 0580 - 058F
495// 0590 - 059F
496// 05A0 - 05AF
497// 05B0 - 05BF
498// 05C0 - 05CF
499// 05D0 - 05DF
500// 05E0 - 05EF
501{ 0x10DE05E0,"GeForce GTX 295" },
502{ 0x10DE05E1,"GeForce GTX 280" },
503{ 0x10DE05E2,"GeForce GTX 260" },
504{ 0x10DE05E3,"GeForce GTX 285" },
505{ 0x10DE05E4,"NVIDIA GT200" },
506{ 0x10DE05E5,"NVIDIA GT200" },
507{ 0x10DE05E6,"GeForce GTX 275" },
508{ 0x10DE05E7,"nVidia Tesla C1060" },
509{ 0x10DE05E8,"NVIDIA GT200" },
510{ 0x10DE05E9,"NVIDIA GT200" },
511{ 0x10DE05EA,"GeForce GTX 260" },
512{ 0x10DE05EB,"GeForce GTX 295" },
513{ 0x10DE05EC,"NVIDIA GT200" },
514{ 0x10DE05ED,"Quadroplex 2200 D2" },
515{ 0x10DE05EE,"NVIDIA GT200" },
516{ 0x10DE05EF,"NVIDIA GT200" },
517// 05F0 - 05FF
518{ 0x10DE05F0,"NVIDIA GT200" },
519{ 0x10DE05F1,"NVIDIA GT200" },
520{ 0x10DE05F2,"NVIDIA GT200" },
521{ 0x10DE05F3,"NVIDIA GT200" },
522{ 0x10DE05F4,"NVIDIA GT200" },
523{ 0x10DE05F5,"NVIDIA GT200" },
524{ 0x10DE05F6,"NVIDIA GT200" },
525{ 0x10DE05F7,"NVIDIA GT200" },
526{ 0x10DE05F8,"Quadroplex 2200 S4" },
527{ 0x10DE05F9,"NVIDIA Quadro CX" },
528{ 0x10DE05FA,"NVIDIA GT200" },
529{ 0x10DE05FB,"NVIDIA GT200" },
530{ 0x10DE05FC,"NVIDIA GT200" },
531{ 0x10DE05FD,"Quadro FX 5800" },
532{ 0x10DE05FE,"Quadro FX 4800" },
533{ 0x10DE05FF,"Quadro FX 3800" },
534// 0600 - 060F
535{ 0x10DE0600,"GeForce 8800 GTS" },
536{ 0x10DE0601,"GeForce 9800 GT" },
537{ 0x10DE0602,"GeForce 8800 GT" },
538{ 0x10DE0603,"GeForce GT 230" },
539{ 0x10DE0604,"GeForce 9800 GX2" },
540{ 0x10DE0605,"GeForce 9800 GT" },
541{ 0x10DE0606,"GeForce 8800 GS" },
542{ 0x10DE0607,"GeForce GTS 240" },
543{ 0x10DE0608,"GeForce 9800M GTX" },
544{ 0x10DE0609,"GeForce 8800M GTS" },
545{ 0x10DE060A,"GeForce GTX 280M" },
546{ 0x10DE060B,"GeForce 9800M GT" },
547{ 0x10DE060C,"GeForce 8800M GTX" },
548{ 0x10DE060D,"GeForce 8800 GS" },
549{ 0x10DE060F,"GeForce GTX 285M" },
550// 0610 - 061F
551{ 0x10DE0610,"GeForce 9600 GSO" },
552{ 0x10DE0611,"GeForce 8800 GT" },
553{ 0x10DE0612,"GeForce 9800 GTX" },
554{ 0x10DE0613,"GeForce 9800 GTX+" },
555{ 0x10DE0614,"GeForce 9800 GT" },
556{ 0x10DE0615,"GeForce GTS 250" },
557{ 0x10DE0617,"GeForce 9800M GTX" },
558{ 0x10DE0618,"GeForce GTX 260M" },
559{ 0x10DE0619,"Quadro FX 4700 X2" },
560{ 0x10DE061A,"Quadro FX 3700" },
561{ 0x10DE061B,"Quadro VX 200" },
562{ 0x10DE061C,"Quadro FX 3600M" },
563{ 0x10DE061D,"Quadro FX 2800M" },
564{ 0x10DE061E,"Quadro FX 3700M" },
565{ 0x10DE061F,"Quadro FX 3800M" },
566// 0620 - 062F
567{ 0x10DE0620,"NVIDIA G94" },
568{ 0x10DE0621,"GeForce GT 230" },
569{ 0x10DE0622,"GeForce 9600 GT" },
570{ 0x10DE0623,"GeForce 9600 GS" },
571{ 0x10DE0624,"NVIDIA G94" },
572{ 0x10DE0625,"GeForce 9600 GSO 512"},
573{ 0x10DE0626,"GeForce GT 130" },
574{ 0x10DE0627,"GeForce GT 140" },
575{ 0x10DE0628,"GeForce 9800M GTS" },
576{ 0x10DE0629,"NVIDIA G94" },
577{ 0x10DE062A,"GeForce 9700M GTS" },
578{ 0x10DE062B,"GeForce 9800M GS" },
579{ 0x10DE062C,"GeForce 9800M GTS" },
580{ 0x10DE062D,"GeForce 9600 GT" },
581{ 0x10DE062E,"GeForce 9600 GT" },
582{ 0x10DE062F,"GeForce 9800 S" },
583// 0630 - 063F
584{ 0x10DE0630,"GeForce 9700 S" },
585{ 0x10DE0631,"GeForce GTS 160M" },
586{ 0x10DE0632,"GeForce GTS 150M" },
587{ 0x10DE0633,"NVIDIA G94" },
588{ 0x10DE0634,"NVIDIA G94" },
589{ 0x10DE0635,"GeForce 9600 GSO" },
590{ 0x10DE0636,"NVIDIA G94" },
591{ 0x10DE0637,"GeForce 9600 GT" },
592{ 0x10DE0638,"Quadro FX 1800" },
593{ 0x10DE0639,"NVIDIA G94" },
594{ 0x10DE063A,"Quadro FX 2700M" },
595{ 0x10DE063B,"NVIDIA G94" },
596{ 0x10DE063C,"NVIDIA G94" },
597{ 0x10DE063D,"NVIDIA G94" },
598{ 0x10DE063E,"NVIDIA G94" },
599{ 0x10DE063F,"NVIDIA G94" },
600// 0640 - 064F
601{ 0x10DE0640,"GeForce 9500 GT" },
602{ 0x10DE0641,"GeForce 9400 GT" },
603{ 0x10DE0642,"GeForce 8400 GS" },
604{ 0x10DE0643,"GeForce 9500 GT" },
605{ 0x10DE0644,"GeForce 9500 GS" },
606{ 0x10DE0645,"GeForce 9500 GS" },
607{ 0x10DE0646,"GeForce GT 120" },
608{ 0x10DE0647,"GeForce 9600M GT" },
609{ 0x10DE0648,"GeForce 9600M GS" },
610{ 0x10DE0649,"GeForce 9600M GT" },
611{ 0x10DE064A,"GeForce 9700M GT" },
612{ 0x10DE064B,"GeForce 9500M G" },
613{ 0x10DE064C,"GeForce 9650M GT" },
614// 0650 - 065F
615{ 0x10DE0650,"NVIDIA G96-825" },
616{ 0x10DE0651,"GeForce G 110M" },
617{ 0x10DE0652,"GeForce GT 130M" },
618{ 0x10DE0653,"GeForce GT 120M" },
619{ 0x10DE0654,"GeForce GT 220M" },
620{ 0x10DE0655,"GeForce GT 120" },
621{ 0x10DE0656,"GeForce 9650 S" },
622{ 0x10DE0657,"NVIDIA G96" },
623{ 0x10DE0658,"Quadro FX 380" },
624{ 0x10DE0659,"Quadro FX 580" },
625{ 0x10DE065A,"Quadro FX 1700M" },
626{ 0x10DE065B,"GeForce 9400 GT" },
627{ 0x10DE065C,"Quadro FX 770M" },
628{ 0x10DE065D,"NVIDIA G96" },
629{ 0x10DE065E,"NVIDIA G96" },
630{ 0x10DE065F,"GeForce G210" },
631// 0660 - 066F
632// 0670 - 067F
633// 0680 - 068F
634// 0690 - 069F
635// 06A0 - 06AF
636{ 0x10DE06A0,"NVIDIA GT214" },
637// 06B0 - 06BF
638{ 0x10DE06B0,"NVIDIA GT214" },
639// 06C0 - 06CF
640{ 0x10DE06C0,"GeForce GTX 480" },
641{ 0x10DE06C3,"GeForce GTX D12U" },
642{ 0x10DE06C4,"GeForce GTX 465" },
643{ 0x10DE06CA,"GeForce GTX 480M" },
644{ 0x10DE06CD,"GeForce GTX 470" },
645// 06D0 - 06DF
646{ 0x10DE06D1,"Tesla C2050" },
647{ 0x10DE06D2,"Tesla M2070" },
648{ 0x10DE06D8,"Quadro 6000" },
649{ 0x10DE06D9,"Quadro 5000" },
650{ 0x10DE06DA,"Quadro 5000M" },
651{ 0x10DE06DC,"Quadro 6000" },
652{ 0x10DE06DD,"Quadro 4000" },
653{ 0x10DE06DE,"Tesla M2050" },
654{ 0x10DE06DF,"Tesla M2070-Q" },
655// 06E0 - 06EF
656{ 0x10DE06E0,"GeForce 9300 GE" },
657{ 0x10DE06E1,"GeForce 9300 GS" },
658{ 0x10DE06E2,"GeForce 8400" },
659{ 0x10DE06E3,"GeForce 8400 SE" },
660{ 0x10DE06E4,"GeForce 8400 GS" },
661{ 0x10DE06E5,"GeForce 9300M GS" },
662{ 0x10DE06E6,"GeForce G100" },
663{ 0x10DE06E7,"GeForce 9300 SE" },
664{ 0x10DE06E8,"GeForce 9200M GE" },
665{ 0x10DE06E9,"GeForce 9300M GS" },
666{ 0x10DE06EA,"Quadro NVS 150M" },
667{ 0x10DE06EB,"Quadro NVS 160M" },
668{ 0x10DE06EC,"GeForce G 105M" },
669{ 0x10DE06ED,"NVIDIA G98" },
670{ 0x10DE06EF,"GeForce G 103M" },
671// 06F0 - 06FF
672{ 0x10DE06F0,"NVIDIA G98" },
673{ 0x10DE06F1,"GeForce G105M" },
674{ 0x10DE06F2,"NVIDIA G98" },
675{ 0x10DE06F3,"NVIDIA G98" },
676{ 0x10DE06F4,"NVIDIA G98" },
677{ 0x10DE06F5,"NVIDIA G98" },
678{ 0x10DE06F6,"NVIDIA G98" },
679{ 0x10DE06F7,"NVIDIA G98" },
680{ 0x10DE06F8,"Quadro NVS 420" },
681{ 0x10DE06F9,"Quadro FX 370 LP" },
682{ 0x10DE06FA,"Quadro NVS 450" },
683{ 0x10DE06FB,"Quadro FX 370M" },
684{ 0x10DE06FC,"NVIDIA G98" },
685{ 0x10DE06FD,"Quadro NVS 295" },
686{ 0x10DE06FE,"NVIDIA G98" },
687{ 0x10DE06FF,"HICx16 + Graphics" },
688// 0700 - 070F
689// 0710 - 071F
690// 0720 - 072F
691// 0730 - 073F
692// 0740 - 074F
693// 0750 - 075F
694// 0760 - 076F
695// 0770 - 077F
696// 0780 - 078F
697// 0790 - 079F
698// 07A0 - 07AF
699// 07B0 - 07BF
700// 07C0 - 07CF
701// 07D0 - 07DF
702// 07E0 - 07EF
703{ 0x10DE07E0,"GeForce 7150 / nForce 630i" },
704{ 0x10DE07E1,"GeForce 7100 / nForce 630i" },
705{ 0x10DE07E2,"GeForce 7050 / nForce 630i" },
706{ 0x10DE07E3,"GeForce 7050 / nForce 610i" },
707{ 0x10DE07E5,"GeForce 7050 / nForce 620i" },
708// 07F0 - 07FF
709// 0800 - 080F
710// 0810 - 081F
711// 0820 - 082F
712// 0830 - 083F
713// 0840 - 084F
714{ 0x10DE0840,"GeForce 8200M" },
715{ 0x10DE0844,"GeForce 9100M G" },
716{ 0x10DE0845,"GeForce 8200M G" },
717{ 0x10DE0846,"GeForce 9200" },
718{ 0x10DE0847,"GeForce 9100" },
719{ 0x10DE0848,"GeForce 8300" },
720{ 0x10DE0849,"GeForce 8200" },
721{ 0x10DE084A,"nForce 730a" },
722{ 0x10DE084B,"GeForce 9200" },
723{ 0x10DE084C,"nForce 980a/780a SLI" },
724{ 0x10DE084D,"nForce 750a SLI" },
725{ 0x10DE084F,"GeForce 8100 / nForce 720a" },
726// 0850 - 085F
727// 0860 - 086F
728{ 0x10DE0860,"GeForce 9300" },
729{ 0x10DE0861,"GeForce 9400" },
730{ 0x10DE0862,"GeForce 9400M G" },
731{ 0x10DE0863,"GeForce 9400M" },
732{ 0x10DE0864,"GeForce 9300" },
733{ 0x10DE0865,"GeForce 9300" },
734{ 0x10DE0866,"GeForce 9400M G" },
735{ 0x10DE0867,"GeForce 9400" },
736{ 0x10DE0868,"nForce 760i SLI" },
737{ 0x10DE0869,"GeForce 9400" },
738{ 0x10DE086A,"GeForce 9400" },
739{ 0x10DE086C,"GeForce 9300 / nForce 730i" },
740{ 0x10DE086D,"GeForce 9200" },
741{ 0x10DE086E,"GeForce 9100M G" },
742{ 0x10DE086F,"GeForce 8200M G" },
743// 0870 - 087F
744{ 0x10DE0870,"GeForce 9400M" },
745{ 0x10DE0871,"GeForce 9200" },
746{ 0x10DE0872,"GeForce G102M" },
747{ 0x10DE0873,"GeForce G205M" },
748{ 0x10DE0874,"ION 9300M" },
749{ 0x10DE0876,"ION 9400M" },
750{ 0x10DE087A,"GeForce 9400" },
751{ 0x10DE087D,"ION 9400M" },
752{ 0x10DE087E,"ION LE" },
753{ 0x10DE087F,"ION LE" }, // Tesla M2070-Q ??
754// 0880 - 088F
755// 0890 - 089F
756// 08A0 - 08AF
757{ 0x10DE08A0,"GeForce 320M" },
758{ 0x10DE08A1,"MCP89-MZT" },
759{ 0x10DE08A2,"GeForce 320M" },
760{ 0x10DE08A3,"GeForce 320M" },
761{ 0x10DE08A4,"GeForce 320M" },
762{ 0x10DE08A5,"GeForce 320M" },
763// 08B0 - 08BF
764{ 0x10DE08B0,"MCP83 MMD" },
765{ 0x10DE08B1,"GeForce 300M" },
766{ 0x10DE08B2,"GeForce 300M" }, // MCP83-MJ
767{ 0x10DE08B3,"MCP89 MM9" },
768// 08C0 - 08CF
769// 08D0 - 08DF
770// 08E0 - 08EF
771// 08F0 - 08FF
772// 0900 - 090F
773// 0910 - 091F
774// 0920 - 092F
775// 0930 - 093F
776// 0940 - 094F
777// 0950 - 095F
778// 0960 - 096F
779// 0970 - 097F
780// 0980 - 098F
781// 0990 - 099F
782// 09A0 - 09AF
783// 09B0 - 09BF
784// 09C0 - 09CF
785// 09D0 - 09DF
786// 09E0 - 09EF
787// 09F0 - 09FF
788// 0A00 - 0A0F
789// { 0x10DE0A00,"NVIDIA GT212" },
790// 0A10 - 0A1F
791// { 0x10DE0A10,"NVIDIA GT212" },
792// 0A20 - 0A2F
793{ 0x10DE0A20,"GeForce GT 220" },
794{ 0x10DE0A21,"D10M2-20" },
795{ 0x10DE0A22,"GeForce 315" },
796{ 0x10DE0A23,"GeForce 210" },
797{ 0x10DE0A26,"GeForce 405" },
798{ 0x10DE0A27,"GeForce 405" },
799{ 0x10DE0A28,"GeForce GT 230" },
800{ 0x10DE0A29,"GeForce GT 330M" },
801{ 0x10DE0A2A,"GeForce GT 230M" },
802{ 0x10DE0A2B,"GeForce GT 330M" },
803{ 0x10DE0A2C,"NVS 5100M" },
804{ 0x10DE0A2D,"GeForce GT 320M" },
805// 0A30 - 0A3F
806{ 0x10DE0A30,"GeForce GT 330M" },
807{ 0x10DE0A32,"GeForce GT 415" },
808{ 0x10DE0A34,"GeForce GT 240M" },
809{ 0x10DE0A35,"GeForce GT 325M" },
810{ 0x10DE0A38,"Quadro 400" },
811{ 0x10DE0A3C,"Quadro FX 880M" },
812{ 0x10DE0A3D,"N10P-ES" },
813{ 0x10DE0A3F,"GT216-INT" },
814// 0A40 - 0A4F
815// 0A50 - 0A5F
816// 0A60 - 0A6F
817{ 0x10DE0A60,"GeForce G210" },
818{ 0x10DE0A61,"NVS 2100" },
819{ 0x10DE0A62,"GeForce 205" },
820{ 0x10DE0A63,"GeForce 310" },
821{ 0x10DE0A64,"ION" },
822{ 0x10DE0A65,"GeForce 210" },
823{ 0x10DE0A66,"GeForce 310" },
824{ 0x10DE0A67,"GeForce 315" },
825{ 0x10DE0A68,"GeForce G105M" },
826{ 0x10DE0A69,"GeForce G105M" },
827{ 0x10DE0A6A,"NVS 2100M" },
828{ 0x10DE0A6C,"NVS 3100M" },
829{ 0x10DE0A6E,"GeForce 305M" },
830{ 0x10DE0A6F,"ION" },
831// 0A70 - 0A7F
832{ 0x10DE0A70,"GeForce 310M" },
833{ 0x10DE0A71,"GeForce 305M" },
834{ 0x10DE0A72,"GeForce 310M" },
835{ 0x10DE0A73,"GeForce 305M" },
836{ 0x10DE0A74,"GeForce G210M" },
837{ 0x10DE0A75,"GeForce G310M" },
838{ 0x10DE0A76,"ION" },
839{ 0x10DE0A78,"Quadro FX 380 LP" },
840// { 0x10DE0A79,"N12M-NS-S" },
841{ 0x10DE0A7A,"GeForce 315M" },
842{ 0x10DE0A7B,"GeForce 505" },
843{ 0x10DE0A7C,"Quadro FX 380M" },
844{ 0x10DE0A7D,"N11M-ES" }, //SUBIDS
845{ 0x10DE0A7E,"GT218-INT-S" },
846{ 0x10DE0A7F,"GT218-INT-B" },
847// 0A80 - 0A8F
848// 0A90 - 0A9F
849// 0AA0 - 0AAF
850// 0AB0 - 0ABF
851// 0AC0 - 0ACF
852// 0AD0 - 0ADF
853// 0AE0 - 0AEF
854// 0AF0 - 0AFF
855// 0B00 - 0B0F
856// 0B10 - 0B1F
857// 0B20 - 0B2F
858// 0B30 - 0B3F
859// 0B40 - 0B4F
860// 0B50 - 0B5F
861// 0B60 - 0B6F
862// 0B70 - 0B7F
863// 0B80 - 0B8F
864// 0B90 - 0B9F
865// 0BA0 - 0BAF
866// 0BB0 - 0BBF
867// 0BC0 - 0BCF
868// 0BD0 - 0BDF
869// 0BE0 - 0BEF
870// 0BF0 - 0BFF
871// 0C00 - 0C0F
872// 0C10 - 0C1F
873// 0C20 - 0C2F
874// 0C30 - 0C3F
875// 0C40 - 0C4F
876// 0C50 - 0C5F
877// 0C60 - 0C6F
878// 0C70 - 0C7F
879// 0C80 - 0C8F
880// 0C90 - 0C9F
881// 0CA0 - 0CAF
882{ 0x10DE0CA0,"GeForce GT 330 " },
883{ 0x10DE0CA2,"GeForce GT 320" },
884{ 0x10DE0CA3,"GeForce GT 240" },
885{ 0x10DE0CA4,"GeForce GT 340" },
886{ 0x10DE0CA5,"GeForce GT 220" },
887{ 0x10DE0CA7,"GeForce GT 330" },
888{ 0x10DE0CA8,"GeForce GTS 260M" },
889{ 0x10DE0CA9,"GeForce GTS 250M" },
890{ 0x10DE0CAC,"GeForce GT 220" },
891{ 0x10DE0CAD,"N10E-ES" }, // SUBIDS
892{ 0x10DE0CAE,"GT215-INT" },
893{ 0x10DE0CAF,"GeForce GT 335M" },
894// 0CB0 - 0CBF
895{ 0x10DE0CB0,"GeForce GTS 350M" },
896{ 0x10DE0CB1,"GeForce GTS 360M" },
897{ 0x10DE0CBC,"Quadro FX 1800M" },
898// 0CC0 - 0CCF
899// 0CD0 - 0CDF
900// 0CE0 - 0CEF
901// 0CF0 - 0CFF
902// 0D00 - 0D0F
903// 0D10 - 0D1F
904// 0D20 - 0D2F
905// 0D30 - 0D3F
906// 0D40 - 0D4F
907// 0D50 - 0D5F
908// 0D60 - 0D6F
909// 0D70 - 0D7F
910// 0D80 - 0D8F
911// 0D90 - 0D9F
912// 0DA0 - 0DAF
913// 0DB0 - 0DBF
914// 0DC0 - 0DCF
915{ 0x10DE0DC0,"GeForce GT 440" },
916// { 0x10DE0DC1,"D12-P1-35" },
917// { 0x10DE0DC2,"D12-P1-35" },
918{ 0x10DE0DC4,"GeForce GTS 450" },
919{ 0x10DE0DC5,"GeForce GTS 450" },
920{ 0x10DE0DC6,"GeForce GTS 450" },
921// { 0x10DE0DCA,"GF10x" },
922// { 0x10DE0DCC,"N12E-GS" },
923{ 0x10DE0DCD,"GeForce GT 555M" },
924{ 0x10DE0DCE,"GeForce GT 555M" },
925// { 0x10DE0DCF,"N12P-GT-B" },
926// 0DD0 - 0DDF
927// { 0x10DE0DD0,"N11E-GT" },
928{ 0x10DE0DD1,"GeForce GTX 460M" },
929{ 0x10DE0DD2,"GeForce GT 445M" },
930{ 0x10DE0DD3,"GeForce GT 435M" },
931{ 0x10DE0DD6,"GeForce GT 550M" },
932{ 0x10DE0DD8,"Quadro 2000" },
933{ 0x10DE0DDA,"Quadro 2000M" },
934{ 0x10DE0DDE,"GF106-ES" },
935// { 0x10DE0DDF,"GF106-INT" },
936// 0DE0 - 0DEF
937{ 0x10DE0DE0,"GeForce GT 440" },
938{ 0x10DE0DE1,"GeForce GT 430" },
939{ 0x10DE0DE2,"GeForce GT 420" },
940{ 0x10DE0DE3,"GeForce GT 635M" },
941{ 0x10DE0DE4,"GeForce GT 520" },
942{ 0x10DE0DE5,"GeForce GT 530" },
943{ 0x10DE0DE8,"GeForce GT 620M" },
944{ 0x10DE0DE9,"GeForce GT 630M" },
945{ 0x10DE0DEA,"GeForce GT 610M" },
946{ 0x10DE0DEB,"GeForce GT 555M" },
947{ 0x10DE0DEC,"GeForce GT 525M" },
948{ 0x10DE0DED,"GeForce GT 520M" },
949{ 0x10DE0DEE,"GeForce GT 415M" },
950{ 0x10DE0DEF,"N13P-NS1-A1" },
951// 0DF0 - 0DFF
952{ 0x10DE0DF0,"GeForce GT 425M" },
953{ 0x10DE0DF1,"GeForce GT 420M" },
954{ 0x10DE0DF2,"GeForce GT 435M" },
955{ 0x10DE0DF3,"GeForce GT 420M" },
956{ 0x10DE0DF4,"GeForce GT 540M" },
957{ 0x10DE0DF5,"GeForce GT 525M" },
958{ 0x10DE0DF6,"GeForce GT 550M" },
959{ 0x10DE0DF7,"GeForce GT 520M" },
960{ 0x10DE0DF8,"Quadro 600" },
961{ 0x10DE0DF9,"Quadro 500M" },
962{ 0x10DE0DFA,"Quadro 1000M" },
963{ 0x10DE0DFC,"NVS 5200M" },
964{ 0x10DE0DFE,"GF108 ES" },
965// { 0x10DE0DFF,"GF108 INT" },
966// 0E00 - 0E0F
967// 0E10 - 0E1F
968// 0E20 - 0E2F
969{ 0x10DE0E21,"D12U-25" },
970{ 0x10DE0E22,"GeForce GTX 460" },
971{ 0x10DE0E23,"GeForce GTX 460 SE" },
972{ 0x10DE0E24,"GeForce GTX 460" },
973// { 0x10DE0E25,"D12U-50" },
974{ 0x10DE0E28,"GeForce GTX 460" },
975// 0E30 - 0E3F
976{ 0x10DE0E30,"GeForce GTX 470M" },
977{ 0x10DE0E31,"GeForce GTX 485M" },
978// { 0x10DE0E32,"N12E-GT" },
979{ 0x10DE0E38,"GF104GL" },
980{ 0x10DE0E3A,"Quadro 3000M" },
981{ 0x10DE0E3B,"Quadro 4000M" },
982// { 0x10DE0E3E,"GF104-ES" },
983// { 0x10DE0E3F,"GF104-INT" },
984// 0E40 - 0E4F
985// 0E50 - 0E5F
986// 0E60 - 0E6F
987// 0E70 - 0E7F
988// 0E80 - 0E8F
989// 0E90 - 0E9F
990// 0EA0 - 0EAF
991// 0EB0 - 0EBF
992// 0EC0 - 0ECF
993// 0ED0 - 0EDF
994// 0EE0 - 0EEF
995// 0EF0 - 0EFF
996// 0F00 - 0F0F
997{ 0x10DE0F00,"GeForce GT 630" },
998{ 0x10DE0F01,"GeForce GT 620" },
999// 0F10 - 0F1F
1000// 0F20 - 0F2F
1001// 0F30 - 0F3F
1002// 0F40 - 0F4F
1003// 0F50 - 0F5F
1004// 0F60 - 0F6F
1005// 0F70 - 0F7F
1006// 0F80 - 0F8F
1007// 0F90 - 0F9F
1008// 0FA0 - 0FAF
1009// 0FB0 - 0FBF
1010// 0FC0 - 0FCF
1011{ 0x10DE0FC0,"GeForce GT 640" },
1012{ 0x10DE0FC1,"GeForce GT 640" },
1013{ 0x10DE0FC2,"GeForce GT 630" },
1014{ 0x10DE0FC6,"GeForce GTX 650" },
1015{ 0x10DE0FCD,"GeForce GT 755M" },
1016// 0FD0 - 0FDF
1017{ 0x10DE0FD1,"GeForce GT 650M" },
1018{ 0x10DE0FD2,"GeForce GT 640M" },
1019{ 0x10DE0FD3,"GeForce GT 640M LE" },
1020{ 0x10DE0FD4,"GeForce GTX 660M" },
1021{ 0x10DE0FD5,"GeForce GT 650M" },
1022{ 0x10DE0FD8,"GeForce GT 640M" },
1023{ 0x10DE0FD9,"GeForce GT 645M" },
1024{ 0x10DE0FDB,"GK107-ESP-A1" },
1025{ 0x10DE0FDF,"GeForce GT 740M" },
1026// 0FE0 - 0FEF
1027{ 0x10DE0FE0,"GeForce GTX 660M" },
1028{ 0x10DE0FE1,"GeForce GT 730M" },
1029{ 0x10DE0FE3,"GeForce GT 745M" },
1030{ 0x10DE0FE4,"GeForce GT 750M" },
1031// 0FF0 - 0FFF
1032{ 0x10DE0FF2,"VGX K1" },
1033{ 0x10DE0FF8,"Quadro K500M" },
1034{ 0x10DE0FF9,"Quadro K2000D" },
1035{ 0x10DE0FFA,"Quadro K600" },
1036{ 0x10DE0FFB,"Quadro K2000M" },
1037{ 0x10DE0FFC,"Quadro K1000M" },
1038{ 0x10DE0FFD,"NVS 510" },
1039{ 0x10DE0FFE,"Quadro K2000" },
1040{ 0x10DE0FFF,"Quadro 410" },
1041// 1000 - 100F
1042{ 0x10DE1003,"GeForce GTX Titan LE" },
1043{ 0x10DE1004,"GeForce GTX 780" },
1044{ 0x10DE1005,"GeForce GTX Titan" },
1045{ 0x10DE100A,"GeForce GTX 780 Ti" },
1046{ 0x10DE100C,"GeForce GTX Titan Black" },
1047// 1010 - 101F
1048{ 0x10DE101F,"Tesla K20" },
1049// 1020 - 102F
1050{ 0x10DE1020,"Tesla K20X" },
1051{ 0x10DE1021,"Tesla K20Xm" },
1052{ 0x10DE1022,"Tesla K20c" },
1053{ 0x10DE1026,"Tesla K20s" },
1054{ 0x10DE1028,"Tesla K20m" },
1055// 1030 - 103F
1056// 1040 - 104F
1057{ 0x10DE1040,"GeForce GT 520" },
1058// { 0x10DE1041,"D13M1-45" },
1059{ 0x10DE1042,"GeForce 510" },
1060{ 0x10DE1048,"GeForce 605" },
1061{ 0x10DE1049,"GeForce GT 620" },
1062{ 0x10DE104A,"GeForce GT 610" },
1063{ 0x10DE104B,"GeForce GT 625 (OEM)" },
1064// 1050 - 105F
1065{ 0x10DE1050,"GeForce GT 520M" },
1066{ 0x10DE1051,"GeForce GT 520MX" },
1067{ 0x10DE1052,"GeForce GT 520M" },
1068{ 0x10DE1054,"GeForce GT 410M" },
1069{ 0x10DE1055,"GeForce 410M" },
1070{ 0x10DE1056,"Quadro NVS 4200M" },
1071{ 0x10DE1057,"Quadro NVS 4200M" },
1072{ 0x10DE1058,"GeForce GT 610M" },
1073{ 0x10DE1059,"GeForce 610M" },
1074{ 0x10DE105A,"GeForce 610M" },
1075{ 0x10DE105B,"GeForce 705A" },
1076// 1060 - 106F
1077// 1070 - 107F
1078{ 0x10DE107C,"Quadro NVS 315" },
1079{ 0x10DE107D,"Quadro NVS 310" },
1080// { 0x10DE107E,"GF119-INT" },
1081{ 0x10DE107F,"GF119-ES" },
1082// 1080 - 108F
1083{ 0x10DE1080,"GeForce GTX 580" },
1084{ 0x10DE1081,"GeForce GTX 570" },
1085{ 0x10DE1082,"GeForce GTX 560 Ti" },
1086{ 0x10DE1083,"D13U" },
1087{ 0x10DE1084,"GeForce GTX 560" },
1088{ 0x10DE1086,"GeForce GTX 570 HD" },
1089{ 0x10DE1087,"GeForce GTX 560 Ti-448" },
1090{ 0x10DE1088,"GeForce GTX 590" },
1091{ 0x10DE1089,"GeForce GTX 580" },
1092{ 0x10DE108B,"GeForce GTX 590" },
1093// { 0x10DE108C,"D13U" },
1094{ 0x10DE108E,"Tesla C2090" },
1095// 1090 - 109F
1096{ 0x10DE1091,"Tesla M2090" }, // X2090
1097{ 0x10DE1094,"Tesla M2075" },
1098{ 0x10DE1096,"Tesla C2075" },
1099{ 0x10DE1098,"D13U" },
1100{ 0x10DE109A,"Quadro 5010M" },
1101{ 0x10DE109B,"Quadro 7000" },
1102// 10A0 - 10AF
1103// 10B0 - 10BF
1104// 10C0 - 10CF
1105{ 0x10DE10C0,"GeForce 9300 GS" },
1106{ 0x10DE10C3,"GeForce 8400 GS" },
1107{ 0x10DE10C4,"ION" },
1108{ 0x10DE10C5,"GeForce 405" },
1109// 10D0 - 10DF
1110{ 0x10DE10D8,"Quadro NVS 300" },
1111// 10E0 - 10EF
1112// 10F0 - 10FF
1113// 1100 - 110F
1114// 1110 - 111F
1115// 1120 - 112F
1116// 1130 - 113F
1117// 1140 - 114F
1118{ 0x10DE1140,"GeForce GT 610M" },
1119{ 0x10DE1141,"GeForce 610M" },
1120{ 0x10DE1142,"GeForce 620M" },
1121// { 0x10DE1143,"N13P-GV" },
1122// { 0x10DE1144,"GF117" },
1123// { 0x10DE1145,"GF117" },
1124// { 0x10DE1146,"GF117" },
1125// { 0x10DE1147,"GF117" },
1126{ 0x10DE1149,"GF117-ES" },
1127// { 0x10DE114A,"GF117-INT" },
1128// { 0x10DE114B,"PCI-GEN3-B" },
1129// 1150 - 115F
1130// 1160 - 116F
1131// 1170 - 117F
1132// 1180 - 118F
1133{ 0x10DE1180,"GeForce GTX 680" },
1134{ 0x10DE1182,"GeForce GTX 760 Ti" },
1135{ 0x10DE1183,"GeForce GTX 660 Ti" },
1136{ 0x10DE1184,"GeForce GTX 770" },
1137{ 0x10DE1185,"GeForce GTX 660" },
1138{ 0x10DE1187,"GeForce GTX 760" },
1139{ 0x10DE1188,"GeForce GTX 690" },
1140{ 0x10DE1189,"GeForce GTX 670" },
1141{ 0x10DE118A,"GRID K520" },
1142{ 0x10DE118B,"GRID K200" }, // GRID K2 GeForce USM
1143{ 0x10DE118E,"GeForce GTX 760 (192-bit)" },
1144{ 0x10DE118F,"Tesla K10" },
1145// 1190 - 119F
1146{ 0x10DE1192,"GeForce GK104" },
1147{ 0x10DE1193,"GeForce GTX 760 Ti" },
1148{ 0x10DE1198,"GeForce GTX 880M" },
1149{ 0x10DE1199,"GeForce GTX 870M" },
1150{ 0x10DE119a,"GeForce GTX 860M" },
1151{ 0x10DE119d,"GeForce GTX 775M" }, // Mac Edition
1152{ 0x10DE119e,"GeForce GTX 780M" }, // Mac Edition
1153{ 0x10DE119F,"GeForce GTX 780M" },
1154// 11A0 - 11AF
1155{ 0x10DE11A0,"GeForce GTX 680M" },
1156{ 0x10DE11A1,"GeForce GTX 670MX" },
1157{ 0x10DE11A2,"GeForce GTX 675MX" }, // Mac Edition
1158{ 0x10DE11A3,"GeForce GTX 680MX" },
1159{ 0x10DE11A7,"GeForce GTX 675MX" },
1160// 11B0 - 11BF
1161{ 0x10DE11B0,"GRID K240Q" }, // K260Q vGPU
1162{ 0x10DE11B1,"GRID K2 Tesla USM" },
1163{ 0x10DE11B6,"Quadro K3100M" },
1164{ 0x10DE11B7,"Quadro K4100M" },
1165{ 0x10DE11B8,"Quadro K5100M" },
1166{ 0x10DE11BA,"Quadro K5000" },
1167{ 0x10DE11BB,"Quadro 4100" },
1168{ 0x10DE11BC,"Quadro K5000M" },
1169{ 0x10DE11BD,"Quadro K4000M" },
1170{ 0x10DE11BE,"Quadro K3000M" },
1171{ 0x10DE11BF,"VGX K2" },
1172// 11C0 - 11CF
1173{ 0x10DE11C0,"GeForce GTX 660" },
1174{ 0x10DE11C2,"GeForce GTX 650 Ti BOOST" },
1175{ 0x10DE11C3,"GeForce GTX 650 Ti" },
1176{ 0x10DE11C4,"GeForce GTX 645" },
1177{ 0x10DE11C6,"GeForce GTX 650 Ti" },
1178{ 0x10DE11C7,"GeForce GTX 750 Ti" },
1179{ 0x10DE11C8,"GeForce GTX 650 OEM" },
1180// 11D0 - 11DF
1181{ 0x10DE11D0,"GK106-INT353" },
1182// 11E0 - 11EF
1183{ 0x10DE11E0,"GeForce GTX 770M" },
1184{ 0x10DE11E1,"N14E-GE-B-A1" },
1185{ 0x10DE11E2,"GeForce GTX 765M" },
1186{ 0x10DE11E3,"GeForce GTX 760M" },
1187// 11F0 - 11FF
1188{ 0x10DE11FA,"Quadro K4000" },
1189{ 0x10DE11FC,"Quadro 2100M" },
1190// 1200 - 120F
1191{ 0x10DE1200,"GeForce GTX 560 Ti" },
1192{ 0x10DE1201,"GeForce GTX 560" },
1193{ 0x10DE1202,"GeForce GTX 560 Ti" },
1194{ 0x10DE1203,"GeForce GTX 460 SE v2" },
1195{ 0x10DE1205,"GeForce GTX 460 v2" },
1196{ 0x10DE1206,"GeForce GTX 555" },
1197{ 0x10DE1207,"GeForce GT 645" },
1198{ 0x10DE1208,"GeForce GTX 560 SE" },
1199{ 0x10DE1210,"GeForce GTX 570M" },
1200{ 0x10DE1211,"GeForce GTX 580M" },
1201{ 0x10DE1212,"GeForce GTX 675M" },
1202{ 0x10DE1213,"GeForce GTX 670M" },
1203//{ 0x10DE121F,"GF114-INT" },
1204{ 0x10DE1240,"GeForce GT 620M" },
1205{ 0x10DE1241,"GeForce GT 545" },
1206{ 0x10DE1243,"GeForce GT 545" },
1207{ 0x10DE1244,"GeForce GTX 550 Ti" },
1208{ 0x10DE1245,"GeForce GTS 450" },
1209{ 0x10DE1246,"GeForce GT 550M" },
1210{ 0x10DE1247,"GeForce GT 555M" },
1211{ 0x10DE1248,"GeForce GT 555M" },
1212{ 0x10DE1249,"GeForce GTS 450" },
1213{ 0x10DE124B,"GeForce GT 640" },
1214{ 0x10DE124D,"GeForce GT 555M" },
1215{ 0x10DE1250,"GF116-INT" },
1216{ 0x10DE1251,"GeForce GTX 560M" },
1217// 1260 - 126F
1218// 1270 - 127F
1219// 1280 - 128F
1220{ 0x10DE1280,"GeForce GT 635" },
1221{ 0x10DE1281,"GeForce GT 710" },
1222{ 0x10DE1282,"GeForce GT 640" },
1223{ 0x10DE1284,"GeForce GT 630" },
1224{ 0x10DE1286,"GeForce GT 720" },
1225{ 0x10DE1287,"GeForce GT 730" }, // GK208
1226// 1290 - 129F
1227{ 0x10DE1290,"GeForce GT 730M" },
1228{ 0x10DE1291,"GeForce GT 735M" },
1229{ 0x10DE1292,"GeForce GT 740M" },
1230{ 0x10DE1293,"GeForce GT 730M" },
1231{ 0x10DE1294,"GeForce GT 740M" },
1232{ 0x10DE1295,"GeForce GT 710M" },
1233{ 0x10DE1296,"GeForce 825M" }, // GK208M
1234{ 0x10DE1298,"GeForce GT 720M" },
1235// 12A0 - 12AF
1236//{ 0x10DE12A0,"GeForce GT ???" },
1237{ 0x10DE12AF,"GK208-INT" },
1238{ 0x10DE12B0,"GK208-CS-Q" },
1239{ 0x10DE12B9,"Quadro K610M" },
1240{ 0x10DE12BA,"Quadro K510M" },
1241// 12B0 - 12BF
1242// 12C0 - 12CF
1243// 12D0 - 12DF
1244// 12E0 - 12EF
1245// 12F0 - 12FF
1246{ 0x10DE1340,"GeForce 830M" },
1247{ 0x10DE1341,"GeForce 840M" },
1248{ 0x10DE1380,"GeForce GTX 750 Ti" },
1249{ 0x10DE1381,"GeForce GTX 750" },
1250{ 0x10DE1382,"GeForce GTX 745" },
1251{ 0x10DE1390,"GeForce 845M" },
1252{ 0x10DE1391,"GeForce GTX 850M" },
1253{ 0x10DE1392,"GeForce GTX 860M" },
1254{ 0x10DE1393,"GeForce 840M" },
1255{ 0x10DE13BA,"Quadro K2200" },
1256{ 0x10DE13BB,"Quadro K620" },
1257{ 0x10DE13BD,"Tesla M40" },
1258// 12B0 - 12BF
1259{ 0x10DE13C0,"GeForce GTX 980" }, // GM204
1260//{ 0x10DE13C1,"GeForce GTX 9xx" }, // GM204
1261{ 0x10DE13C2,"GeForce GTX 970" } // GM204
1262//{ 0x10DE13C3,"GeForce GTX 9xx" }, // GM204
1263};
1264
1265static nvidia_card_info_t nvidia_card_exceptions[] = {
1266 /* ========================================================================================
1267 * Layout is device(VendorId + DeviceId), subdev (SubvendorId + SubdeviceId), display name.
1268 * ========================================================================================
1269 */
1270 /* ------ Specific DeviceID and SubDevID. ------ */
1271// 0000 - 00FF
1272{ 0x10DE0040,0x10438178,"Asus V9999 Ultra V62.11" },
1273{ 0x10DE0040,0x1043817D,"Asus V9999GT V61.21" },
1274{ 0x10DE0040,0x7FFFFFFF,"GeForce 6800 Ultra [NV40.0]" },
1275// 0100 - 01FF
1276{ 0x10DE01D7,0x102801C2,"Dell Quadro NVS 110M" },
1277{ 0x10DE01D7,0x102801CC,"Dell Quadro NVS 110M" },
1278{ 0x10DE01D7,0x10DE014B,"nVidia Quadro NVS 110M" },
1279
1280{ 0x10DE01D8,0x102801CC,"Dell Quadro NVS 120M" },
1281{ 0x10DE01D8,0x10282003,"Dell Quadro NVS 120M" },
1282
1283{ 0x10DE01DA,0x10280407,"Dell GeForce 7300 LE" },
1284// 0200 - 02FF
1285{ 0x10DE025B,0x10480D23,"ELSA Gloria4 700XGL" },
1286// 0300 - 03FF
1287{ 0x10DE0391,0x10DE047A,"Galaxy GeForce 7600 GT" },
1288{ 0x10DE0391,0x19F120DE,"Galaxy GeForce 7600 GT" },
1289
1290{ 0x10DE0393,0x00000400,"Apple GeForce 7300GT" },
1291// 0400 - 04FF
1292{ 0x10DE0402,0x10DE0439,"Galaxy 8600GT" },
1293{ 0x10DE0402,0x10DE0505,"Galaxy 8600GT" },
1294// 0500 - 05FF
1295{ 0x10DE05E2,0x104382EB,"ASUS ENGTX260" },
1296{ 0x10DE05E2,0x16822390,"HFX GeForce GTX 260" },
1297{ 0x10DE05E2,0x17870000,"HIS GeForce GTX 260" },
1298
1299{ 0x10DE05E6,0x10B00401,"Gainward GeForce GTX 285" },
1300
1301{ 0x10DE05E7,0x10DE0595,"nVidia Tesla T10 Processor" },
1302{ 0x10DE05E7,0x10DE066A,"nVidia Tesla C1060" },
1303{ 0x10DE05E7,0x10DE068F,"nVidia Tesla T10 Processor" },
1304{ 0x10DE05E7,0x10DE0697,"nVidia Tesla M1060" },
1305{ 0x10DE05E7,0x10DE0714,"nVidia Tesla M1060" },
1306{ 0x10DE05E7,0x10DE0743,"nVidia Tesla M1060" },
1307// 0600 - 06FF
1308{ 0x10DE0600,0x10DE0000,"Abit GeForce 8800 GTS" },
1309
1310{ 0x10DE0605,0x145834A2,"Gigabyte GV-N98TOC-512H" },
1311
1312{ 0x10DE0608,0x15880577,"Solidum GeForce 9800M GTX" },
1313
1314{ 0x10DE0609,0x11700121,"Inventec GeForce 8800M GTS" },
1315
1316{ 0x10DE0612,0x104382A6,"Asus GeForce 9800 GTX+" },
1317{ 0x10DE0612,0x10DE0571,"nVidia GeForce 9800 GTX+" },
1318{ 0x10DE0612,0x10DE0592,"nVidia GeForce 9800 GTX+" },
1319{ 0x10DE0612,0x3842C842,"EVGA GeForce 9800 GTX+" },
1320{ 0x10DE0612,0x3842C875,"EVGA GeForce 9800 GTX+" },
1321
1322{ 0x10DE0615,0x10480F67,"ELSA GeForce GTS 250" },
1323{ 0x10DE0615,0x10DE0592,"Palit GeForce GTS 250" },
1324{ 0x10DE0615,0x10DE0593,"Palit GeForce GTS 250" },
1325{ 0x10DE0615,0x10DE0652,"Palit GeForce GTS 250" },
1326{ 0x10DE0615,0x10DE0719,"Palit GeForce GTS 250" },
1327{ 0x10DE0615,0x10DE079E,"Palit GeForce GTS 250" },
1328{ 0x10DE0615,0x11503842,"TMC GeForce GTS 250" }, // Thinking Machines Corporation
1329{ 0x10DE0615,0x11513842,"JAE GeForce GTS 250" },
1330{ 0x10DE0615,0x11553842,"Pine GeForce GTS 250" },
1331{ 0x10DE0615,0x11563842,"Periscope GeForce GTS 250" },
1332
1333{ 0x10DE0618,0x10432028,"Asus GeForce GTX 170M" },
1334{ 0x10DE0618,0x1043202B,"Asus GeForce GTX 680" },
1335
1336{ 0x10DE0622,0x104382AC,"Asus EN9600GT Magic" },
1337
1338{ 0x10DE0640,0x10DE077F,"Inno3D GeForce 9500GT HDMI" },
1339
1340{ 0x10DE0649,0x1043202D,"Asus GeForce GT 220M" },
1341
1342{ 0x10DE06CD,0x10DE079F,"Point of View GeForce GTX 470" },
1343{ 0x10DE06CD,0x14622220,"MSi GeForce GTX 470 Twin Frozr II" },
1344
1345{ 0x10DE06D1,0x10DE0771,"nVidia Tesla C2050" },
1346{ 0x10DE06D1,0x10DE0772,"nVidia Tesla C2070" },
1347
1348{ 0x10DE06D2,0x10DE0774,"nVidia Tesla M2070" },
1349{ 0x10DE06D2,0x10DE0830,"nVidia Tesla M2070" },
1350{ 0x10DE06D2,0x10DE0842,"nVidia Tesla M2070" },
1351{ 0x10DE06D2,0x10DE088F,"nVidia Tesla X2070" },
1352{ 0x10DE06D2,0x10DE0908,"nVidia Tesla M2070" },
1353
1354{ 0x10DE06DE,0x10DE0773,"nVidia Tesla S2050" },
1355{ 0x10DE06DE,0x10DE0830,"nVidia Tesla M2070" },
1356{ 0x10DE06DE,0x10DE0831,"nVidia Tesla M2070" },
1357{ 0x10DE06DE,0x10DE0832,"nVidia Tesla M2070" },
1358{ 0x10DE06DE,0x10DE0840,"nVidia Tesla X2070" },
1359
1360{ 0x10DE06E4,0x10438322,"Asus EN8400GS" },
1361{ 0x10DE06E4,0x14583475,"GV-NX84S256HE [GeForce 8400 GS]" },
1362
1363{ 0x10DE06E8,0x10280262,"Dell GeForce 9200M GS" },
1364{ 0x10DE06E8,0x10280271,"Dell GeForce 9200M GS" },
1365{ 0x10DE06E8,0x10280272,"Dell GeForce 9200M GS" },
1366{ 0x10DE06E8,0x103C30F4,"HP GeForce 9200M GS" },
1367{ 0x10DE06E8,0x103C30F7,"HP GeForce 9200M GS" },
1368{ 0x10DE06E8,0x103C3603,"HP GeForce 9200M GS" },
1369// 0700 - 07FF
1370// 0800 - 08FF
1371{ 0x10DE0873,0x104319B4,"Asus GeForce G102M" },
1372// 0900 - 09FF
1373// 0A00 - 0AFF
1374{ 0x10DE0A6F,0x12974003,"Shuttle XS 3510MA" },
1375
1376{ 0x10DE0A70,0x17AA3605,"Lenovo ION" },
1377
1378{ 0x10DE0A73,0x17AA3607,"Lenovo ION" },
1379{ 0x10DE0A73,0x17AA3610,"Lenovo ION" },
1380
1381{ 0x10DE0A75,0x17AA3605,"Lenovo ION" },
1382// 0B00 - 0BFF
1383// 0C00 - 0CFF
1384{ 0x10DE0CA3,0x14628041,"MSi VN240GT-MD1G" },
1385{ 0x10DE0CA3,0x16423926,"Bitland GeForce GT 230" },
1386// 0D00 - 0DFF
1387{ 0x10DE0DD8,0x10DE0914,"nVidia Quadro 2000D" },
1388
1389{ 0x10DE0DEF,0x17AA21F3,"Lenovo NVS 5400M" },
1390{ 0x10DE0DEF,0x17AA21F4,"Lenovo NVS 5400M" },
1391{ 0x10DE0DEF,0x17AA21F5,"Lenovo NVS 5400M" },
1392{ 0x10DE0DEF,0x17AA21F6,"Lenovo NVS 5400M" },
1393{ 0x10DE0DEF,0x17AA5005,"Lenovo NVS 5400M" },
1394
1395// 0E00 - 0EFF
1396{ 0x10DE0E22,0x1043835D,"Asus ENGTX460" },
1397
1398{ 0x10DE0E23,0x10B00401,"Gainward GeForce GTX 460" },
1399// 0F00 - 0FFF
1400{ 0x10DE0FD2,0x10280595,"Dell GeForce GT 640M LE" },
1401{ 0x10DE0FD2,0x102805B2,"Dell GeForce GT 640M LE" },
1402// 1000 - 10FF
1403{ 0x10DE1080,0x14622561,"MSI N580GTX Lightning" },
1404{ 0x10DE1080,0x14622563,"MSI N580GTX Lightning" },
1405
1406{ 0x10DE1086,0x10DE0871,"Inno3D GeForce GTX 570" },
1407
1408{ 0x10DE1087,0x104383D6,"Asus ENGTX560Ti448 DCII" },
1409
1410{ 0x10DE1091,0x10DE088E,"nVidia Tesla X2090" },
1411{ 0x10DE1091,0x10DE0891,"nVidia Tesla X2090" },
1412
1413{ 0x10DE1094,0x10DE0888,"nVidia Tesla M2075" },
1414
1415{ 0x10DE1096,0x10DE0910,"nVidia Tesla C2075" },
1416{ 0x10DE1096,0x10DE0911,"nVidia Tesla C2050" },
1417
1418// 1100 - 11FF
1419{ 0x10DE1140,0x1025064A,"Acer GeForce GT 620M" },
1420{ 0x10DE1140,0x1025064C,"Acer GeForce GT 620M" },
1421{ 0x10DE1140,0x10250680,"Acer GeForce GT 620M" },
1422{ 0x10DE1140,0x10250692,"Acer GeForce GT 620M" },
1423{ 0x10DE1140,0x10250694,"Acer GeForce GT 620M" },
1424{ 0x10DE1140,0x10250702,"Acer GeForce GT 620M" },
1425{ 0x10DE1140,0x10250719,"Acer GeForce GT 620M" },
1426{ 0x10DE1140,0x10250725,"Acer GeForce GT 620M" },
1427{ 0x10DE1140,0x10250728,"Acer GeForce GT 620M" },
1428{ 0x10DE1140,0x1025072B,"Acer GeForce GT 620M" },
1429{ 0x10DE1140,0x1025072E,"Acer GeForce GT 620M" },
1430{ 0x10DE1140,0x10250732,"Acer GeForce GT 620M" },
1431{ 0x10DE1140,0x10280565,"Dell GeForce GT 630M" },
1432{ 0x10DE1140,0x10280568,"Dell GeForce GT 630M" },
1433{ 0x10DE1140,0x144DC0D5,"Samsung GeForce GT 630M" },
1434{ 0x10DE1140,0x17AA500D,"Lenovo GeForce GT 620M" },
1435{ 0x10DE1140,0x1B0A20DD,"Pegatron GeForce GT 620M" },
1436{ 0x10DE1140,0x1B0A20FD,"Pegatron GeForce GT 620M" },
1437
1438{ 0x10DE1180,0x00001255,"Afox GTX 680" },
1439{ 0x10DE1180,0x104383F0,"Asus GTX680-2GD5" },
1440{ 0x10DE1180,0x104383F6,"Asus GTX 680 Direct CU II" },
1441{ 0x10DE1180,0x104383F7,"Asus GTX 680 Direct CU II" },
1442{ 0x10DE1180,0x1458353C,"GV-N680OC-2GD WindForce GTX 680 OC" },
1443{ 0x10DE1180,0x14622820,"MSi N680GTX TwinFrozer" },
1444{ 0x10DE1180,0x14622830,"MSi GTX 680 Lightning" },
1445{ 0x10DE1180,0x14622831,"MSi GTX 680 Lightning LN2" },
1446{ 0x10DE1180,0x15691180,"Palit GTX 680 JetStream" },
1447{ 0x10DE1180,0x15691181,"Palit GTX 680 JetStream" },
1448{ 0x10DE1180,0x15691189,"Palit GTX 680 JetStream" },
1449{ 0x10DE1180,0x38422682,"EVGA GTX 680 SC" },
1450{ 0x10DE1180,0x38422683,"EVGA GTX 680 SC" },
1451
1452{ 0x10DE1187,0x14583614,"GV-N760OC-4GD" },
1453
1454{ 0x10DE1189,0x10438405,"Asus GTX 670 Direct CU II TOP" },
1455{ 0x10DE1189,0x15691189,"Palit GTX 670 JetStream" },
1456{ 0x10DE1189,0x19DA1255,"Zotac GTX 670 AMP! Edition" },
1457
1458{ 0x10DE11A1,0x15587102,"Clevo N13E-GR" },
1459
1460{ 0x10DE11C0,0x10DE0995,"Inno3D GeForce GTX660" },
1461{ 0x10DE11C0,0x1458354E,"GV-N660OC-2GD" },
1462
1463{ 0x10DE11C6,0x1043842A,"GTX650TI-1GD5" },
1464// 1200 - 12FF
1465{ 0x10DE1247,0x10432119,"Asus GeForce GT 670M" },
1466{ 0x10DE1247,0x10432120,"Asus GeForce GT 670M" },
1467{ 0x10DE1247,0x1043212A,"Asus GeForce GT 635M" },
1468{ 0x10DE1247,0x1043212B,"Asus GeForce GT 635M" },
1469{ 0x10DE1247,0x1043212C,"Asus GeForce GT 635M" },
1470{ 0x10DE1247,0x152D0930,"Quanta GeForce GT 635M" },
1471
1472{ 0x10DE1248,0x152D0930,"Quanta GeForce GT 635M" },
1473
1474{ 0x10DE124D,0x146210CC,"MSi GeForce GT 635M" },
1475};
1476
1477static int patch_nvidia_rom(uint8_t *rom)
1478{
1479if (!rom || (rom[0] != 0x55 && rom[1] != 0xaa)) {
1480printf("False ROM signature: 0x%02x%02x\n", rom[0], rom[1]);
1481return PATCH_ROM_FAILED;
1482}
1483
1484uint16_t dcbptr = READ_LE_SHORT(rom, 0x36);
1485
1486if (!dcbptr) {
1487printf("no dcb table found\n");
1488return PATCH_ROM_FAILED;
1489}
1490//else
1491//printf("dcb table at offset 0x%04x\n", dcbptr);
1492
1493uint8_t *dcbtable = &rom[dcbptr];
1494uint8_t dcbtable_version = dcbtable[0];
1495uint8_t headerlength = 0;
1496uint8_t numentries = 0;
1497uint8_t recordlength = 0;
1498
1499if (dcbtable_version >= 0x20) {
1500uint32_t sig;
1501
1502if (dcbtable_version >= 0x30) {
1503headerlength = dcbtable[1];
1504numentries = dcbtable[2];
1505recordlength = dcbtable[3];
1506
1507sig = READ_LE_INT(dcbtable, 6);
1508} else {
1509sig = READ_LE_INT(dcbtable, 4);
1510headerlength = 8;
1511}
1512
1513if (sig != 0x4edcbdcb) {
1514printf("Bad display config block signature (0x%8x)\n", sig); //Azi: issue #48
1515return PATCH_ROM_FAILED;
1516}
1517} else if (dcbtable_version >= 0x14) { /* some NV15/16, and NV11+ */
1518char sig[8] = { 0 };
1519
1520strncpy(sig, (char *)&dcbtable[-7], 7);
1521recordlength = 10;
1522
1523if (strcmp(sig, "DEV_REC")) {
1524printf("Bad Display Configuration Block signature (%s)\n", sig);
1525return PATCH_ROM_FAILED;
1526}
1527} else {
1528printf("ERROR: dcbtable_version is 0x%X\n", dcbtable_version);
1529return PATCH_ROM_FAILED;
1530}
1531
1532if (numentries >= MAX_NUM_DCB_ENTRIES) {
1533numentries = MAX_NUM_DCB_ENTRIES;
1534}
1535
1536uint8_t num_outputs = 0, i = 0;
1537
1538struct dcbentry {
1539uint8_t type;
1540uint8_t index;
1541uint8_t *heads;
1542} entries[numentries];
1543
1544for (i = 0; i < numentries; i++) {
1545uint32_t connection;
1546connection = READ_LE_INT(dcbtable,headerlength + recordlength * i);
1547
1548/* Should we allow discontinuous DCBs? Certainly DCB I2C tables can be discontinuous */
1549if ((connection & 0x0000000f) == 0x0000000f) { /* end of records */
1550continue;
1551}
1552if (connection == 0x00000000) { /* seen on an NV11 with DCB v1.5 */
1553continue;
1554}
1555if ((connection & 0xf) == 0x6) { /* we skip type 6 as it doesnt appear on macbook nvcaps */
1556continue;
1557}
1558
1559entries[num_outputs].type = connection & 0xf;
1560entries[num_outputs].index = num_outputs;
1561entries[num_outputs++].heads = (uint8_t*)&(dcbtable[(headerlength + recordlength * i) + 1]);
1562
1563}
1564
1565int has_lvds = false;
1566uint8_t channel1 = 0, channel2 = 0;
1567
1568for (i = 0; i < num_outputs; i++) {
1569if (entries[i].type == 3) {
1570has_lvds = true;
1571//printf("found LVDS\n");
1572channel1 |= ( 0x1 << entries[i].index);
1573entries[i].type = TYPE_GROUPED;
1574}
1575}
1576
1577// if we have a LVDS output, we group the rest to the second channel
1578if (has_lvds) {
1579for (i = 0; i < num_outputs; i++) {
1580if (entries[i].type == TYPE_GROUPED) {
1581continue;
1582}
1583
1584channel2 |= ( 0x1 << entries[i].index);
1585entries[i].type = TYPE_GROUPED;
1586}
1587} else {
1588int x;
1589// we loop twice as we need to generate two channels
1590for (x = 0; x <= 1; x++) {
1591for (i=0; i<num_outputs; i++) {
1592if (entries[i].type == TYPE_GROUPED) {
1593continue;
1594}
1595// if type is TMDS, the prior output is ANALOG
1596// we always group ANALOG and TMDS
1597// if there is a TV output after TMDS, we group it to that channel as well
1598if (i && entries[i].type == 0x2) {
1599switch (x) {
1600case 0:
1601//printf("group channel 1\n");
1602channel1 |= ( 0x1 << entries[i].index);
1603entries[i].type = TYPE_GROUPED;
1604
1605if (entries[i-1].type == 0x0) {
1606channel1 |= ( 0x1 << entries[i-1].index);
1607entries[i-1].type = TYPE_GROUPED;
1608}
1609// group TV as well if there is one
1610if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
1611//printf("group tv1\n");
1612channel1 |= ( 0x1 << entries[i+1].index);
1613entries[i+1].type = TYPE_GROUPED;
1614}
1615break;
1616
1617case 1:
1618//printf("group channel 2 : %d\n", i);
1619channel2 |= ( 0x1 << entries[i].index);
1620entries[i].type = TYPE_GROUPED;
1621
1622if (entries[i - 1].type == 0x0) {
1623channel2 |= ( 0x1 << entries[i-1].index);
1624entries[i-1].type = TYPE_GROUPED;
1625}
1626// group TV as well if there is one
1627if ( ((i+1) < num_outputs) && (entries[i+1].type == 0x1) ) {
1628//printf("group tv2\n");
1629channel2 |= ( 0x1 << entries[i+1].index);
1630entries[i+1].type = TYPE_GROUPED;
1631}
1632break;
1633default:
1634break;
1635
1636}
1637break;
1638}
1639}
1640}
1641}
1642
1643// if we have left ungrouped outputs merge them to the empty channel
1644uint8_t *togroup;// = (channel1 ? (channel2 ? NULL : &channel2) : &channel1);
1645togroup = &channel2;
1646
1647for (i = 0; i < num_outputs; i++) {
1648if (entries[i].type != TYPE_GROUPED) {
1649//printf("%d not grouped\n", i);
1650if (togroup) {
1651*togroup |= ( 0x1 << entries[i].index);
1652}
1653entries[i].type = TYPE_GROUPED;
1654}
1655}
1656
1657if (channel1 > channel2) {
1658uint8_t buff = channel1;
1659channel1 = channel2;
1660channel2 = buff;
1661}
1662
1663default_NVCAP[6] = channel1;
1664default_NVCAP[8] = channel2;
1665
1666// patching HEADS
1667for (i = 0; i < num_outputs; i++) {
1668if (channel1 & (1 << i)) {
1669*entries[i].heads = 1;
1670} else if(channel2 & (1 << i)) {
1671*entries[i].heads = 2;
1672}
1673}
1674return (has_lvds ? PATCH_ROM_SUCCESS_HAS_LVDS : PATCH_ROM_SUCCESS);
1675}
1676
1677static char *get_nvidia_model(uint32_t device_id, uint32_t subsys_id)
1678{
1679int i, j;
1680
1681// First check in the plist, (for e.g this can override any hardcoded devices)
1682cardList_t * nvcard = FindCardWithIds(device_id, subsys_id);
1683if (nvcard) {
1684if (nvcard->model) {
1685return nvcard->model;
1686}
1687}
1688
1689//ErmaC added selector for Chameleon "old" style in System Profiler
1690if (getBoolForKey(kNvidiaGeneric, &showGeneric, &bootInfo->chameleonConfig)) {
1691verbose("\tNvidiaGeneric = Yes\n");
1692
1693for (i = 1; i < (sizeof(nvidia_card_generic) / sizeof(nvidia_card_generic[0])); i++) {
1694if (nvidia_card_generic[i].device == device_id) {
1695return nvidia_card_generic[i].name;
1696}
1697}
1698return nvidia_card_generic[0].name;
1699}
1700
1701// Then check the exceptions table
1702if (subsys_id) {
1703for (i = 0; i < (sizeof(nvidia_card_exceptions) / sizeof(nvidia_card_exceptions[0])); i++) {
1704if ((nvidia_card_exceptions[i].device == device_id) && (nvidia_card_exceptions[i].subdev == subsys_id)){
1705return nvidia_card_exceptions[i].name;
1706break;
1707}
1708}
1709}
1710
1711// At last try the generic names
1712for (i = 1; i < (sizeof(nvidia_card_generic) / sizeof(nvidia_card_generic[0])); i++) {
1713 if (nvidia_card_generic[i].device == device_id) {
1714if (subsys_id) {
1715for (j = 0; j < (sizeof(nvidia_card_vendors) / sizeof(nvidia_card_vendors[0])); j++) {
1716if (nvidia_card_vendors[j].device == (subsys_id & 0xffff0000)) {
1717snprintf(generic_name, 128, "%s %s", // sizeof(generic_name), "%s %s",
1718nvidia_card_vendors[j].name, nvidia_card_generic[i].name);
1719return &generic_name[0];
1720}
1721}
1722}
1723return nvidia_card_generic[i].name;
1724}
1725}
1726return nvidia_card_generic[0].name;
1727}
1728
1729static uint32_t load_nvidia_bios_file(const char *filename, uint8_t **buf)
1730{
1731int fd;
1732int size;
1733
1734if ((fd = open_bvdev("bt(0,0)", filename, 0)) < 0) {
1735return 0;
1736}
1737
1738size = file_size(fd);
1739
1740if (size) {
1741*buf = malloc(size);
1742size = read(fd, (char *)buf, size);
1743}
1744close(fd);
1745
1746return size > 0 ? size : 0;
1747}
1748
1749static int devprop_add_nvidia_template(struct DevPropDevice *device)
1750{
1751char tmp[16];
1752
1753if (!device)
1754return 0;
1755
1756if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_0))
1757return 0;
1758if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_0))
1759return 0;
1760if (!DP_ADD_TEMP_VAL(device, nvidia_name_0))
1761return 0;
1762if (!DP_ADD_TEMP_VAL(device, nvidia_compatible_1))
1763return 0;
1764if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_1))
1765return 0;
1766if (!DP_ADD_TEMP_VAL(device, nvidia_name_1))
1767return 0;
1768if (devices_number == 1) {
1769if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_parent))
1770return 0;
1771} else {
1772if (!DP_ADD_TEMP_VAL(device, nvidia_device_type_child))
1773return 0;
1774}
1775
1776// Rek : Dont use sprintf return, it does not WORK !! our custom sprintf() always return 0!
1777// len = sprintf(tmp, "Slot-%x", devices_number);
1778snprintf(tmp, sizeof(tmp), "Slot-%x",devices_number);
1779devprop_add_value(device, "AAPL,slot-name", (uint8_t *) tmp, strlen(tmp));
1780devices_number++;
1781
1782return 1;
1783}
1784
1785unsigned long long mem_detect(volatile uint8_t *regs, uint8_t nvCardType, pci_dt_t *nvda_dev, uint32_t device_id, uint32_t subsys_id)
1786{
1787unsigned long long vram_size = 0;
1788
1789// First check if any value exist in the plist
1790cardList_t * nvcard = FindCardWithIds(device_id, subsys_id);
1791if (nvcard)
1792{
1793if (nvcard->videoRam > 0)
1794{
1795vram_size = nvcard->videoRam * 1024 * 1024;
1796
1797return vram_size;
1798}
1799}
1800
1801// Then, Workaround for 9600M GT, GT 210/420/430/440/525M/540M & GTX 560M
1802switch (nvda_dev->device_id)
1803{
1804case 0x0647: // 9600M GT 0647
1805vram_size = 512*1024*1024;
1806break;
1807case 0x0649:// 9600M GT 0649
1808// 10DE06491043202D 1GB VRAM
1809if (((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id) == 0x1043202D )
1810{
1811vram_size = 1024*1024*1024;
1812}
1813break;
1814case 0x0A65: // GT 210
1815case 0x0DE0: // GT 440
1816case 0x0DE1: // GT 430
1817case 0x0DE2: // GT 420
1818case 0x0DEC: // GT 525M 0DEC
1819vram_size = 1024*1024*1024;
1820break;
1821case 0x0DE9: // GT 630M
1822// 10DE0DE9103C181D 1GB VRAM
1823if (((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id) == 0x103C181D )
1824{
1825vram_size = 1024*1024*1024;
1826}
1827break;
1828case 0x0DF4: // GT 540M
1829case 0x0DF5: // GT 525M 0DF5
1830vram_size = 1024*1024*1024;
1831break;
1832case 0x0F00:// GT 630
1833// 10DE0F0014583544 2GB VRAM
1834//if (((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id) == 0x14583544 )
1835//{
1836vram_size = -2147483648UL;//2147483648;
1837//}
1838break;
1839case 0x11C6:// GTX650TI 11C6
1840// 10DE11C61043842A 1GB VRAM
1841if (((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id) == 0x1043842A )
1842{
1843vram_size = 1024*1024*1024;
1844}
1845break;
1846case 0x1251: // GTX 560M
1847vram_size = 1536*1024*1024;
1848break;
1849default:
1850break;
1851}
1852
1853if (!vram_size){ // Finally, if vram_size still not set do the calculation with our own method
1854if (nvCardType < NV_ARCH_50) {
1855vram_size = REG32(NV04_PFB_FIFO_DATA);
1856vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
1857} else if (nvCardType < NV_ARCH_C0) {
1858vram_size = REG32(NV04_PFB_FIFO_DATA);
1859vram_size |= (vram_size & 0xff) << 32;
1860vram_size &= 0xffffffff00ll;
1861} else { // >= NV_ARCH_C0
1862vram_size = REG32(NVC0_MEM_CTRLR_RAM_AMOUNT) << 20;
1863vram_size *= REG32(NVC0_MEM_CTRLR_COUNT);
1864}
1865}
1866
1867return vram_size;
1868}
1869
1870static bool checkNvRomSig(uint8_t * aRom){
1871return aRom != NULL && (aRom[0] == 0x55 && aRom[1] == 0xaa);
1872}
1873
1874bool setup_nvidia_devprop(pci_dt_t *nvda_dev)
1875{
1876struct DevPropDevice*device = NULL;
1877char*devicepath = NULL;
1878option_rom_pci_header_t*rom_pci_header;
1879volatile uint8_t*regs;
1880uint8_t*rom = NULL;
1881uint8_t*nvRom;
1882uint8_tnvCardType = 0;
1883unsigned long longvideoRam = 0;
1884uint32_tnvBiosOveride;
1885uint32_tbar[7];
1886uint32_tboot_display = 0;
1887intnvPatch = 0;
1888intlen;
1889charbiosVersion[64];
1890charnvFilename[64];
1891charkNVCAP[12];
1892char*model = NULL;
1893const char*value;
1894booldoit;
1895
1896fill_card_list();
1897
1898devicepath = get_pci_dev_path(nvda_dev);
1899bar[0] = pci_config_read32(nvda_dev->dev.addr, 0x10 );
1900regs = (uint8_t *) (bar[0] & ~0x0f);
1901
1902// get card type
1903nvCardType = (REG32(0) >> 20) & 0x1ff;
1904
1905model = get_nvidia_model(((nvda_dev->vendor_id << 16) | nvda_dev->device_id),((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id));
1906
1907// Amount of VRAM in kilobytes
1908videoRam = mem_detect(regs, nvCardType, nvda_dev,((nvda_dev->vendor_id << 16) | nvda_dev->device_id),((nvda_dev->subsys_id.subsys.vendor_id << 16) | nvda_dev->subsys_id.subsys.device_id) );
1909
1910snprintf(nvFilename, sizeof(nvFilename), "/Extra/%04x_%04x.rom", (uint16_t)nvda_dev->vendor_id, (uint16_t)nvda_dev->device_id);
1911
1912if (getBoolForKey(kUseNvidiaROM, &doit, &bootInfo->chameleonConfig) && doit)
1913{
1914verbose("Looking for nvidia video bios file %s\n", nvFilename);
1915nvBiosOveride = load_nvidia_bios_file(nvFilename, &rom);
1916
1917if (nvBiosOveride > 0) {
1918verbose("Using nVidia Video BIOS File %s (%d Bytes)\n", nvFilename, nvBiosOveride);
1919DBG("%s Signature 0x%02x%02x %d bytes\n", nvFilename, rom[0], rom[1], nvBiosOveride);
1920} else {
1921printf("ERROR: unable to open nVidia Video BIOS File %s\n", nvFilename);
1922free(rom);
1923return false;
1924}
1925} else {
1926rom = malloc(NVIDIA_ROM_SIZE);
1927// Otherwise read bios from card
1928nvBiosOveride = 0;
1929
1930// PROM first
1931// Enable PROM access
1932(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED;
1933nvRom = (uint8_t*)&regs[NV_PROM_OFFSET];
1934
1935// Valid Signature ?
1936if (checkNvRomSig(nvRom)) {
1937bcopy((uint8_t *)nvRom, rom, NVIDIA_ROM_SIZE);
1938DBG("PROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
1939} else {
1940
1941// disable PROM access
1942(REG32(NV_PBUS_PCI_NV_20)) = NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED;
1943
1944//PRAM next
1945nvRom = (uint8_t*)&regs[NV_PRAMIN_OFFSET];
1946
1947if(checkNvRomSig(nvRom)) {
1948bcopy((uint32_t *)nvRom, rom, NVIDIA_ROM_SIZE);
1949DBG("PRAM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
1950} else {
1951// 0xC0000 last
1952bcopy((char *)0xc0000, rom, NVIDIA_ROM_SIZE);
1953
1954// Valid Signature ?
1955if (!checkNvRomSig(rom)) {
1956printf("ERROR: Unable to locate nVidia Video BIOS\n");
1957return false;
1958} else {
1959 DBG("ROM Address 0x%x Signature 0x%02x%02x\n", nvRom, rom[0], rom[1]);
1960 }
1961 }//end PRAM check
1962 }//end PROM check
1963 }//end load rom from bios
1964
1965if ((nvPatch = patch_nvidia_rom(rom)) == PATCH_ROM_FAILED) {
1966printf("ERROR: nVidia ROM Patching Failed!\n");
1967free(rom);
1968//return false;
1969}
1970
1971rom_pci_header = (option_rom_pci_header_t*)(rom + *(uint16_t *)&rom[24]);
1972
1973// check for 'PCIR' sig
1974if (rom_pci_header->signature == 0x50434952) {
1975if (rom_pci_header->device_id != nvda_dev->device_id) {
1976// Get Model from the OpROM
1977model = get_nvidia_model(((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id), 0);
1978
1979// Get VRAM again
1980videoRam = mem_detect(regs, nvCardType, nvda_dev, ((rom_pci_header->vendor_id << 16) | rom_pci_header->device_id), 0);
1981
1982} else {
1983printf("nVidia incorrect PCI ROM signature: 0x%x\n", rom_pci_header->signature);
1984}
1985}
1986
1987verbose("%s %dMB NV%02x [%04x:%04x]-[%04x:%04x] :: %s device number: %d\n",
1988model, (uint32_t)(videoRam / 1024 / 1024),
1989(REG32(0) >> 20) & 0x1ff, nvda_dev->vendor_id, nvda_dev->device_id,
1990nvda_dev->subsys_id.subsys.vendor_id, nvda_dev->subsys_id.subsys.device_id,
1991devicepath, devices_number);
1992
1993if (!string) {
1994string = devprop_create_string();
1995}
1996device = devprop_add_device(string, devicepath);
1997
1998/* FIXME: for primary graphics card only */
1999boot_display = 1;
2000if (devices_number == 1) {
2001devprop_add_value(device, "@0,AAPL,boot-display", (uint8_t*)&boot_display, 4);
2002}
2003
2004if (nvPatch == PATCH_ROM_SUCCESS_HAS_LVDS) {
2005uint8_t built_in = 0x01;
2006devprop_add_value(device, "@0,built-in", &built_in, 1);
2007}
2008
2009// get bios version
2010const int MAX_BIOS_VERSION_LENGTH = 32;
2011char* version_str = (char*)malloc(MAX_BIOS_VERSION_LENGTH);
2012
2013memset(version_str, 0, MAX_BIOS_VERSION_LENGTH);
2014
2015int i, version_start;
2016int crlf_count = 0;
2017
2018// only search the first 384 bytes
2019for (i = 0; i < 0x180; i++) {
2020if (rom[i] == 0x0D && rom[i+1] == 0x0A) {
2021crlf_count++;
2022// second 0x0D0A was found, extract bios version
2023if (crlf_count == 2) {
2024if (rom[i-1] == 0x20) i--; // strip last " "
2025
2026for (version_start = i; version_start > (i-MAX_BIOS_VERSION_LENGTH); version_start--) {
2027// find start
2028if (rom[version_start] == 0x00) {
2029version_start++;
2030
2031// strip "Version "
2032if (strncmp((const char*)rom+version_start, "Version ", 8) == 0) {
2033version_start += 8;
2034}
2035
2036strncpy(version_str, (const char*)rom+version_start, i-version_start);
2037break;
2038}
2039}
2040break;
2041}
2042}
2043}
2044
2045snprintf(biosVersion, sizeof(biosVersion), "%s", (nvBiosOveride > 0) ? nvFilename : version_str);
2046snprintf(kNVCAP, sizeof(kNVCAP), "NVCAP_%04x", nvda_dev->device_id);
2047
2048if (getValueForKey(kNVCAP, &value, &len, &bootInfo->chameleonConfig) && len == NVCAP_LEN * 2) {
2049uint8_t new_NVCAP[NVCAP_LEN];
2050
2051if (hex2bin(value, new_NVCAP, NVCAP_LEN) == 0) {
2052verbose("Using user supplied NVCAP for %s :: %s\n", model, devicepath);
2053memcpy(default_NVCAP, new_NVCAP, NVCAP_LEN);
2054}
2055}
2056
2057if (getValueForKey(kDcfg0, &value, &len, &bootInfo->chameleonConfig) && len == DCFG0_LEN * 2) {
2058uint8_t new_dcfg0[DCFG0_LEN];
2059
2060if (hex2bin(value, new_dcfg0, DCFG0_LEN) == 0) {
2061memcpy(default_dcfg_0, new_dcfg0, DCFG0_LEN);
2062
2063verbose("Using user supplied @0,display-cfg\n");
2064printf("@0,display-cfg: %02x%02x%02x%02x\n",
2065 default_dcfg_0[0], default_dcfg_0[1], default_dcfg_0[2], default_dcfg_0[3]);
2066}
2067}
2068
2069if (getValueForKey(kDcfg1, &value, &len, &bootInfo->chameleonConfig) && len == DCFG1_LEN * 2) {
2070uint8_t new_dcfg1[DCFG1_LEN];
2071
2072if (hex2bin(value, new_dcfg1, DCFG1_LEN) == 0) {
2073memcpy(default_dcfg_1, new_dcfg1, DCFG1_LEN);
2074
2075verbose("Using user supplied @1,display-cfg\n");
2076printf("@1,display-cfg: %02x%02x%02x%02x\n",
2077 default_dcfg_1[0], default_dcfg_1[1], default_dcfg_1[2], default_dcfg_1[3]);
2078}
2079}
2080
2081#if DEBUG_NVCAP
2082printf("NVCAP: %02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x-%02x%02x%02x%02x\n",
2083default_NVCAP[0], default_NVCAP[1], default_NVCAP[2], default_NVCAP[3],
2084default_NVCAP[4], default_NVCAP[5], default_NVCAP[6], default_NVCAP[7],
2085default_NVCAP[8], default_NVCAP[9], default_NVCAP[10], default_NVCAP[11],
2086default_NVCAP[12], default_NVCAP[13], default_NVCAP[14], default_NVCAP[15],
2087default_NVCAP[16], default_NVCAP[17], default_NVCAP[18], default_NVCAP[19]);
2088#endif
2089
2090devprop_add_nvidia_template(device);
2091devprop_add_value(device, "NVCAP", default_NVCAP, NVCAP_LEN);
2092devprop_add_value(device, "NVPM", default_NVPM, NVPM_LEN);
2093devprop_add_value(device, "VRAM,totalsize", (uint8_t*)&videoRam, 4);
2094devprop_add_value(device, "model", (uint8_t*)model, strlen(model) + 1);
2095devprop_add_value(device, "rom-revision", (uint8_t*)biosVersion, strlen(biosVersion) + 1);
2096devprop_add_value(device, "@0,display-cfg", default_dcfg_0, DCFG0_LEN);
2097devprop_add_value(device, "@1,display-cfg", default_dcfg_1, DCFG1_LEN);
2098
2099/******************** Added Marchrius.**********************/
2100// For the AppleBacklightDisplay //
2101/***********************************************************/
2102if (getBoolForKey(kEnableBacklight, &doit, &bootInfo->chameleonConfig) && doit){
2103uint8_t AAPL_value[] = {0x01, 0x00, 0x00, 0x00}; //Is the same for all
2104devprop_add_value(device, "AAPL,HasPanel", AAPL_value, 4);
2105devprop_add_value(device, "AAPL,Haslid", AAPL_value, 4);
2106devprop_add_value(device, "AAPL,backlight-control", AAPL_value, 4);
2107devprop_add_value(device, "@0,backlight-control", AAPL_value, 4);
2108}
2109/************************** End ****************************/
2110
2111/***********************************************************/
2112// For the DualLink //
2113/***********************************************************/
2114if (getBoolForKey(kEnableDualLink, &doit, &bootInfo->chameleonConfig) && doit) {
2115uint8_t AAPL00_value[] = {0x01, 0x00, 0x00, 0x00};
2116devprop_add_value(device, "AAPL00,DualLink", AAPL00_value, 4);
2117}
2118/************************** End ****************************/
2119
2120/************************ HDMI Audio ***********************/
2121doit = false;
2122//http://forge.voodooprojects.org/p/chameleon/issues/67/
2123if(getBoolForKey(kEnableHDMIAudio, &doit, &bootInfo->chameleonConfig) && doit) {
2124static uint8_t connector_type_1[]= {0x00, 0x08, 0x00, 0x00};
2125devprop_add_value(device, "@0,connector-type",connector_type_1, 4);
2126devprop_add_value(device, "@1,connector-type",connector_type_1, 4);
2127devprop_add_value(device, "@2,connector-type",connector_type_1, 4);
2128devprop_add_value(device, "@3,connector-type",connector_type_1, 4);
2129}
2130/************************ End Audio *************************/
2131
2132if (getBoolForKey(kVBIOS, &doit, &bootInfo->chameleonConfig) && doit) {
2133devprop_add_value(device, "vbios", rom, (nvBiosOveride > 0) ? nvBiosOveride : (rom[2] * 512));
2134}
2135
2136stringdata = malloc(sizeof(uint8_t) * string->length);
2137memcpy(stringdata, (uint8_t*)devprop_generate_string(string), string->length);
2138stringlength = string->length;
2139
2140free(version_str);
2141free(rom);
2142return true;
2143}
2144

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