| 1 | /*␊ |
| 2 | * platform.h␊ |
| 3 | * AsereBLN: reworked and extended␊ |
| 4 | *␊ |
| 5 | */␊ |
| 6 | ␊ |
| 7 | #ifndef __LIBSAIO_PLATFORM_H␊ |
| 8 | #define __LIBSAIO_PLATFORM_H␊ |
| 9 | ␊ |
| 10 | //#include "libsaio.h"␊ |
| 11 | ␊ |
| 12 | extern bool platformCPUFeature(uint32_t);␊ |
| 13 | extern void scan_platform(void);␊ |
| 14 | extern void dumpPhysAddr(const char * title, void * a, int len);␊ |
| 15 | ␊ |
| 16 | /* CPUID index into cpuid_raw */␊ |
| 17 | #define CPUID_0␉␉␉␉0␊ |
| 18 | #define CPUID_1␉␉␉␉1␊ |
| 19 | #define CPUID_2␉␉␉␉2␊ |
| 20 | #define CPUID_3␉␉␉␉3␊ |
| 21 | #define CPUID_4␉␉␉␉4␊ |
| 22 | #define CPUID_5␉␉␉␉5␊ |
| 23 | #define CPUID_6␉␉␉␉6␊ |
| 24 | #define CPUID_80␉␉␉7␊ |
| 25 | #define CPUID_81␉␉␉8␊ |
| 26 | #define CPUID_85␉␉␉9␊ |
| 27 | #define CPUID_86␉␉␉10␊ |
| 28 | #define CPUID_87␉␉␉11␊ |
| 29 | #define CPUID_88␉␉␉12␊ |
| 30 | #define CPUID_81E␉␉␉13␊ |
| 31 | #define CPUID_MAX␉␉␉14␊ |
| 32 | ␊ |
| 33 | #define CPUID_MODEL_ANY␉␉␉0x00␊ |
| 34 | #define CPUID_MODEL_UNKNOWN␉␉0x01␊ |
| 35 | #define CPUID_MODEL_PRESCOTT␉␉0x03␉␉␉// Celeron D, Pentium 4 (90nm)␊ |
| 36 | #define CPUID_MODEL_NOCONA␉␉0x04␉␉␉// Xeon Nocona/Paxville, Irwindale (90nm)␊ |
| 37 | #define CPUID_MODEL_PRESLER␉␉0x06␉␉␉// Pentium 4, Pentium D (65nm)␊ |
| 38 | #define CPUID_MODEL_PENTIUM_M␉␉0x09␉␉␉// Banias Pentium M (130nm)␊ |
| 39 | #define CPUID_MODEL_DOTHAN␉␉0x0D␉␉␉// Dothan Pentium M, Celeron M (90nm)␊ |
| 40 | #define CPUID_MODEL_YONAH␉␉0x0E␉␉␉// Sossaman, Yonah␊ |
| 41 | #define CPUID_MODEL_MEROM␉␉0x0F␉␉␉// Allendale, Conroe, Kentsfield, Woodcrest, Clovertown, Tigerton, Merom␊ |
| 42 | #define CPUID_MODEL_CONROE␉␉0x16␉␉␉// Merom, Conroe (65nm), Celeron (45nm)␊ |
| 43 | #define CPUID_MODEL_PENRYN␉␉0x17␉␉␉// Wolfdale, Yorkfield, Harpertown, Penryn␊ |
| 44 | #define CPUID_MODEL_WOLFDALE␉␉0x17␉␉␉// Xeon 31xx, 33xx, 52xx, 54xx, Core 2 Quad 8xxx and 9xxx␊ |
| 45 | #define CPUID_MODEL_NEHALEM␉␉0x1A␉␉␉// Bloomfield. Nehalem-EP, Nehalem-WS, Gainestown␊ |
| 46 | #define CPUID_MODEL_ATOM␉␉0x1C␉␉␉// Pineview, Bonnell␊ |
| 47 | #define CPUID_MODEL_XEON_MP␉␉0x1D␉␉␉// MP 7400␊ |
| 48 | #define CPUID_MODEL_FIELDS␉␉0x1E␉␉␉// Core i7 and i5 Processor - Clarksfield, Lynnfield, Jasper Forest␊ |
| 49 | #define CPUID_MODEL_CLARKDALE␉␉0x1F␉␉␉// Core i7 and i5 Processor - Nehalem (Havendale, Auburndale)␊ |
| 50 | #define CPUID_MODEL_DALES␉␉0x25␉␉␉// Westmere Client - Clarkdale, Arrandale␊ |
| 51 | #define CPUID_MODEL_ATOM_SAN␉␉0x26␉␉␉// Lincroft␊ |
| 52 | #define CPUID_MODEL_LINCROFT␉␉0x27␉␉␉// Bonnell, penwell␊ |
| 53 | #define CPUID_MODEL_SANDYBRIDGE␉␉0x2A␉␉␉// Sandy Bridge␊ |
| 54 | #define CPUID_MODEL_WESTMERE␉␉0x2C␉␉␉// Gulftown, Westmere-EP, Westmere-WS␊ |
| 55 | #define CPUID_MODEL_JAKETOWN␉␉0x2D␉␉␉// Sandy Bridge-E, Sandy Bridge-EP␊ |
| 56 | #define CPUID_MODEL_NEHALEM_EX␉␉0x2E␉␉␉// Nehalem-EX Xeon - Beckton␊ |
| 57 | #define CPUID_MODEL_WESTMERE_EX␉␉0x2F␉␉␉// Westmere-EX Xeon - Eagleton␊ |
| 58 | #define CPUID_MODEL_CLOVERVIEW␉␉0x35␉␉␉// Atom Family Bonnell, cloverview␊ |
| 59 | #define CPUID_MODEL_ATOM_2000␉␉0x36␉␉␉// Cedarview / Saltwell␊ |
| 60 | #define CPUID_MODEL_ATOM_3700␉␉0x37␉␉␉// Atom E3000, Z3000 Atom Silvermont **BYT␊ |
| 61 | #define CPUID_MODEL_IVYBRIDGE␉␉0x3A␉␉␉// Ivy Bridge␊ |
| 62 | #define CPUID_MODEL_HASWELL␉␉0x3C␉␉␉// Haswell DT ex.i7 4790K␊ |
| 63 | #define CPUID_MODEL_HASWELL_U5␉␉0x3D␉␉␉// Haswell U5 5th generation Broadwell, Core M / Core-AVX2␊ |
| 64 | #define CPUID_MODEL_IVYBRIDGE_XEON␉0x3E␉␉␉// Ivy Bridge Xeon␊ |
| 65 | #define CPUID_MODEL_HASWELL_SVR␉␉0x3F␉␉␉// Haswell Server, Xeon E5-2600/1600 v3 (Haswell-E) **HSX␊ |
| 66 | //#define CPUID_MODEL_HASWELL_H␉␉0x??␉␉␉// Haswell H␊ |
| 67 | #define CPUID_MODEL_HASWELL_ULT␉␉0x45␉␉␉// Haswell ULT, 4th gen Core, Xeon E3-12xx v3 C8/C9/C10␊ |
| 68 | #define CPUID_MODEL_HASWELL_ULX␉␉0x46␉␉␉// Crystal Well, 4th gen Core, Xeon E3-12xx v3␊ |
| 69 | #define CPUID_MODEL_BROADWELL_HQ␉0x47␉␉␉// Broadwell BDW␊ |
| 70 | #define CPUID_MODEL_MERRIFIELD␉␉0x4A␉␉␉// Future Atom E3000, Z3000 silvermont / atom (Marrifield)␊ |
| 71 | #define CPUID_MODEL_BRASWELL␉␉0x4C␉␉␉// Atom (Braswell)␊ |
| 72 | #define CPUID_MODEL_AVOTON␉␉0x4D␉␉␉// Silvermont/Avoton Atom C2000 **AVN␊ |
| 73 | #define CPUID_MODEL_SKYLAKE␉␉0x4E␉␉␉// Future Core **SKL␊ |
| 74 | #define CPUID_MODEL_BRODWELL_SVR␉0x4F␉␉␉// Broadwell Server **BDX␊ |
| 75 | #define CPUID_MODEL_SKYLAKE_AVX␉␉0x55␉␉␉// Skylake with AVX-512 support.␊ |
| 76 | #define CPUID_MODEL_BRODWELL_MSVR␉0x56␉␉␉// Broadwell Micro Server, Future Xeon **BDX-DE␊ |
| 77 | #define CPUID_MODEL_KNIGHT␉␉0x57␉␉␉// Knights Landing␊ |
| 78 | #define CPUID_MODEL_ANNIDALE␉␉0x5A␉␉␉// Silvermont, Future Atom E3000, Z3000 (Annidale)␊ |
| 79 | #define CPUID_MODEL_GOLDMONT␉␉0x5C␊ |
| 80 | #define CPUID_MODEL_VALLEYVIEW␉␉0x5D␉␉␉// Silvermont, Future Atom E3000, Z3000␊ |
| 81 | #define CPUID_MODEL_SKYLAKE_S␉␉0x5E␉␉␉// Skylake **SKL␊ |
| 82 | #define CPUID_MODEL_CANNONLAKE␉␉0x66␊ |
| 83 | #define CPUID_MODEL_DENVERTON␉␉0x5F␉␉␉// Goldmont Microserver␊ |
| 84 | #define CPUID_MODEL_XEON_MILL␉␉0x85␉␉␉// Knights Mill␊ |
| 85 | #define CPUID_MODEL_KABYLAKE1␉␉0x8E␉␉␉// Kabylake Mobile␊ |
| 86 | #define CPUID_MODEL_KABYLAKE2␉␉0x9E␉␉␉// Kabylake Dektop␊ |
| 87 | ␊ |
| 88 | /* CPUID Vendor */␊ |
| 89 | #define␉CPUID_VID_INTEL␉␉␉"GenuineIntel"␊ |
| 90 | #define␉CPUID_VID_AMD␉␉␉"AuthenticAMD"␊ |
| 91 | ␊ |
| 92 | #define CPUID_VENDOR_INTEL␉␉0x756E6547␊ |
| 93 | #define CPUID_VENDOR_AMD␉␉0x68747541␊ |
| 94 | ␊ |
| 95 | /* This spells out "GenuineIntel". */␊ |
| 96 | //#define is_intel \␊ |
| 97 | // ebx == 0x756e6547 && ecx == 0x6c65746e && edx == 0x49656e69␊ |
| 98 | ␊ |
| 99 | /* This spells out "AuthenticAMD". */␊ |
| 100 | //#define is_amd \␊ |
| 101 | // ebx == 0x68747541 && ecx == 0x444d4163 && edx == 0x69746e65␊ |
| 102 | ␊ |
| 103 | /* Unknown CPU */␊ |
| 104 | #define CPU_STRING_UNKNOWN␉␉"Unknown CPU Typ"␊ |
| 105 | ␊ |
| 106 | //definitions from Apple XNU␊ |
| 107 | ␊ |
| 108 | /* CPU defines */␊ |
| 109 | #define bit(n)␉␉␉␉(1ULL << (n))␊ |
| 110 | #define bitmask(h,l)␉␉␉((bit(h) | (bit(h)-1)) & ~(bit(l)-1))␊ |
| 111 | #define bitfield(x,h,l)␉␉␉(((x) & bitmask(h,l)) >> l)␊ |
| 112 | #define hbit(n)␉␉␉␉(1ULL << ((n)+32))␊ |
| 113 | #define min(a,b)␉␉␉((a) < (b) ? (a) : (b))␊ |
| 114 | #define quad32(hi,lo)␉␉␉((((uint32_t)(hi)) << 16) | (((uint32_t)(lo)) & 0xFFFF))␊ |
| 115 | #define quad64(hi,lo)␉␉␉((((uint64_t)(hi)) << 32) | (((uint64_t)(lo)) & 0xFFFFFFFFUL))␊ |
| 116 | ␊ |
| 117 | /*␊ |
| 118 | * The CPUID_FEATURE_XXX values define 64-bit values␊ |
| 119 | * returned in %ecx:%edx to a CPUID request with %eax of 1: ␊ |
| 120 | */␊ |
| 121 | #define CPUID_FEATURE_FPU␉␉bit(0) /* Floating point unit on-chip */␊ |
| 122 | #define CPUID_FEATURE_VME␉␉bit(1) /* Virtual Mode Extension */␊ |
| 123 | #define CPUID_FEATURE_DE␉␉bit(2) /* Debugging Extension */␊ |
| 124 | #define CPUID_FEATURE_PSE␉␉bit(3) /* Page Size Extension */␊ |
| 125 | #define CPUID_FEATURE_TSC␉␉bit(4) /* Time Stamp Counter */␊ |
| 126 | #define CPUID_FEATURE_MSR␉␉bit(5) /* Model Specific Registers */␊ |
| 127 | #define CPUID_FEATURE_PAE␉␉bit(6) /* Physical Address Extension */␊ |
| 128 | #define CPUID_FEATURE_MCE␉␉bit(7) /* Machine Check Exception */␊ |
| 129 | #define CPUID_FEATURE_CX8␉␉bit(8) /* CMPXCHG8B */␊ |
| 130 | #define CPUID_FEATURE_APIC␉␉bit(9) /* On-chip APIC */␊ |
| 131 | #define CPUID_FEATURE_SEP␉␉bit(11) /* Fast System Call */␊ |
| 132 | #define CPUID_FEATURE_MTRR␉␉bit(12) /* Memory Type Range Register */␊ |
| 133 | #define CPUID_FEATURE_PGE␉␉bit(13) /* Page Global Enable */␊ |
| 134 | #define CPUID_FEATURE_MCA␉␉bit(14) /* Machine Check Architecture */␊ |
| 135 | #define CPUID_FEATURE_CMOV␉␉bit(15) /* Conditional Move Instruction */␊ |
| 136 | #define CPUID_FEATURE_PAT␉␉bit(16) /* Page Attribute Table */␊ |
| 137 | #define CPUID_FEATURE_PSE36␉␉bit(17) /* 36-bit Page Size Extension */␊ |
| 138 | #define CPUID_FEATURE_PSN␉␉bit(18) /* Processor Serial Number */␊ |
| 139 | #define CPUID_FEATURE_CLFSH␉␉bit(19) /* CLFLUSH Instruction supported */␊ |
| 140 | #define CPUID_FEATURE_DS␉␉bit(21) /* Debug Store */␊ |
| 141 | #define CPUID_FEATURE_ACPI␉␉bit(22) /* Thermal monitor and Clock Ctrl */␊ |
| 142 | #define CPUID_FEATURE_MMX␉␉bit(23) /* MMX supported */␊ |
| 143 | #define CPUID_FEATURE_FXSR␉␉bit(24) /* Fast floating pt save/restore */␊ |
| 144 | #define CPUID_FEATURE_SSE␉␉bit(25) /* Streaming SIMD extensions */␊ |
| 145 | #define CPUID_FEATURE_SSE2␉␉bit(26) /* Streaming SIMD extensions 2 */␊ |
| 146 | #define CPUID_FEATURE_SS␉␉bit(27) /* Self-Snoop */␊ |
| 147 | #define CPUID_FEATURE_HTT␉␉bit(28) /* Hyper-Threading Technology */␊ |
| 148 | #define CPUID_FEATURE_TM␉␉bit(29) /* Thermal Monitor (TM1) */␊ |
| 149 | #define CPUID_FEATURE_PBE␉␉bit(31) /* Pend Break Enable */␊ |
| 150 | ␊ |
| 151 | #define CPUID_FEATURE_SSE3␉␉hbit(0) /* Streaming SIMD extensions 3 */␊ |
| 152 | #define CPUID_FEATURE_PCLMULQDQ␉␉hbit(1) /* PCLMULQDQ Instruction */␊ |
| 153 | #define CPUID_FEATURE_DTES64␉␉hbit(2) /* 64-bit DS layout */␊ |
| 154 | #define CPUID_FEATURE_MONITOR␉␉hbit(3) /* Monitor/mwait */␊ |
| 155 | #define CPUID_FEATURE_DSCPL␉␉hbit(4) /* Debug Store CPL */␊ |
| 156 | #define CPUID_FEATURE_VMX␉␉hbit(5) /* VMX */␊ |
| 157 | #define CPUID_FEATURE_SMX␉␉hbit(6) /* SMX */␊ |
| 158 | #define CPUID_FEATURE_EST␉␉hbit(7) /* Enhanced SpeedsTep (GV3) */␊ |
| 159 | #define CPUID_FEATURE_TM2␉␉hbit(8) /* Thermal Monitor 2 */␊ |
| 160 | #define CPUID_FEATURE_SSSE3␉␉hbit(9) /* Supplemental SSE3 instructions */␊ |
| 161 | #define CPUID_FEATURE_CID␉␉hbit(10) /* L1 Context ID */␊ |
| 162 | #define CPUID_FEATURE_SEGLIM64␉␉hbit(11) /* 64-bit segment limit checking */␊ |
| 163 | #define CPUID_FEATURE_FMA␉␉hbit(12) /* Fused-Multiply-Add support */␊ |
| 164 | #define CPUID_FEATURE_CX16␉␉hbit(13) /* CmpXchg16b instruction */␊ |
| 165 | #define CPUID_FEATURE_xTPR␉␉hbit(14) /* Send Task PRiority msgs */␊ |
| 166 | #define CPUID_FEATURE_PDCM␉␉hbit(15) /* Perf/Debug Capability MSR */␊ |
| 167 | ␊ |
| 168 | #define CPUID_FEATURE_PCID␉␉hbit(17) /* ASID-PCID support */␊ |
| 169 | #define CPUID_FEATURE_DCA␉␉hbit(18) /* Direct Cache Access */␊ |
| 170 | #define CPUID_FEATURE_SSE4_1␉␉hbit(19) /* Streaming SIMD extensions 4.1 */␊ |
| 171 | #define CPUID_FEATURE_SSE4_2␉␉hbit(20) /* Streaming SIMD extensions 4.2 */␊ |
| 172 | #define CPUID_FEATURE_x2APIC␉␉hbit(21) /* Extended APIC Mode */␊ |
| 173 | #define CPUID_FEATURE_MOVBE␉␉hbit(22) /* MOVBE instruction */␊ |
| 174 | #define CPUID_FEATURE_POPCNT␉␉hbit(23) /* POPCNT instruction */␊ |
| 175 | #define CPUID_FEATURE_TSCTMR␉␉hbit(24) /* TSC deadline timer */␊ |
| 176 | #define CPUID_FEATURE_AES␉␉hbit(25) /* AES instructions */␊ |
| 177 | #define CPUID_FEATURE_XSAVE␉␉hbit(26) /* XSAVE instructions */␊ |
| 178 | #define CPUID_FEATURE_OSXSAVE␉␉hbit(27) /* XGETBV/XSETBV instructions */␊ |
| 179 | #define CPUID_FEATURE_AVX1_0␉␉hbit(28) /* AVX 1.0 instructions */␊ |
| 180 | #define CPUID_FEATURE_F16C␉␉hbit(29) /* Float16 convert instructions */␊ |
| 181 | #define CPUID_FEATURE_RDRAND␉␉hbit(30) /* RDRAND instruction */␊ |
| 182 | #define CPUID_FEATURE_VMM␉␉hbit(31) /* VMM (Hypervisor) present */␊ |
| 183 | ␊ |
| 184 | /*␊ |
| 185 | * Leaf 7, subleaf 0 additional features.␊ |
| 186 | * Bits returned in %ebx to a CPUID request with {%eax,%ecx} of (0x7,0x0}:␊ |
| 187 | */␊ |
| 188 | #define CPUID_LEAF7_FEATURE_RDWRFSGS␉bit(0)␉/* FS/GS base read/write */␊ |
| 189 | #define CPUID_LEAF7_FEATURE_TSCOFF␉bit(1)␉/* TSC thread offset */␊ |
| 190 | #define CPUID_LEAF7_FEATURE_BMI1␉bit(3)␉/* Bit Manipulation Instrs, set 1 */␊ |
| 191 | #define CPUID_LEAF7_FEATURE_HLE␉␉bit(4)␉/* Hardware Lock Elision*/␊ |
| 192 | #define CPUID_LEAF7_FEATURE_AVX2␉bit(5)␉/* AVX2 Instructions */␊ |
| 193 | #define CPUID_LEAF7_FEATURE_SMEP␉bit(7)␉/* Supervisor Mode Execute Protect */␊ |
| 194 | #define CPUID_LEAF7_FEATURE_BMI2␉bit(8)␉/* Bit Manipulation Instrs, set 2 */␊ |
| 195 | #define CPUID_LEAF7_FEATURE_ENFSTRG␉bit(9)␉/* ENhanced Fast STRinG copy */␊ |
| 196 | #define CPUID_LEAF7_FEATURE_INVPCID␉bit(10)␉/* INVPCID intruction, TDB */␊ |
| 197 | #define CPUID_LEAF7_FEATURE_RTM␉␉bit(11)␉/* TBD */␊ |
| 198 | ␊ |
| 199 | /*␊ |
| 200 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| 201 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000001: ␊ |
| 202 | */␊ |
| 203 | #define CPUID_EXTFEATURE_SYSCALL␉bit(11)␉/* SYSCALL/sysret */␊ |
| 204 | #define CPUID_EXTFEATURE_XD␉␉bit(20)␉/* eXecute Disable */␊ |
| 205 | ␊ |
| 206 | #define CPUID_EXTFEATURE_1GBPAGE␉bit(26)␉/* 1GB pages support */␊ |
| 207 | #define CPUID_EXTFEATURE_RDTSCP␉␉bit(27)␉/* RDTSCP */␊ |
| 208 | #define CPUID_EXTFEATURE_EM64T␉␉bit(29)␉/* Extended Mem 64 Technology */␊ |
| 209 | ␊ |
| 210 | ␊ |
| 211 | #define CPUID_EXTFEATURE_LAHF␉␉hbit(0)␉/* LAFH/SAHF instructions */␊ |
| 212 | ␊ |
| 213 | /*␊ |
| 214 | * The CPUID_EXTFEATURE_XXX values define 64-bit values␊ |
| 215 | * returned in %ecx:%edx to a CPUID request with %eax of 0x80000007: ␊ |
| 216 | */␊ |
| 217 | #define CPUID_EXTFEATURE_TSCI␉␉bit(8)␉/* TSC Invariant */␊ |
| 218 | ␊ |
| 219 | #define␉CPUID_CACHE_SIZE␉␉16␉/* Number of descriptor values */␊ |
| 220 | ␊ |
| 221 | #define CPUID_MWAIT_EXTENSION␉␉bit(0)␉/* enumeration of WMAIT extensions */␊ |
| 222 | #define CPUID_MWAIT_BREAK␉␉bit(1)␉/* interrupts are break events␉ */␊ |
| 223 | ␊ |
| 224 | //-- processor type -> p_type:␊ |
| 225 | #define PT_OEM␉␉␉␉0x00␉// Intel Original OEM Processor;␊ |
| 226 | #define PT_OD␉␉␉␉0x01 ␉// Intel Over Drive Processor;␊ |
| 227 | #define PT_DUAL␉␉␉␉0x02␉// Intel Dual Processor;␊ |
| 228 | #define PT_RES␉␉␉␉0x03␉// Intel Reserved;␊ |
| 229 | ␊ |
| 230 | /* Known MSR registers */␊ |
| 231 | #define MSR_IA32_PLATFORM_ID␉␉0x0017␊ |
| 232 | #define IA32_APIC_BASE␉␉␉0x001B /* used also for AMD */␊ |
| 233 | #define MSR_CORE_THREAD_COUNT␉␉0x0035␉/* limited use - not for Penryn or older */␊ |
| 234 | #define IA32_TSC_ADJUST␉␉␉0x003B␊ |
| 235 | #define MSR_IA32_BIOS_SIGN_ID␉␉0x008B␉/* microcode version */␊ |
| 236 | #define MSR_FSB_FREQ␉␉␉0x00CD␉/* limited use - not for i7 */␊ |
| 237 | #define␉MSR_PLATFORM_INFO␉␉0x00CE␉/* limited use - MinRatio for i7 but Max for Yonah␉*/␊ |
| 238 | ␊ |
| 239 | /* turbo for penryn */␊ |
| 240 | #define MSR_PKG_CST_CONFIG_CONTROL␉0x00E2␉␉// sandy and ivy␊ |
| 241 | #define MSR_PMG_IO_CAPTURE_BASE␉␉0x00E4␊ |
| 242 | #define IA32_MPERF␉␉␉0x00E7␉␉// TSC in C0 only␊ |
| 243 | #define IA32_APERF␉␉␉0x00E8␉␉// actual clocks in C0␊ |
| 244 | #define MSR_IA32_EXT_CONFIG␉␉0x00EE␉␉// limited use - not for i7␊ |
| 245 | #define MSR_FLEX_RATIO␉␉␉0x0194␉␉// limited use - not for Penryn or older␊ |
| 246 | ␉␉␉␉␉␉//see no value on most CPUs␊ |
| 247 | #define␉MSR_IA32_PERF_STATUS␉␉0x0198␊ |
| 248 | #define MSR_IA32_PERF_CONTROL␉␉0x0199␊ |
| 249 | #define MSR_IA32_CLOCK_MODULATION␉0x019A␊ |
| 250 | #define MSR_THERMAL_STATUS␉␉0x019C␊ |
| 251 | #define MSR_IA32_MISC_ENABLE␉␉0x01A0␊ |
| 252 | #define MSR_THERMAL_TARGET␉␉0x01A2␉␉// TjMax limited use - not for Penryn or older␊ |
| 253 | #define MSR_MISC_PWR_MGMT␉␉0x01AA␊ |
| 254 | #define MSR_TURBO_RATIO_LIMIT␉␉0x01AD␉␉// limited use - not for Penryn or older␊ |
| 255 | ␊ |
| 256 | #define IA32_ENERGY_PERF_BIAS␉␉0x01B0␊ |
| 257 | #define MSR_PACKAGE_THERM_STATUS␉0x01B1␊ |
| 258 | #define IA32_PLATFORM_DCA_CAP␉␉0x01F8␊ |
| 259 | #define MSR_POWER_CTL␉␉␉0x01FC␉␉// MSR 000001FC 0000-0000-0004-005F␊ |
| 260 | ␊ |
| 261 | // Nehalem (NHM) adds support for additional MSRs␊ |
| 262 | #define MSR_SMI_COUNT 0x034␊ |
| 263 | #define MSR_NHM_PLATFORM_INFO 0x0ce␊ |
| 264 | #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x0e2␊ |
| 265 | #define MSR_PKG_C3_RESIDENCY 0x3f8␊ |
| 266 | #define MSR_PKG_C6_RESIDENCY 0x3f9␊ |
| 267 | #define MSR_CORE_C3_RESIDENCY 0x3fc␊ |
| 268 | #define MSR_CORE_C6_RESIDENCY 0x3fd␊ |
| 269 | ␊ |
| 270 | // Sandy Bridge & JakeTown specific 'Running Average Power Limit' MSR's.␊ |
| 271 | #define MSR_RAPL_POWER_UNIT␉␉0x606␉␉// R/O␊ |
| 272 | //MSR 00000606 0000-0000-000A-1003␊ |
| 273 | #define MSR_PKGC3_IRTL␉␉␉0x60A␉␉// RW time limit to go C3␊ |
| 274 | // bit 15 = 1 -- the value valid for C-state PM␊ |
| 275 | #define MSR_PKGC6_IRTL␉␉␉0x60B␉␉// RW time limit to go C6␊ |
| 276 | //MSR 0000060B 0000-0000-0000-8854␊ |
| 277 | //Valid + 010=1024ns + 0x54=84mks␊ |
| 278 | #define MSR_PKGC7_IRTL␉␉␉0x60C␉␉// RW time limit to go C7␊ |
| 279 | //MSR 0000060C 0000-0000-0000-8854␊ |
| 280 | ␊ |
| 281 | // Sandy Bridge (SNB) adds support for additional MSRs␊ |
| 282 | #define MSR_PKG_C7_RESIDENCY␉␉0x3FA␊ |
| 283 | #define MSR_CORE_C7_RESIDENCY␉␉0x3FE␊ |
| 284 | #define MSR_PKG_C2_RESIDENCY␉␉0x60D␉␉// same as TSC but in C2 only␊ |
| 285 | ␊ |
| 286 | #define MSR_PKG_RAPL_POWER_LIMIT␉0x610␉␉//MSR 00000610 0000-A580-0000-8960␊ |
| 287 | #define MSR_PKG_ENERGY_STATUS␉␉0x611␉␉//MSR 00000611 0000-0000-3212-A857␊ |
| 288 | #define MSR_PKG_POWER_INFO␉␉0x614␉␉//MSR 00000614 0000-0000-01E0-02F8␊ |
| 289 | ␊ |
| 290 | // Sandy Bridge IA (Core) domain MSR's.␊ |
| 291 | #define MSR_PP0_POWER_LIMIT␉␉0x638␊ |
| 292 | #define MSR_PP0_ENERGY_STATUS␉␉0x639␊ |
| 293 | #define MSR_PP0_POLICY␉␉␉0x63A␊ |
| 294 | #define MSR_PP0_PERF_STATUS␉␉0x63B␊ |
| 295 | ␊ |
| 296 | // Sandy Bridge Uncore (IGPU) domain MSR's (Not on JakeTown).␊ |
| 297 | #define MSR_PP1_POWER_LIMIT␉␉0x640␊ |
| 298 | #define MSR_PP1_ENERGY_STATUS␉0x641␊ |
| 299 | #define MSR_PP1_POLICY␉␉␉0x642␊ |
| 300 | ␊ |
| 301 | // JakeTown only Memory MSR's.␊ |
| 302 | #define MSR_PKG_PERF_STATUS␉␉0x613 ␊ |
| 303 | #define MSR_DRAM_POWER_LIMIT␉ ␉0x618␊ |
| 304 | #define MSR_DRAM_ENERGY_STATUS␉␉0x619␊ |
| 305 | #define MSR_DRAM_PERF_STATUS␉␉0x61B␊ |
| 306 | #define MSR_DRAM_POWER_INFO␉␉0x61C␊ |
| 307 | ␊ |
| 308 | // Ivy Bridge␊ |
| 309 | #define MSR_CONFIG_TDP_NOMINAL␉␉0x648␊ |
| 310 | #define MSR_CONFIG_TDP_LEVEL1␉␉0x649␊ |
| 311 | #define MSR_CONFIG_TDP_LEVEL2␉␉0x64A␊ |
| 312 | #define MSR_CONFIG_TDP_CONTROL␉␉0x64B␉␉// write once to lock␊ |
| 313 | #define MSR_TURBO_ACTIVATION_RATIO␉0x64C␊ |
| 314 | ␊ |
| 315 | // Haswell (HSW) adds support for additional MSRs␊ |
| 316 | #define MSR_PKG_C8_RESIDENCY 0x630␊ |
| 317 | #define MSR_PKG_C9_RESIDENCY 0x631␊ |
| 318 | #define MSR_PKG_C10_RESIDENCY 0x632␊ |
| 319 | ␊ |
| 320 | // Skylake (SKL) adds support for additional MSRs␊ |
| 321 | #define MSR_PKG_WEIGHTED_CORE_C0_RES 0x658␊ |
| 322 | #define MSR_PKG_ANY_CORE_C0_RES 0x659␊ |
| 323 | #define MSR_PKG_ANY_GFXE_C0_RES 0x65A␊ |
| 324 | #define MSR_PKG_BOTH_CORE_GFXE_C0_RES 0x65B␊ |
| 325 | ␊ |
| 326 | /* AMD Defined MSRs */␊ |
| 327 | #define MSR_K6_EFER␉␉␉0xC0000080␉// extended feature register␊ |
| 328 | #define MSR_K6_STAR␉␉␉0xC0000081␉// legacy mode SYSCALL target␊ |
| 329 | #define MSR_K6_WHCR␉␉␉0xC0000082␉// long mode SYSCALL target␊ |
| 330 | #define MSR_K6_UWCCR␉␉␉0xC0000085␊ |
| 331 | #define MSR_K6_EPMR␉␉␉0xC0000086␊ |
| 332 | #define MSR_K6_PSOR␉␉␉0xC0000087␊ |
| 333 | #define MSR_K6_PFIR␉␉␉0xC0000088␊ |
| 334 | ␊ |
| 335 | #define MSR_K7_EVNTSEL0␉␉␉0xC0010000␊ |
| 336 | #define MSR_K7_PERFCTR0␉␉␉0xC0010004␊ |
| 337 | #define MSR_K7_HWCR␉␉␉0xC0010015␊ |
| 338 | #define MSR_K7_CLK_CTL␉␉␉0xC001001b␊ |
| 339 | #define MSR_K7_FID_VID_CTL␉␉0xC0010041␊ |
| 340 | ␊ |
| 341 | #define AMD_K8_PERF_STS 0xC0010042␊ |
| 342 | #define AMD_PSTATE_LIMIT 0xC0010061 // max enabled p-state (msr >> 4) & 7␊ |
| 343 | #define AMD_PSTATE_CONTROL 0xC0010062 // switch to p-state␊ |
| 344 | #define AMD_PSTATE0_STS 0xC0010064␊ |
| 345 | #define AMD_COFVID_STS 0xC0010071 // current p-state (msr >> 16) & 7␊ |
| 346 | ␊ |
| 347 | #define MSR_AMD_MPERF␉␉␉0x000000E7␊ |
| 348 | #define MSR_AMD_APERF␉␉␉0x000000E8␊ |
| 349 | ␊ |
| 350 | ␊ |
| 351 | #define DEFAULT_FSB␉␉␉100000 /* for now, hardcoding 100MHz for old CPUs */␊ |
| 352 | ␊ |
| 353 | // DFE: This constant comes from older xnu:␊ |
| 354 | #define CLKNUM␉␉␉␉1193182␉␉/* formerly 1193167 */␊ |
| 355 | ␊ |
| 356 | /* CPU Features */␊ |
| 357 | #define CPU_FEATURE_MMX␉␉␉0x00000001␉␉// MMX Instruction Set␊ |
| 358 | #define CPU_FEATURE_SSE␉␉␉0x00000002␉␉// SSE Instruction Set␊ |
| 359 | #define CPU_FEATURE_SSE2␉␉0x00000004␉␉// SSE2 Instruction Set␊ |
| 360 | #define CPU_FEATURE_SSE3␉␉0x00000008␉␉// SSE3 Instruction Set␊ |
| 361 | #define CPU_FEATURE_SSE41␉␉0x00000010␉␉// SSE41 Instruction Set␊ |
| 362 | #define CPU_FEATURE_SSE42␉␉0x00000020␉␉// SSE42 Instruction Set␊ |
| 363 | #define CPU_FEATURE_EM64T␉␉0x00000040␉␉// 64Bit Support␊ |
| 364 | #define CPU_FEATURE_HTT␉␉␉0x00000080␉␉// HyperThreading␊ |
| 365 | #define CPU_FEATURE_MOBILE␉␉0x00000100␉␉// Mobile CPU␊ |
| 366 | #define CPU_FEATURE_MSR␉␉␉0x00000200␉␉// MSR Support␊ |
| 367 | ␊ |
| 368 | /* SMBIOS Memory Types */ ␊ |
| 369 | #define SMB_MEM_TYPE_UNDEFINED␉␉0␊ |
| 370 | #define SMB_MEM_TYPE_OTHER␉␉1␊ |
| 371 | #define SMB_MEM_TYPE_UNKNOWN␉␉2␊ |
| 372 | #define SMB_MEM_TYPE_DRAM␉␉3␊ |
| 373 | #define SMB_MEM_TYPE_EDRAM␉␉4␊ |
| 374 | #define SMB_MEM_TYPE_VRAM␉␉5␊ |
| 375 | #define SMB_MEM_TYPE_SRAM␉␉6␊ |
| 376 | #define SMB_MEM_TYPE_RAM␉␉7␊ |
| 377 | #define SMB_MEM_TYPE_ROM␉␉8␊ |
| 378 | #define SMB_MEM_TYPE_FLASH␉␉9␊ |
| 379 | #define SMB_MEM_TYPE_EEPROM␉␉10␊ |
| 380 | #define SMB_MEM_TYPE_FEPROM␉␉11␊ |
| 381 | #define SMB_MEM_TYPE_EPROM␉␉12␊ |
| 382 | #define SMB_MEM_TYPE_CDRAM␉␉13␊ |
| 383 | #define SMB_MEM_TYPE_3DRAM␉␉14␊ |
| 384 | #define SMB_MEM_TYPE_SDRAM␉␉15␊ |
| 385 | #define SMB_MEM_TYPE_SGRAM␉␉16␊ |
| 386 | #define SMB_MEM_TYPE_RDRAM␉␉17␊ |
| 387 | #define SMB_MEM_TYPE_DDR␉␉18␊ |
| 388 | #define SMB_MEM_TYPE_DDR2␉␉19␊ |
| 389 | #define SMB_MEM_TYPE_FBDIMM␉␉20␊ |
| 390 | #define SMB_MEM_TYPE_DDR3␉␉24␉␉␉// Supported in 10.5.6+ AppleSMBIOS␊ |
| 391 | #define SMB_MEM_TYPE_DDR4␉␉26␊ |
| 392 | ␊ |
| 393 | /* Memory Configuration Types */ ␊ |
| 394 | #define SMB_MEM_CHANNEL_UNKNOWN␉␉0␊ |
| 395 | #define SMB_MEM_CHANNEL_SINGLE␉␉1␊ |
| 396 | #define SMB_MEM_CHANNEL_DUAL␉␉2␊ |
| 397 | #define SMB_MEM_CHANNEL_TRIPLE␉␉3␊ |
| 398 | ␊ |
| 399 | /* Maximum number of ram slots */␊ |
| 400 | #define MAX_RAM_SLOTS␉␉␉8␊ |
| 401 | ␊ |
| 402 | #define RAM_SLOT_ENUMERATOR␉␉{0, 2, 4, 1, 3, 5, 6, 8, 10, 7, 9, 11}␊ |
| 403 | ␊ |
| 404 | /* Maximum number of SPD bytes */␊ |
| 405 | #define MAX_SPD_SIZE␉␉␉256␊ |
| 406 | ␊ |
| 407 | /* Size of SMBIOS UUID in bytes */␊ |
| 408 | #define UUID_LEN␉␉␉16␊ |
| 409 | ␊ |
| 410 | typedef struct _RamSlotInfo_t␊ |
| 411 | {␊ |
| 412 | ␉uint32_t␉␉ModuleSize;␉␉␉// Size of Module in MB␊ |
| 413 | ␉uint32_t␉␉Frequency;␉␉␉// in Mhz␊ |
| 414 | ␉const char*␉␉Vendor;␊ |
| 415 | ␉const char*␉␉PartNo;␊ |
| 416 | ␉const char*␉␉SerialNo;␊ |
| 417 | ␉char*␉␉␉spd;␉␉␉␉// SPD Dump␊ |
| 418 | ␉bool␉␉␉InUse;␊ |
| 419 | ␉uint8_t␉␉␉Type;␊ |
| 420 | ␉uint8_t␉␉␉BankConnections;␉␉// table type 6, see (3.3.7)␊ |
| 421 | ␉uint8_t␉␉␉BankConnCnt;␊ |
| 422 | } RamSlotInfo_t;␊ |
| 423 | ␊ |
| 424 | //==============================================================================␊ |
| 425 | ␊ |
| 426 | typedef struct _PlatformInfo_t␊ |
| 427 | {␊ |
| 428 | ␉struct CPU {␊ |
| 429 | ␉␉uint32_t␉␉Features;␉␉// CPU Features like MMX, SSE2, VT, MobileCPU␊ |
| 430 | ␉␉uint32_t␉␉Vendor;␉␉␉// Vendor␊ |
| 431 | ␉␉uint32_t␉␉CoresPerPackage;␊ |
| 432 | ␉␉uint32_t␉␉LogicalPerPackage;␊ |
| 433 | ␉␉uint32_t␉␉Signature;␉␉// Processor Signature␊ |
| 434 | ␉␉uint32_t␉␉Stepping;␉␉// Stepping␊ |
| 435 | ␉␉uint32_t␉␉Model;␉␉␉// Model␊ |
| 436 | ␉␉//uint32_t␉␉Type;␉␉␉// Processor Type␊ |
| 437 | ␉␉uint32_t␉␉ExtModel;␉␉// Extended Model␊ |
| 438 | ␉␉uint32_t␉␉Family;␉␉␉// Family␊ |
| 439 | ␉␉uint32_t␉␉ExtFamily;␉␉// Extended Family␊ |
| 440 | ␉␉uint32_t␉␉NoCores;␉␉// No Cores per Package␊ |
| 441 | ␉␉uint32_t␉␉NoThreads;␉␉// Threads per Package␊ |
| 442 | ␉␉uint8_t␉␉␉MaxCoef;␉␉// Max Multiplier␊ |
| 443 | ␉␉uint8_t␉␉␉MaxDiv;␉␉␉// Min Multiplier␊ |
| 444 | ␉␉uint8_t␉␉␉CurrCoef;␉␉// Current Multiplier␊ |
| 445 | ␉␉uint8_t␉␉␉CurrDiv;␊ |
| 446 | ␉␉uint64_t␉␉TSCFrequency;␉␉// TSC Frequency Hz␊ |
| 447 | ␉␉uint64_t␉␉FSBFrequency;␉␉// FSB Frequency Hz␊ |
| 448 | ␉␉uint64_t␉␉CPUFrequency;␉␉// CPU Frequency Hz␊ |
| 449 | ␉␉uint32_t␉␉MaxRatio;␉␉// Max Bus Ratio␊ |
| 450 | ␉␉uint32_t␉␉MinRatio;␉␉// Min Bus Ratio␊ |
| 451 | ␉␉char␉␉␉BrandString[48];␉// 48 Byte Branding String␊ |
| 452 | ␉␉uint32_t␉␉CPUID[CPUID_MAX][4];␉// CPUID 0..4, 80..81 Raw Values␊ |
| 453 | ␊ |
| 454 | ␉} CPU;␊ |
| 455 | ␊ |
| 456 | ␉struct DMI␊ |
| 457 | ␉{␊ |
| 458 | ␉␉int␉␉␉MaxMemorySlots;␉␉// number of memory slots populated by SMBIOS␊ |
| 459 | ␉␉int␉␉␉CntMemorySlots;␉␉// number of memory slots counted␊ |
| 460 | ␉␉int␉␉␉MemoryModules;␉␉// number of memory modules installed␊ |
| 461 | ␉␉int␉␉␉DIMM[MAX_RAM_SLOTS];␉// Information and SPD mapping for each slot␊ |
| 462 | ␉} DMI;␊ |
| 463 | ␊ |
| 464 | ␉struct RAM␊ |
| 465 | ␉{␊ |
| 466 | ␉␉uint64_t␉␉Frequency;␉␉// Ram Frequency␊ |
| 467 | ␉␉uint32_t␉␉Divider;␉␉// Memory divider␊ |
| 468 | ␉␉uint8_t␉␉␉CAS;␉␉␉// CAS 1/2/2.5/3/4/5/6/7␊ |
| 469 | ␉␉uint8_t␉␉␉TRC;␊ |
| 470 | ␉␉uint8_t␉␉␉TRP;␊ |
| 471 | ␉␉uint8_t␉␉␉RAS;␊ |
| 472 | ␉␉uint8_t␉␉␉Channels;␉␉// Channel Configuration Single,Dual, Triple or Quad␊ |
| 473 | ␉␉uint8_t␉␉␉NoSlots;␉␉// Maximum no of slots available␊ |
| 474 | ␉␉uint8_t␉␉␉Type;␉␉␉// Standard SMBIOS v2.5 Memory Type␊ |
| 475 | ␉␉RamSlotInfo_t␉DIMM[MAX_RAM_SLOTS];␉␉// Information about each slot␊ |
| 476 | ␉} RAM;␊ |
| 477 | ␊ |
| 478 | ␉uint8_t␉␉␉␉Type;␉␉␉// system-type: 1=Desktop, 2=Portable, 3=Workstation... according ACPI2.0 (FACP: PM_Profile)␊ |
| 479 | ␉uint8_t␉␉␉␉*UUID;␉␉␉// system-id (SMBIOS Table 1: system uuid)␊ |
| 480 | ␉uint32_t␉␉␉HWSignature;␉␉// machine-signature (FACS: Hardware Signature)␊ |
| 481 | } PlatformInfo_t;␊ |
| 482 | ␊ |
| 483 | extern PlatformInfo_t Platform;␊ |
| 484 | ␊ |
| 485 | #endif /* !__LIBSAIO_PLATFORM_H */␊ |
| 486 | |
